ETC CXA7005R

CXA7005R
LCD Driver
Description
The CXA7005R is a driver IC developed for use
with Sony polycrystalline silicon TFT LCD panels. It
supports 10-bit digital input, and the input data is
demultiplexed into 6 phases and output. The
CXA7005R can directly drive an LCD panel, and the
VCOM setting circuit and precharge pulse waveform
generator are also on-chip.
48 pin LQFP (Plastic)
Features
• Supports 10-bit input
• Low output deviation
• Various adjustment functions using a 3-wire serial interface
• Supports signals up to XGA
• Supports dot and line inversion
• VCOM voltage generation circuit
• Precharge pulse waveform generation circuit
Applications
LCD projectors and other video equipment
Absolute Maximum Ratings (VSS = 0V)
• Supply voltage
VCC
16
V
VDD
5
V
• Operating temperature
Topr
–20 to +70
°C
• Storage temperature
Tstg
–65 to +150 °C
• Allowable power dissipation PD
1200
mW
Recommended Operating Conditions
• Supply voltage
VCC
15.0 to 15.5
VDD
3.0 to 3.6
• Operating temperature
Topr
–20 to +70
V
V
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E03426A35
CXA7005R
DGND
VDD
CLK
FRP
PRG
DIRC
STATUS
FRINV
AGND
AGND
AGND
VCC
Block Diagram
36
35
34
33
32
31
30
29
28
27
26
25
D_IN9 37
24 SID_OUT
TG
SID
D_IN8 38
23 PVCC
D/A
D_IN7 39
22 SIG_OUT1
D/A
Driver
D_IN6 40
21 SIG_OUT2
D/A
Driver
D_IN5 41
20 SIG_OUT3
D_IN4 42
D/A
Driver
D/A
Driver
D/A
Driver
19 PGND
Digital
D_IN3 43
18 PGND
D_IN2 44
17 SIG_OUT4
D_IN1 45
16 SIG_OUT5
D/A
D_IN0 46
Driver
15 SIG_OUT6
DGND 47
14 PVCC
REF
DC_GEN
SIF
SENB
SCLK
SDAT
ADDR0
7
8
9
10
11
12
REF_OUT
6
VCC
5
REF_IN
4
AGND
3
AGND
2
ADDR1
1
DGND
13 VCOM_OUT
DGND
DGND 48
–2–
CXA7005R
Pin Description
Pin
No.
Symbol
I/O
Standard
voltage level
Equivalent circuit
Description
VDD
3
SENB
I
High: ≥ 2.0V
Low: ≤ 0.8V
Enable input for 3-wire
serial interface.
Data is written only while
this pin is low.
1k
3
GND
VDD
4
SCLK
I
High: ≥ 2.0V
Low: ≤ 0.8V
Clock input for 3-wire
serial interface.
Supports a clock from
100kHz to 1MHz.
1k
4
GND
VDD
5
SDAT
I
High: ≥ 2.0V
Low: ≤ 0.8V
1k
Data input for 3-wire
serial interface.
5
GND
VDD
40k
6
7
ADDR0
ADDR1
I
IC address setting for
3-wire serial interface.
Addresses from 0h to 7h
can be set by changing
this setting.
20k
High = VDD
Low = GND
6
7
40k
GND
VCC
8k
10
REF_IN
I
6.0V
8k
16k
16k
10
145
2k
36k
25µ
GND
–3–
12.5µ
Reference voltage
(signal center) input.
When using multiple
CXA7005Rs, connect to
REF_OUT that differs
from the reference.
CXA7005R
Pin
No.
Symbol
I/O
Standard
voltage level
Equivalent circuit
Description
VCC
2k
12
REF_OUT
O
6.0V
12
Signal center voltage
(inversion folded voltage)
output.
When using multiple
CXA7005Rs, connect to
REF_IN through a 1kΩ
resistor.
13
Common voltage output
of LCD panel.
Adjustment is possible
by the 3-wire serial
interface setting.
145
124k
2k
GND
VCC
1k
500
13
VCOM_OUT O
5.5 to 7.5V
145
500
1k
GND
VCC
15
16
17
20
21
22
PVCC
400
SIG_OUT6
to
SIG_OUT1
1.5 to 13.5V
16 21
17 22
400
GND
PGND
VCC
PVCC
400
24
15 20
400
O
SID_OUT
O
1.5 to 13.5V
145
24
GND
PGND
Demultiplexed output of
AC inverse driven video
signals.
Can be directly
connected to the LCD
panel.
Precharge waveform
output.
Adjustment is possible
by the 3-wire serial
interface setting.
This pin cannot directly
drive the LCD panel, so
input to the LCD panel
through a buffer.
VDD
29
FRINV
I
High: ≥ 2.0V
Low: ≤ 0.8V
20k
29
GND
–4–
Input for switching the
output polarity to
inverted or non-inverted
relative to the LCD
panel AC drive inversion
timing (FRP) pulse.
CXA7005R
Pin
No.
Symbol
I/O
Standard
voltage level
Equivalent circuit
Master/slave setting
when using two
CXA7005Rs.
When set high, this chip
operates as the master
IC; when set low, this
chip operates as the
slave IC.
When using only one
CXA7005R, leave this
pin open.
VDD
30
STATUS
I
High: ≥ 2.0V
Low: ≤ 0.8V
Description
20k
30
GND
VDD
31
DIRC
I
High: ≥ 2.0V
Low: ≤ 0.8V
Scan direction setting.
The scan direction is set
in combination with the
3-wire serial interface
setting DIRCR.
20k
31
GND
VDD
32
PRG
I
High: ≥ 2.0V
Low: ≤ 0.8V
1k
32
Timing pulse input for
switching the Pin 24
(SID_OUT) output level.
This pin is also used as
the circuit reset pulse.
GND
VDD
33
FRP
I
High: ≥ 2.0V
Low: ≤ 0.8V
1k
33
LCD panel AC drive
inversion timing input.
High: inverted
Low: non-inverted
GND
VDD
34
CLK
I
High: ≥ 2.0V
Low: ≤ 0.8V
1k
34
GND
–5–
Dot clock input.
The polarity is
determined by the 3-wire
serial interface setting
CKPOL.
High: reverse polarity
Low: positive polarity
CXA7005R
Pin
No.
Symbol
I/O
Standard
voltage level
Equivalent circuit
Description
VDD
37
to
46
D_IN9
to
D_IN0
I
High: ≥ 2.0V
Low: ≤ 0.8V
1k
37 to 46
Digital data input.
D_IN0: LSB
D_IN11: MSB
GND
35
VDD
3.3V
3.3V power supply.
11, 25 VCC
15.5V
15V power supply.
14, 23 PVCC
15.5V
Power VCC.
1, 2,
36, DGND
47, 48
DGND
GND.
8, 9,
26, 27, AGND
28
AGND
GND.
18, 19 PGND
PGND
Power GND.
–6–
CXA7005R
Electrical Characteristics Measurement Circuit
36
VCC
AGND
AGND
AGND
FRINV
STATUS
DIRC
PRG
FRP
CLK
19
43
18
44
17
45
16
46
15
47
14
48
13
1
2
3
4
5
6
7
8
9
10
11
SID_OUT
PVCC
47pF
SIG_OUT1
SIG_OUT2
250pF
SIG_OUT3
250pF
PGND
250pF
PGND
SIG_OUT4
SIG_OUT5
250pF
SIG_OUT6
250pF
PVCC
250pF
VCOM_OUT
12
REF_OUT
DGND
A
25
42
VCC
DGND
26
20
REF_IN
D_IN0
27
41
AGND
D_IN1
28
21
AGND
D_IN2
29
40
ADDR1
D_IN3
30
22
ADDR0
D_IN4
31
39
SDAT
D_IN5
32
23
SCLK
D_IN6
33
38
SENB
D_IN7
34
24
DGND
D_IN8
35
A
37
DGND
D_IN9
VDD
DGND
A
VDD
PVCC
15.25V
VDD
–7–
VCC
15.25V
VDD
3.3V
CXA7005R
Electrical Characteristics
No.
Item
Symbol
(Ta = 25°C)
Measurement description
Min.
Typ.
Max.
Unit
—
10
—
bit
0
—
—
ns
1
Digital input
resolution
n
2
Digital input
setup time 1
Ts1
CKPOL: 3.3V, PRG and D_IN[9:0] setup
time relative to CLK input.
3
Digital input
setup time 2
Ts2
CKPOL: 0V, PRG and D_IN[9:0] setup time
relative to CLK input.
0.5
—
—
ns
4
Digital input
hold time 1
Th1
CKPOL: 3.3V, PRG and D_IN[9:0] hold
time relative to CLK input.
2.5
—
—
ns
5
Digital input
hold time 2
Th2
CKPOL: 0V, PRG and D_IN[9:0] hold time
relative to CLK input.
2
—
—
ns
6
CLK input
frequency
range 1
fCLK1
SLDAT: 3.3V, maximum frequency at which
the internal timing generator and D/A
converter operate normally.
—
—
100
MHz
7
CLK input
frequency
range 2
fCLK2
SLDAT: 0V, maximum frequency at which
the internal timing generator and D/A
converter operate normally.
—
—
80
MHz
8
SIG_OUT output
voltage range
VSIGOUT
Output voltage range of SIG_OUT1 to
SIG_OUT6.
1.5
—
13.5
V
9
SIG_OUT output
amplitude
adjustable range
Gain control: 00h, measure the SIG_OUT
VSIGOUTpp voltage difference at D_IN[9:0] = 000h and
3FFh.
2
—
6
V
170
—
—
V/µs
0
—
1.175
V
6.375
—
8.625
V
10
SIG_OUT
slew rate
SROUT
Load capacitance C = 270pF; measure the
slew rate at 10 to 90% of SIG_OUT1 to
SIG_OUT6 rise and fall when D_IN[9:0] is
varied from 000h to 3FFh or from 3FFh to
000h.
11
SIG_OUT offset
adjustable range
VOFST
Offset adjustable range of SIG_OUT1 to
SIG_OUT6 by Bright control.
12
Signal center
adjustable range
VSIG
Signal center voltage adjustable range
when SIG center is varied.
13
SID amplitude
ASID1
adjustable range 1
SID_OUT amplitude adjustable range by
SID control A.
0
—
6
V
14
SID amplitude
ASID2
adjustable range 2
SID_OUT amplitude adjustable range by
SID control B.
0
—
6
V
15
VCOM
adjustable range
VCOM
VCOM_OUT adjustable range relative to
signal center voltage when VCOM control
is varied.
–2
—
0
V
16
VDD current
consumption
IDD
CLK = 80MHz, VDD current consumption.
23
—
28
mA
17
VCC current
consumption 2
ICC
CLK = 80MHz, inversion signal every
D_IN = 000h, FRP = 60CLK,
VCC + PVCC current consumption when
SIG_OUT load capacitance = 250pF.
38
—
68
mA
–8–
CXA7005R
No.
Item
Measurement description
Min.
Typ.
Max.
Unit
18
Output deviation
between
SIG_OUT
channels 1
DOUT1
D_IN[9:0] = 1FFh, value obtained by
subtracting minimum value from maximum
value of SIG_OUT1 to SIG_OUT6 output
at Gain control = BFh.
—
—
5
mV
19
Output deviation
between
SIG_OUT
channels 2
DOUT2
D_IN[9:0] = 000h or 3FFh, value obtained
by subtracting minimum value from
maximum value of SIG_OUT1 to SIG_OUT6
at Gain control = BFh.
—
—
10
mV
20
Output deviation
between
SIG_OUT ICs 1
DIC1
D_IN[9:0] = 1FFh, value obtained by
subtracting minimum value from maximum
value of SIG_OUT1 to SIG_OUT6 at
Gain control = BFh.
—
—
5
mV
21
Output deviation
between
SIG_OUT ICs 2
DIC2
D_IN[9:0] = 000h or 3FFh, value obtained
by subtracting minimum value from
maximum value of SIG_OUT1 to SIG_OUT6
at Gain control = BFh.
—
—
10
mV
22
MAINDAC
differential
linearity error
DLE
MAINDAC differential linearity error
–1
—
1
LSB
Symbol
–9–
CXA7005R
3-wire Serial Interface
The CXA7005R makes the various register settings using a 3-wire serial interface.
Up to 8 IC addresses can be designated by the ADDR0 and ADDR1 (Pins 6 and 7) settings, and these
settings can be adjusted individually. The relationship between the IC address and ADDR0 and ADDR1 is
shown below. In addition, the adjustable settings include the mode settings, gain, offset, signal center voltage,
precharge, and common voltage (VCOM) settings. (See the Register Function Setting Table.)
AC Characteristics
(Topr = –20 to +75°C, VDD = 3.3 ± 0.3V, VSS = 0V)
Item
Symbol
Min.
Typ.
Max.
Unit
SENB setup time relative to the rising edge of SCLK
tes
100
—
—
ns
SENB hold time relative to the rising edge of SCLK
teh
100
—
—
ns
SDAT setup time relative to the rising edge of SCLK
tds
100
—
—
ns
SDAT hold time relative to the rising edge of SCLK
tdh
100
—
—
ns
Timing Definition
ENABLE highYKFVJ
400nsQTOQTG
tes
teh
VDD
SENB
VSS
VDD
SCLK
VSS
tds
tdh
VDD
SDAT
VSS
– 10 –
CXA7005R
Input Format and Initialization
The 3-wire serial interface input format is shown below.
The minimum configuration is the 3 bytes of one write designation byte, one data byte, and one dummy data
byte. In addition, the register address is automatically incremented by the number of input data.
• Initialization
This IC must initialize the registers before setting the registers. Write "1" to register address (00h) RESET after
power is turned on. This setting initializes this IC.
After initialization, register setting is performed by returning RESET to "0". When initialization is not performed,
the setting value of a register may not be reflected correctly.
Input Format
SENB
SCLK
Write designation byte
SDAT
Data
Dummy data
Write Designation Byte
SENB
SCLK
0
SDAT
D2
D1
D0
REG
ADDR2
0
IC address
REG
ADDR1
REG
ADDR0
Register address
IC Address Definition
IC address
External pin
IC address for serial interface
D2
D1
D0
ADDR1
ADDR0
0
L
L
L
L
L
1
L
L
H
L
C
2
L
H
L
L
H
3
L
H
H
C
L
4
H
L
L
C
H
5
H
L
H
H
L
6
H
H
L
H
C
7
H
H
H
H
H
– 11 –
L: GND
C: 1/2VDD or OPEN
H: VDD
CXA7005R
Register Function Setting Table
REG ADDR
Function
D7
D6
D5
D4
D3
D2
00
Mode
RESET
SIDAT
SLINV
FHCNT
DIRCR
SIDON
PRPOL CKPOL
01
SIG center
SIGC5
SIGC4
SIGC3
SIGC2
SIGC1
SIGC0
02
Gain control
G7
G6
G5
G4
G3
G2
G1
G0
03
Bright control
B7
B6
B5
B4
B3
B2
B1
B0
04
VCOM control
VC6
VC5
VC4
VC3
VC2
VC1
VC0
05
SID control A
SIDA6
SIDA5
SIDA4
SIDA3
SIDA2
SIDA1
SIDA0
06
SID control B
SIDB6
SIDB5
SIDB5
SIDB3
SIDB2
SIDB1
SIDB0
Mode:
SIG center:
Gain control:
Bright control:
VCOM control:
SID control A:
SID control B:
Various function settings
Signal center voltage setting
Voltage amplitude setting between SIG_OUT white and black levels
Offset adjustment from SIG_OUT signal center voltage
VCOM voltage setting
Precharge signal voltage setting A
Precharge signal voltage setting B
– 12 –
D1
D0
CXA7005R
Description of Operation
The flow of internal operations is described below.
The digital signals input to D_IN0 to D_IN9 are internally demultiplexed into 6 phases, and then data processed
according to the various mode settings. After that, the signals are D/A converted into analog signals for each
channel, amplified at the rear end, and output.
The output level relative to the output level setting changes according to the following settings.
A: Register Gain control setting
B: Register Bright control setting
C: Signal center voltage
A
B
B
1023
A
512
C
0
Digital IN
SIG_OUT
• Signal center voltage adjustment (C)
The signal center voltage is determined by the register setting SIG center.
The signal center voltage can be adjusted in 35mV/LSB steps from 00h: 6.5V to 3Fh: 8.5V.
• Offset adjustment relative to the signal center voltage (B)
The output voltage at digital input 3FFh is determined by the SIG_C voltage and the register setting Bright
control.
The offset relative to the signal center voltage can be adjusted in 4mV/LSB steps from 00h: SIG_C ± 0.2V to
FFh: SIG_C ± 1V.
• White-black amplitude gain adjustment (A)
The white-black voltage amplitude when the digital input is varied from 000h to 3FFh is determined by the
register setting Gain control in the condition with the white level fixed.
The gain relative to the signal center voltage can be adjusted in 16mV/LSB steps from 00h: SIG_C ± 2V to
FFh: SIG_C ± 5.5V.
– 13 –
CXA7005R
Other settings are as follows.
Mode setting
The CXA7005R can be set to master/slave mode, single mode, and right/left inversion, etc. This makes it
possible to support various systems. (Various mode setting is designated with register and external pins.)
The various operating modes are described below.
• Operating mode setting <SLDAT>
The digital input of two ICs can be used together in master/slave mode by setting the Mode setting: SLDAT to
high level, or single mode can be set by setting SLDAT to low level. In master/slave mode, the 10-bit input is
shorted between the two ICs, and the ODD or EVEN data is selected by STATUS (Pin 30), DIRC (Pin 31) and the
Mode setting: DIRCR. Input a clock having the same period as the input data rate to CLK (Pin 34) in both modes.
Input data D_IN[9:0]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SLDAT: H
SLDAT: L
STATUS: L
STATUS: H
DIRC ex-or DIRCR: H
SIG_OUT1: 1
SIG_OUT2: 2
SIG_OUT3: 3
SIG_OUT4: 4
SIG_OUT5: 5
SIG_OUT6: 6
SIG_OUT1: 2
SIG_OUT2: 4
SIG_OUT3: 6
SIG_OUT4: 8
SIG_OUT5: 10
SIG_OUT6: 12
SIG_OUT1: 1
SIG_OUT2: 3
SIG_OUT3: 5
SIG_OUT4: 7
SIG_OUT5: 9
SIG_OUT6: 11
DIRC ex-or DIRCR: L
SIG_OUT1: 6
SIG_OUT2: 5
SIG_OUT3: 4
SIG_OUT4: 3
SIG_OUT5: 2
SIG_OUT6: 1
SIG_OUT1: 11
SIG_OUT2: 9
SIG_OUT3: 7
SIG_OUT4: 5
SIG_OUT5: 3
SIG_OUT6: 1
SIG_OUT1: 12
SIG_OUT2: 10
SIG_OUT3: 8
SIG_OUT4: 6
SIG_OUT5: 4
SIG_OUT6: 2
• Clock polarity setting <CKPOL>
The polarity of the internal circuit operation clock (MCLK) is determined by the Mode setting: CKPOL.
The internal circuits operate at reverse polarity from CLK when CKPOL is high, and at the same polarity as CLK
when CKPOL is low.
– 14 –
CXA7005R
• Horizontal sync timing <PRPOL>
The horizontal sync signal PRG is also used as the internal circuit reset function.
The Mode setting: PRPOL sets whether to apply the reset at the rising edge or the falling edge of PRG.
The reset is applied at the rising edge of the PRG pulse when PRPOL is high, and at the falling edge of the
PRG pulse when PRPOL is low.
PRG
MCLK
PRPOL: H
Reset pulse
PRPOL: L
• Output phase setting <FHCNT>
The SIG_OUT output timing phase can be set by the Mode setting: FHCNT.
When FHCNT is low, all SIG_OUT outputs are output at the same timing. When FHCNT is high, SIG_OUT1 to
SIG_OUT3 and SIG_OUT4 to SIG_OUT6 are output at phases offset by 1/2 clock period from each other.
FHCNT: L
FHCNT: H
SIG_OUT4 to 6
SIG_OUT1 to 3
SIG_OUT4 to 6
SIG_OUT1 to 3
GND
GND
• Polarity setting <FRINV>
Output polarity inversion/non-inversion relative to the signal center voltage is set by the FRP input and the
external pin FRINV (Pin 29). When set to the combinations shown in the table below, SIG_OUT is output noninverted (solid line) or inverted (dotted line) relative to FRP.
FRINV: H
FRINV: L
FRP: H
Non-inverted
Inverted
FRP: L
Inverted
Non-inverted
Inverted
SIG_OUT
SIG_C
Non-inverted
GND
FRP
– 15 –
CXA7005R
• Dot inversion and line inversion mode setting <SLINV>
When Mode setting: SLINV is set to low level, all SIG_OUT channels are output at the same polarity as shown
by the solid line in the figure below. When set to high level, the odd-numbered and even-numbered SIG_OUT
outputs are output at inverse polarities. At this time the odd-numbered outputs are inverted when the FRP
pulse is high, and non-inverted when the FRP pulse is low. Conversely, the even-numbered outputs are
inverted when the FRP pulse is low, and non-inverted when the FRP pulse is high.
Inverted
SIG_OUT
SIG_C
Non-inverted
GND
FRP
– 16 –
CXA7005R
Master/Slave mode
DIRC ex-or DIRCR: H
D_IN
CLK
PRG
PRG_X
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
STATUS: H
ENB_F
ENB
RCLK
CNT6
1
3
5
7
9
11
SOUT1
SOUT2
SOUT3
SOUT4
SOUT5
SOUT6
13
15
17
19
21
23
FHCNT: L
STB1_3
STB4_6
FHCNT: H
STB1_3
STB4_6
STATUS: L
ENB_F
ENB
RCLK
CNT6
2
4
6
8
10
12
SOUT1
SOUT2
SOUT3
SOUT4
SOUT5
SOUT6
FHCNT: L
STB1_3
STB4_6
FHCNT: H
STB1_3
STB4_6
– 17 –
14
16
18
20
22
24
CXA7005R
Master/Slave mode
DIRC ex-or DIRCR: L
D_IN
CLK
PRG
PRG_X
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
STATUS: H
ENB_F
ENB
RCLK
CNT6
12
10
8
6
4
2
SOUT1
SOUT2
SOUT3
SOUT4
SOUT5
SOUT6
24
22
20
18
16
14
FHCNT: L
STB1_3
STB4_6
FHCNT: H
STB1_3
STB4_6
STATUS: L
ENB_F
ENB
RCLK
CNT6
11
9
7
5
3
1
SOUT1
SOUT2
SOUT3
SOUT4
SOUT5
SOUT6
FHCNT: L
STB1_3
STB4_6
FHCNT: H
STB1_3
STB4_6
– 18 –
23
21
19
17
15
13
CXA7005R
Single mode
D_IN
CLK
PRG
PRG_X
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
DIR (DIRC ex-or DIRCR): H
ENB, ENB_F
CNT6
SOUT1
SOUT2
SOUT3
SOUT4
SOUT5
SOUT6
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
5
4
3
11
10
9
17
16
15
23
22
21
29
28
27
2
1
8
7
14
13
20
19
26
25
0
6
12
18
24
FHCNT: L
STB1_3
STB4_6
FHCNT: H
STB1_3
STB4_6
DIR (DIRC ex-or DIRCR) : L
ENB, ENB_F
CNT6
SOUT1
SOUT2
SOUT3
SOUT4
SOUT5
SOUT6
FHCNT: L
STB1_3
STB4_6
FHCNT: H
STB1_3
STB4_6
– 19 –
CXA7005R
SID Signal Generator Block
This circuit generates the precharge signal waveform used by the LCD panel.
The SID_OUT output level switching function is set on and off by the Mode setting (D2): SIDON.
When SIDON is low level, adjustment uses only the register setting: SID control A. When SIDON is high level,
adjustment is possible using both the register settings: SID control A and SID control B.
In addition, the SID_OUT output level relative to the signal center voltage can be set by the register settings:
SID control A and SID control B. Adjustment is possible in 50mV/LSB steps from 00h: SIG_C ± 5.5V to 7Fh:
SIG_C ± 0.1V for both settings.
SID_OUT cannot directly drive the precharge signal input of the LCD panel, so it should be connected through
a buffer having sufficient current supply capability.
SIDON: L
SIDON: H
Adjusted by
SIDA6 to SIDA0
Adjusted by
SIDB6 to SIDB0
Adjusted by only
SIDA6 to SIDA0
SIG_C
SID_OUT
VCOM Voltage Generator Block
This block sets the DC common potential for the LCD panel.
The SIG_OUT center potential set by the SIG_C voltage can be adjusted by the register setting VCOM control.
Adjustment is possible in 17.5mV/LSB steps from 00h: SIG_C – 2V to 7Fh: SIG_C – 0.1V.
– 20 –
CXA7005R
Example of Representative Characteristics (VCC = 15.25V, VDD = 3.3V, Ta = 25°C)
SIGC control characteristics
Gain control characteristics
6.0
9.0
5.5
5.0
SIG_OUT amplitude [V]
SIG_OUT [V]
8.5
8.0
7.5
7.0
4.0
3.5
3.0
2.5
2.0
D_IN: 3FFh
SIGC: 00h to 3Fh
Bright: 00h
6.5
4.5
GAIN: 00h to FFh
1.5
1.0
6.0
0
10
20
30
40
50
60
0
50
SIGC control code (DEC)
100
150
200
250
Gain control code (DEC)
Bright control characteristics
VCOM control characteristics
9.0
8.0
8.5
7.5
VCOM_OUT [V]
SIG_OUT [V]
Inversion
8.0
7.5
7.0
7.0
6.5
6.0
Non-inversion
D_IN: 3FFh
SIGC: 20h
Bright: 00h to FFh
6.5
5.5
VCOM: 00h to 7Fh
6.0
5.0
0
50
100
150
200
250
0
Bright control code (DEC)
40
60
80
100
120
VCOM control code (DEC)
SID control characteristics
D_IN SIG_OUT characteristics
13
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
12
11
Non-inverted SIG_OUT [V]
SID_OUT [V]
20
SIGC: 20h
SID A: 00h to 7Fh
SID B: 00h to 7Fh
Inversion
10
9
8
7
6
5
Non-inversion
4
D_IN: 000h to 3FFh
SIGC: 20h
GAIN: BFh
Bright: 00h
3
2
1
0
0
20
40
60
80
100
120
0
SID control code (DEC)
200
400
600
D_IN code (DEC)
– 21 –
800
1000
CXA7005R
MAINDAC DLE characteristics
1.0
0.8
0.6
0.4
DLE
0.2
0
200
400
600
800
1000
–0.2
–0.4
–0.6
–0.8
D_IN: 000h to 3FFh
–1.0
D_IN code (DEC)
– 22 –
CXA7005R
FB
Application Circuit 1 — Application Circuit to SVGA Panel
47µF/35V
0.1µF
20kΩ
DSD
CXD3531R
PRG
FRP
CLK
10Ω
10Ω
20kΩ
10Ω
0.1µF
FB
RGT
LCD panel
(SVGA)
0.1µF
10Ω
47µF/35V
FB
VCC
AGND
AGND
AGND
FRINV
STATUS
DIRC
PRG
FRP
CLK
VDD
DGND
0.1µF
36 35 34 33 32 31 30 29 28 27 26 25
D_IN4
10Ω
D_IN3
10Ω
D_IN2
10Ω
D_IN1
10Ω
D_IN0
DGND
DGND
21
41
20
42
19
CXA7005R
43
18
44
17
45
16
46
15
47
14
48
13
DGND
1
2
3
4
5
6
7
8
Buffer
SID_OUT
Psig
PVCC
SIG_OUT1
10Ω
SIG_OUT2
10Ω
SIG_OUT3
10Ω
PGND
Vsig1
Vsig2
Vsig3
PGND
SIG_OUT4
10Ω
SIG_OUT5
10Ω
SIG_OUT6
10Ω
Vsig4
Vsig5
Vsig6
PVCC
VCOM_OUT
10Ω
COM
9 10 11 12
REF_OUT
10Ω
40
VCC
D_IN0
D_IN5
22
REF_IN
D_IN1
10Ω
39
AGND
D_IN2
D_IN6
AGND
D_IN3
D_IN7
10Ω
23
ADDR1
D_IN4
10Ω
38
ADDR0
D_IN5
D_IN8
24
SDAT
D_IN6
10Ω
37
SCLK
D_IN7
D_IN9
SENB
D_IN8
10Ω
DGND
D_IN9
47µF/35V
0.1µF
0.1µF
FB
1kΩ
Microcontroller
20kΩ
0.1µF
0.1µF
47µF/35V
VCC
20kΩ
PVCC
VDD
0.1µF
15.5V
15.5V
3.3V
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 23 –
CXA7005R
FB
Application Circuit 2 — Application Circuit to XGA Panel
0.1µF
DSD
CXD3531R
47µF/35V
20kΩ
0.1µF
PRG
FRP
CLK
10Ω
10Ω
20kΩ
10Ω
0.1µF
FB
RGT
10Ω
47µF/35V
FB
VCC
AGND
AGND
AGND
FRINV
STATUS
DIRC
PRG
FRP
CLK
VDD
DGND
0.1µF
LCD panel
(XGA)
36 35 34 33 32 31 30 29 28 27 26 25
D_IN4
10Ω
D_IN3
10Ω
D_IN2
10Ω
D_IN1
10Ω
D_IN0
DGND
DGND
21
41
20
42
19
CXA7005R
43
18
44
17
45
16
46
15
47
14
48
13
2
DGND
DGND
1
3
4
5
6
7
8
Psig
PVCC
SIG_OUT1
10Ω
SIG_OUT2
10Ω
SIG_OUT3
10Ω
Vsig1
Vsig3
Vsig5
PGND
PGND
SIG_OUT4
10Ω
SIG_OUT5
10Ω
SIG_OUT6
10Ω
Vsig7
Vsig9
Vsig11
PVCC
VCOM_OUT
9 10 11 12
Microcontroller
Buffer
SID_OUT
10Ω
0.1µF
COM
47µF/35V
FB
D_IN0
10Ω
22
40
VCC
REF_OUT
D_IN1
D_IN5
39
REF_IN
D_IN2
10Ω
23
AGND
D_IN3
D_IN6
38
AGND
D_IN4
10Ω
24
ADDR1
D_IN5
10Ω
D_IN7
37
ADDR0
D_IN6
D_IN8
SDAT
D_IN7
D_IN9
SCLK
D_IN8
10Ω
10Ω
SENB
D_IN9
1kΩ
47µF/35V
20kΩ
0.1µF
0.1µF
0.1µF
20kΩ
FB
VCC
AGND
AGND
AGND
FRINV
STATUS
DIRC
PRG
FRP
CLK
VDD
DGND
0.1µF
36 35 34 33 32 31 30 29 28 27 26 25
D_IN9
D_IN8
D_IN7
D_IN6
D_IN5
D_IN4
D_IN3
D_IN2
D_IN1
D_IN0
DGND
DGND
37
24
38
23
39
22
40
21
41
20
42
19
CXA7005R
43
18
44
17
45
16
46
15
47
14
48
13
SID_OUT
PVCC
SIG_OUT1
10Ω
SIG_OUT2
10Ω
SIG_OUT3
10Ω
Vsig2
Vsig4
Vsig6
PGND
PGND
SIG_OUT4
10Ω
SIG_OUT5
10Ω
SIG_OUT6
10Ω
Vsig8
Vsig10
Vsig12
PVCC
VCOM_OUT
20kΩ
0.1µF
FB
VCC
REF_IN
9 10 11 12
REF_OUT
Microcontroller
20kΩ
8
AGND
7
AGND
6
ADDR1
5
SDAT
SCLK
4
ADDR0
0.1µF
3
SENB
DGND
20kΩ
2
DGND
1
0.1µF
47µF/35V
VCC
PVCC
VDD
0.1µF
0.1µF
20kΩ
47µF/35V
15.5V
15.5V
3.3V
0.1µF
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 24 –
CXA7005R
Package Outline
Unit: mm
48PIN LQFP (PLASTIC)
9.0 ± 0.2
∗
7.0 ± 0.1
36
S
25
13
48
B
(0.22)
0.5 ± 0.2
A
(8.0)
24
37
12
1
+ 0.05
0.127 – 0.02
0.5
+ 0.08
0.18 – 0.03
0.13 M
+ 0.2
1.5 – 0.1
0.1
S
0.5 ± 0.2
0.18 ± 0.03
0˚ to 10˚
0.127 ± 0.04
0.1 ± 0.1
DETAIL B: PALLADIUM
DETAIL A
NOTE: Dimension “∗” does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
PALLADIUM PLATING
SONY CODE
LQFP-48P-L01
LEAD TREATMENT
EIAJ CODE
P-LQFP48-7x7-0.5
LEAD MATERIAL
COPPER ALLOY
PACKAGE MASS
0.2g
JEDEC CODE
– 25 –
Sony Corporation