CXA2067AS Preamplifier for High-Resolution Computer Display Description The CXA2067AS is a bipolar IC developed for high-resolution computer displays. Features • Wide-band amplifier: 170 MHz@–3 dB (Typ) • Input dynamic range: 1.0 Vp-p (typ) • High gain preamplifier (17 dB) • R, G and B in a single package (SDIP 30 pins) • I2C bus control Contrast control Sub contrast control Brightness control OSD contrast control Cut-off control: 4 channels of DAC output 2 blanking level modes (0.5 V fixed, pedestal –0.3 V) • • • • • • 30 pin SDIP (Plastic) Absolute Maximum Ratings (Ta=25 °C, GND=0 V) • Supply voltage VCC/R/G/B 14 V VCC 7 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –65 to +150 °C • Allowable power dissipation PD Sync separator for sync-on-green Blanking mixing function OSC mixing function Video interval detection function VBLK sync DAC refresh system 12 V power supply interlocked power saving function 2.05 Recommended Operating Conditions Supply voltage VCC/R/G/B 12±0.5 VCC 5±0.5 W V V Applications High-resolution computer displays Structure Bipolar silicon monolithic IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E99857 CXA2067AS Block Diagram D/A CONVERTOR SDA 1 CUTOFF (R) CUTOFF (G) CUTOFF (B) CUTOFF (RGB) DECORDER SCL CONTRAST SUB CONTRAST (R) SUB CONTRAST (G) SUB CONTRAST (B) OSD GAIN (R) OSD GAIN (G) OSD GAIN (B) BRIGHTNESS (RGB) I 2 C BUS 2 30 CSYNC/VDET 29 VCC R 28 S/H-R 27 ROUT 26 GND-R 25 S/H-G 24 GOUT 23 GND-G 22 VCC G 21 S/H-B 20 BOUT 19 GND-B 18 BLKING 17 YS 12V To each MODE SW COF R 3 COF G 4 LPF Rch SUB CONTRAST CONTRAST GAIN CONTROL DATA COF B 5 BLANKING MODE GAIN CONTROL AMP COF RGB BLANKING BUFFER AMP 6 OSD YS GENERATOR RIN 7 BLANKING PULSE OSD PULSE (13PIN) OSD SW OSD GAIN (R) BRIGHTNESS YS PULSE (17PIN) 5V VCC 8 GIN 9 SYNC SEP/VDET 12V SYNC IN SYNC SEPARATOR 10 VDET COMPARATOR BIN SVSW 11 Gch CLP 12 OSD-R 13 Same as R channel to OSDSW OSD-G 14 to OSDSW OSD-B Bch Same as R channel to OSDSW 15 16 12V to OSDSW —2— VCC B CXA2067AS Pin Description Pin No. Symbol Pin voltage Equivalent circuit Description VCC I2C bus standard SDA (serial data) input/output. VILMAX=1.5 V VIHMIN=3.5 V VOLMAX=0.4 V 4k 1 SDA 1 — VCC I2C bus standard SCL (serial clock) input/output. VILMAX=1.5 V VIHMIN=3.5 V 4k 2 SCL 2 — 10k 3 VCC COF R VCC VCC 100 4 COF G — 5 DAC output for cut-off adjustment. Output DC is 1 to 4 V. 3 COF B 4 5 6 COF RGB 7 RIN 6 VCC VCC 9 GIN 1.8 V (Clamp) 1k 11 BIN 8 VCC 14k VCC 8k VCC VCC R, G and B signal inputs. Input via a capacitor. 7 300 9 11 VCC 1k 5V 5 V power supply. —3— CXA2067AS Pin No. Symbol Pin voltage Equivalent circuit Description VCC VCC 10 SYNC IN VCC 100 Sync-on-green signal input. Input via a capacitor. 2.8 V 10 150 VCC VCC 2p 12 CLP 10k — 10k 10k 12 Clamp pulse (positive polarity) input. VILMAX=0.8 V VIHMIN=2.8 V VCC 13 OSD-R VCC 2p 14 OSD-G 5k — 10k 13 OSD control inputs. VILMAX=0.8 V VIHMIN=2.8 V 14 15 OSD-B 16 VCC B 15 12 V 12 V power supply. (B channel) VCC VCC 2p 17 YS — 5k 10k 17 —4— YS (OSD BLK) control input. VILMAX=0.8 V VIHMIN=2.8 V CXA2067AS Pin No. Symbol Pin voltage Equivalent circuit Description VCC VCC 4k VCC 18 BLKING 30k — 10k 18 19 23 26 GND-B GND-G GND-R 20 BOUT 0V Blanking pulse input. Set the V blanking pulse width to 300 µs or more. VILMAX=0.8 V VIHMIN=2.8 V Ground. VCCR/G/B VCCR/G/B 2p VCCR/G/B 24 GOUT 310 — R, G and B outputs. 20 24 27 ROUT 21 S/H-B 27 5k VCC VCC 25 S/H-G — VCC 1k 21 300 25 28 Brightness sample-and-hold. Connect to GND via a capacitor. 1k 28 S/H-R 22 VCC G 12 V 12 V power supply. (G channel) 29 VCC R 12 V 12 V power supply. (R channel) —5— CXA2067AS Pin No. Symbol Pin voltage Equivalent circuit VCC VCC VCC 30 CSYNC /VDET — 100 20k 30 500 —6— Description VCC 5k Sync-on-green signal sync separator output/video detector output. Either of them is selected by SVSW of I2C bus. Typ. : High=4.3 V Low=0.2 V (positive polarity) CXA2067AS Definitions of I2C Bus Register Slave Address SLAVE RECEIVER : 40 (HEX) Register Table SUB ADDRESS BIT7 BIT6 00h 01h 0 BLK MODE 02h 03h 04h 05h VDET LEVEL 06h 07h 08h 09h 0Ah VDET OFF SVSW BIT5 ∗ BIT4 BIT3 BIT2 CONTRAST BRIGHTNESS CUT OFF R CUT OFF G CUT OFF B OSD GAIN CUT OFF RGB SUB CONTRAST R SUB CONTRAST G SUB CONTRAST B ∗ ∗ ∗ BIT1 BIT0 ∗ VSOFF Note) ∗: don’t care Sub Address CONTRAST (8): 0000 Performs the gain control for R, G and B channels in common. Control is performed by the multiplication with SUB CONTRAST. The white balance is adjusted by SUB CONTRAST and the luminance is adjusted by CONTRAST. 0 : Gain minimum (–30 dB or less) 255 : Gain maximum (+17 dB) Sub Address BLK MODE (1): 0001 Switches the blanking level. 0 : Pedestal–0.3 V 1 : 0.3 V fixed Sub Address BRIGHTNESS (6): Performs the black level control for R, G and B channels in common. 0001 0 : Black level minimum (0.9 V) 63 : Black level maximum (2.8 V) Sub Address CUT OFF R (8): 0010 Performs the Pin 3 (COF R) output voltage control. 0 : Output voltage minimum (1 V) 255 : Output voltage maximum (4 V) Sub Address CUT OFF G (8): 0011 Performs the Pin 4 (COF G) output voltage control. 0 : Output voltage minimum (1 V) 255 : Output voltage maximum (4 V) Sub Address CUT OFF B (8): 0100 Performs the Pin 5 (COF B) output voltage control. 0 : Output voltage minimum (1 V) 255 : Output voltage maximum (4 V) —7— CXA2067AS Sub Address VDET LEVEL (2): 0101 Controls the signal detection (VDET) slice level. 0 : Slice level minimum (RIN or GIN or BIN=30 mV) 1 : Slice level maximum (RIN or GIN or BIN=220 mV) Sub Address OSD GAIN (6): 0110 Performs the OSD gain control for R, G and B channels in common. Control is performed by the multiplication with SUB CONTRAST (upper 6 bits) so that the video white balance and tracking are obtained. 0 : Gain minimum (0 Vp-p) 63 : Gain maximum (5 Vp-p) Sub Address CUT OFF RGB (8): Performs the Pin 6 (COF RGB) output voltage. 0110 0 : Output voltage minimum (1 V) 255 : Output voltage maximum (4 V) Sub Address SUB CONTRAST R (8): Performs the R channel gain control. 0111 Control is performed by the multiplication with CONTRAST. Use for the white balance adjustment. 0 : Gain minimum (–30 dB or less) 255 : Gain maximum (+17 dB) Sub Address SUB CONTRAST G (8): Performs the G channel gain control. 1000 Control is performed by the multiplication with CONTRAST. Use for the white balance adjustment. 0 : Gain minimum (–30 dB or less) 255 : Gain maximum (+17 dB) Sub Address SUB CONTRAST B (8): Performs the B channel gain control. 1001 Control is performed by the multiplication with CONTRAST. Use for the white balance adjustment. 0 : Gain minimum (–30 dB or less) 255 : Gain maximum (+17 dB) Sub Address VDET OFF (1): 1010 Performs the Pin 30 output control. 0 : Output ON 1 : Output OFF Sub Address SV SW (1): 1010 Switches the Pin 30 output signal (sync separator/video detector). 0 : Sync separator output 1 : Video detector output Sub Address VS OFF (1): 1010 Performs the control of VBLK sync DAC refresh function. 0 : Function operation ON 1 : Function operation OFF —8— CXA2067AS I2C Bus Logic System No. Item Symbol Min. Typ. Max. Unit 1 High level input voltage VIH 3.0 — 5.0 V 2 Low level input voltage VIL 0 — 1.5 V 3 Low level output voltage with 3 mA SDA current inflow VOL 0 — 0.4 V 4 Maximum clock frequency fSCL 0 — 400 kHz 5 Minimum waiting time for data change tBUF 4.0 — — µs 6 Minimum waiting time for data transmission start tHD : STA 4.0 — — µs 7 Low level clock pulse width tLOW 4.7 — — µs 8 High level clock pulse width tHIGH 4.0 — — µs 9 Minimum waiting time for start preparation tSU : STA 4.7 — — µs 10 Minimum data hold time tHD : DAT 0 — — ns 11 Minimum data preparation time tSU : DAT 250 — — ns 12 Rise time tR — — 1 µs 13 Fall time tF — — 300 ns 14 Minimum waiting time for stop preparation tSU : STO 4.7 — — µs —9— CXA2067AS Electrical Characteristics No. Measurement item 1 2 3 4 Current consumption (5 V) Current consumption (12 V) Current consumption (12 V OFF) Frequency response (50 MHz) Symbol ICC1 ICC2 ICC3 F50 Measurement contents VCC (5 V) pin inflow current RGB signal input: None VCC R/G/B (12 V) pin inflow current RGB signal input: None VCC pin inflow current for 12 V OFF RGB signal input: None Min. Typ. Max. Unit 85 115 140 mA 29.5 45 55.5 mA 20 30 40 mA 0 1.9 dB –3.0 0 3.0 dB 5.6 6.2 — Vp-p — 0 100 mVp-p — 0 100 mVp-p Input the continuous 1 MHz, 50 MHz and 100 MHz sine waves (0.7 Vp-p). Measure the output amplitude gain difference at this time. –1.5 Vout (50 MHz) Gain difference [dB]=20 log Vout (1 MHz) Vout (100 MHz) Gain difference [dB]=20 log Vout (1 MHz) RGB input signal (RGB input pins) 5 Frequency response (100 MHz) F100 0.7Vp-p CLP potential (Approx. 1.7 V) GND 6 Contrast control 1 Measure the output signal amplitude Vout level when a 0.7 Vp-p video signal is input. GCONT1 GCONT1 : Contrast=SubContrast=FF GCONT2 : Contrast=00/SubContrast=FF 7 Contrast control 2 GCONT2 Input signal 0.7Vp-p Measure the output signal amplitude Vout level when a 0.7 Vp-p video signal is input. Contrast=FF/SubContrast=00 8 Sub contrast control GSUB Input signal 0.7Vp-p —10— CXA2067AS No. Measurement item 9 Symbol Measurement contents Min. Typ. Max. Unit GOSD1 Measure the OSD level of the output signal when the OSD pulse is input. GOSD1 : OSD=3F/SubContrast=FF GOSD2 : OSD=00/SubContrast=FF 4.5 5 — Vp-p — 0 0.4 0.7 OSD gain control OSD interval RGB output signal GOSD2 VBRT1 10 OSD level Measure the black level of the RGB output signal. VBRT1 : Brightness=00 VBRT2 : Brightness=3F 150 mVp-p 1 Brightness control V RGB output signal VBRT2 2.2 2.6 3 — 0.3 0.6 Black level GND BLK control (BLK MODE=0) VBLK1 Measure the BLK level of the output signal when the BLK pulse is input. 11 V BLK control (BLK MODE=1) BLK level (VBLK1) VBLK2 — 0.3 0.6 — 30 40 BLK level (VBLK2) GND Sync separator output rise delay SDLYR Vth=50% 12 Rise Delay Sync separator output fall delay SDLYF VDET output rise delay DDLYR 13 VDET output fall delay DDLYF Vth=50% Vth=50% Rise Delay Vth=50% —11— ns Fall Delay 0.7Vp-p Fall Delay — 60 80 — 20 40 ns — 30 60 CXA2067AS No. Measurement item 14 15 DAC output voltage (COFF=00) DAC output voltage (COFF=FF) VDET output amplitude Symbol Measurement contents VCUT1 Min. Typ. Max. — 1 1.3 Measure the DAC output voltage (Pin 6) for COFF=00/FF. VCUT2 Unit V 3.9 4 — 3.85 4 — Input the crosshatch signal of DotClock=100 MHz/0.7 Vp-p and measure the VDET output amplitude. SW SW=1/VDET LEVEL=0 VDET Input signal 0.7Vp-p 10ns —12— 10ns Vp-p CXA2067AS Electrical Characteristics Measurement Circuit SYNC SEP/VDET Output 1 SDA CSYNC/VDET 30 220 I 2 C BUS 47µF 12V 2 VCC R SCL 29 220 0.1µF 3 S/H-R COF R 28 0.1µF 4 ROUT COF G 27 Rch Output DAC Output 5 COF B 6 COF RGB GND-R 26 S/H-G 25 0.1µF 0.1µF 7 GOUT RIN 24 Gch Output 47µF 75 8 5V VCC GND-G 23 47µF 0.1µF 12V 9 GIN VCC G 22 0.1µF 0.1µF 75 10 SYNC IN S/H-B 21 0.1µF 0.1µF 75 11 BIN BOUT 20 0.1µF Bch Output 75 12 CLP GND-B 19 13 OSD-R BLKING 18 14 OSD-G YS 17 47µF 12V 15 OSD-B VCC B 16 0.1µF —13— CXA2067AS Electrical Characteristics Measurement Circuit (Frequency response) SYNC SEP/VDET Output 1 SDA CSYNC/VDET 30 220 I 2 C BUS 47µF 12V 2 VCC R SCL 29 220 0.1µF 3 S/H-R COF R 28 0.1µF 4 ROUT COF G 27 Rch Output DAC Output 5 COF B 6 COF RGB GND-R 26 S/H-G 25 0.1µF 0.1µF 7 GOUT RIN 24 Gch Output 47µF 75 8 5V VCC GND-G 23 47µF 0.1µF 12V 9 GIN VCC G 22 0.1µF 0.1µF 75 10 SYNC IN S/H-B 21 0.1µF 0.1µF 11 BIN BOUT 20 0.1µF Bch Output 12 CLP GND-B 19 13 OSD-R BLKING 18 14 OSD-G YS 17 47µF 12V 15 OSD-B VCC B 16 0.1µF —14— —15— enable The latest data which was sent before VBLK is written to DAC. In this case, Data 1 is written. disable Data 1 Transmission interval DAC rewrite is not performed when the bus data transmission is in progress for the VBLK interval. The sent data is hold. Data 2 Rewrite to Data 3. When Data 3 is not transmitted, rewrite to Data 2. Data 3 The VBLK signal is extracted form the composite BLK signal input to Pin 18. The DAC data rewrite for each control is simultaneously performed, synchronizing to the VBLK signal. The received I2C bus data is held by the latch till the next VBLK signal comes. Therefore, the timing of I2C bus data transmission from the microcomputer is free. The V blanking pulse width input to Pin 18 should be 300µs or more. DAC refresh signal DAC refresh Enable signal Bus data transmission VBLK VBLK Sync DAC Refresh System CXA2067AS CXA2067AS Application Circuit SYNC SEP/VDET Output 1 I 2 C BUS SDA CSYNC/VDET 30 220 47µF 12V 2 VCC R SCL 29 220 0.1µF 3 S/H-R COF R 28 0.1µF 4 ROUT COF G 27 Rch Output DAC Output 5 COF B 6 COF RGB GND-R 26 S/H-G 25 0.1µF 0.1µF 7 GOUT RIN 24 Gch Output 47µF 8 5V VCC GND-G 23 47µF 0.1µF 12V 9 GIN VCC G 22 0.1µF 0.1µF 0.1µF 10 SYNC IN S/H-B 21 0.1µF 11 BIN BOUT 20 0.1µF Bch Output 12 CLP GND-B 19 13 OSD-R BLKING 18 14 OSD-G YS 17 YS input 47µF 12V 15 OSD-B VCC B 16 0.1µF Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. —16— CXA2067AS Notes on Operation 1. The ROUT, GOUT and BOUT outputs should be received in the high impedance state. 2. The wiring from ROUT, GOUT and BOUT to the power amplifier should be as short as possible. 3. For the decoupling capacitors for VCC and VCC R/G/B, the ceramic capacitor and the electrolysis capacitor should be connected in parallel as closely to the IC as possible. 4. The clamp capacitors for RIN, GIN, BIN, S/H R, S/H G and S/H B should be connected as close to the IC as possible. 5. The signals to RIN, GIN and BIN should be input via a clamp capacitor with the low impedance. 6. Set the output OFF when the VDET/CSYNC output is not used. (The cross talk may deteriorate) —17— CXA2067AS Unit : mm + 0.1 .05 0.25 – 0 30PIN SDIP (PLASTIC) + 0.4 26.9 – 0.1 30 + 0.3 8.5 – 0.1 10.16 16 0° to 15° 15 1 + 0.4 3.7 – 0.1 0.5 MIN 1.778 Two kinds of package surface: 1.All mat surface type. 2.All mirror surface type. 0.5 ± 0.1 3.0 MIN Package Outline 0.9 ± 0.15 PACKAGE STRUCTURE MOLDING COMPOUND EPOXY RESIN SONY CODE SDIP-30P-01 LEAD TREATMENT SOLDER/PALLADIUM PLATING EIAJ CODE SDIP030-P-0400 LEAD MATERIAL COPPER ALLOY PACKAGE MASS 1.8g JEDEC CODE —18—