CXA3506R 3-channel 8-bit 120MSPS A/D Converter Amplifier PLL Description The CXA3506R is a 3-channel 8-bit 120MSPS A/D converter with built-in amplifier and PLL developed for LCD projectors and LCD monitors. The CXA3506R inputs RGB graphics signals from personal computers or others. After the input levels are controlled, the A/D conversion is performed with a clock generated by PLL. The digital output levels are compatible with TTL. This IC operates at a maximum conversion rate of 120MHz, and can support up to XGA. Control register supports both I2C and 3-wire bus. Features • Supply voltage: 5V, 3.3V • Power consumption: 1.7W typ. (120MSPS) • 144-pin LQFP • 3-ch AMP and PLL eliminate design time for mutual connections. Structure Bipolar silicon monolithic IC Applications • LCD monitors • LCD projectors • Digital TVs • PDPs 144 pin LQFP (Plastic) Functions and Performance • Power save function • Supports both I2C and 3-wire bus Amplifier block • Clamp • Main contrast: 8-bit • Sub contrast: 8-bit × 3 • Main brightness: 8-bit × 3 • CbCr offset: 6-bit × 2 • Supports YCbCr input • Two input systems • AMP monitor output/SW monitor output • SYNCSEP function A/D converter block • Maximum conversion rate: 120MSPS • Supports XGA input • Supports demultiplexed output • Supports both in-phase and alternate phase during demultiplexing • Supports YUV4:2:2 output • Output high impedance mode • Built-in reference voltage PLL block • Sync input frequency: 10kHz to 100kHz • Clock delay: 1/32 to 64/32CLK • VCO counter: 12-bit • Low clock jitter • CLK inversion • CLK and 1/2CLK outputs • Phase comparison hold • Output high impedance mode Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E99Y22B1Z-PS CXA3506R Absolute Maximum Ratings (Ta = 25°C) Maximum ratings Unit DVCCREG, AVCCADREF, DVCCADTTL, DVCCAD, DVCCPLLTTL, AVCCVCO, DVCCPLL, AVCCIR, AVCCAMPR, AVCCAMPG, AVCCAMPB 5.5 V AVCCAD3, DVCCAD3 5.5 V GND – 0.5 to 5V VCC + 0.5 or 5.5 V GND – 0.5 to 5.5 V –65 to +150 °C 5 W Item Supply voltage Input voltage ADDRESS, XPOWERSAVE, XSENABLE, 3WIRE/I2C, HOLD, XTLOAD, EVEN/ODD, XCLKIN, CLKIN, SYNCIN1, SYNCIN2, CLPIN, RC1, RC2, R/CrIN1, R/CrIN2, R/CrCLP, G/YCLP, B/CbCLP, SOGIN1, G/YIN1, SOGIN2, G/YIN2, B/CbIN1, B/CbIN2, RCrOUT, G/YOUT, B/CbOUT, DACTESTOUT SDA, SCL Storage temperature Tstg Allowable power dissipation PD Recommended Operating Conditions Item Supply voltage Min. Typ. Max. Unit 4.75 5 5.25 V 3 3.3 3.6 V High level 2 — — V Low level — — 0.8 V High level DVCCPLL –0.8 — — V Low level — — DVCCPLL –1.6 V Straight mode 100 — — MSPS DMUX mode 120 — — MSPS YUV4:2:2 D2 mode 100 — — MSPS YUV4:2:2 special mode 100 — — MSPS Ta –10 — +75 °C DVCCREG, AVCCADREF, DVCCADTTL, DVCCAD, DVCCPLLTTL, DVCCPLL, AVCCVCO, AVCCIR, AVCCAMPR, AVCCAMPG, AVCCAMPB AVCCAD3, DVCCAD3 TTL input pin PECL input pin Maximum conversion rate Operating ambient temperature XPOWERSAVE, HOLD, XTLOAD, EVEN/ODD, SYNCIN1, SYNCIN2, CLPIN CLKIN, XCLKIN –2– CXA3506R GA5 GA6 GA7 DVCCADTTL DGNDADTTL GB0 DGNDAD3 AGNDAD3 GB1 GB2 GB3 GB4 GB5 DGNDAD3 GB6 GB7 DGNDADTTL DVCCADTTL DVCCAD DVCCAD3 AVCCAD3 VRB DVCCPLLTTL AGNDADREF DGNDPLLTTL XCLK CLK 1/2XCLK 1/2CLK DPGND DSYNC/DIVOUT UNLOCK SOGOUT HOLD XTLOAD EVEN/ODD Pin Configuration (Top View) 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 XCLKIN 109 72 GA4 CLKIN 110 71 GA3 SYNCIN1 111 70 GA2 SYNCIN2 112 69 GA1 CLPIN 113 68 GA0 DVCCPLL 114 67 DGNDADTTL DGNDPLL 115 66 DGNDAD3 AVCCVCO 116 65 DVCCADTTL AGNDVCO 117 64 BB7 RC1 118 63 BB6 RC2 119 62 BB5 AVCCIR 120 61 BB4 IREF 121 60 BB3 DPGND 122 59 GNDAD3 AGNDIR 123 58 BB2 G/YIN1 124 57 BB1 AVCCAMPG 125 56 BB0 G/YIN2 126 55 DGNDADTTL AGNDAMPG 127 54 DVCCADTTL G/YCLP 128 53 BA7 B/CbCLP 129 52 BA6 R/CrCLP 130 51 BA5 DPGND 131 50 DGNDAD3 SOGIN1 132 49 BA4 B/CbIN1 133 48 BA3 AVCCAMPB 134 47 BA2 SOGIN2 135 46 BA1 B/CbIN2 136 45 BA0 AGNDAMPB 137 44 DGNDADTTL DPGND 138 43 DGNDAD3 R/CrIN1 139 42 DVCCADTTL RB2 RB1 RB0 DGNDADTTL RA7 DVCCADTTL DGNDAD3 RA6 AGNDAD3 RA5 RA4 RA3 RA2 DGNDAD3 RA1 RA0 SDA –3– DGNDADTTL DVCCREG DVCCADTTL DGNDREG VRT 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 DVCCAD3 8 AVCCAD3 7 DPGND 6 AVCCADREF 5 SEROUT 4 3WIRE/I2C 3 XSENABLE 2 SCL 1 XPOWER SAVE 37 RB3 NC 38 RB4 DACTESTOUT 144 NC 39 RB5 G/YOUT 143 R/CrOUT 40 RB6 AGNDAMPR 142 B/CbOUT 41 RB7 R/CrIN2 141 ADDRESS AVCCAMPR 140 SOGIN2 SOGIN1 SYNCIN2 SYNCIN1 B/CbCLP B/CbIN2 B/CbIN1 G/YCLP G/YIN2 SYNCTIP CLP AMP B AMP G CLPIN SYNCSEP SYNCSEP SW SOGT SYNCSEP SW SOGO SW PLL REGISTER Cb Offset (6) Sub Contrast (8) Sub Brightness (8) Sub Contrast (8) Sub Brightness (8) VTH (4) VHYS (2) Main Contrast (8) SW SYNCIN SW SOGP SW B SW G SOGOUT G/YIN1 XPOWER SAVE R/CrCLP Cr Offset (6) SDA R/CrIN2 ADDRESS AMP R Sub Contrast (8) Sub Brightness (8) SCL SW R SEROUT PD R/CrOUT HOLD R/CrIN1 XSENABLE G/YOUT UNLOCK CP (3) SW B/CbOUT RC1 SW RC2 SW VRB VRT VRT Width (2) DIV 1, 2, 4, 8 COARSE DELAY (2) VCO ADC B ADC G ADC R VRB COUNTER (12) FINE DELAY (6) PLL XTLOAD –4– DATA MODE 1/2DIV EVEN/ODD TOP Block Diagram DSYNC/DIVOUT 1/2XCLK 1/2CLK XCLK CLK BA7 to BA0 BB7 to BB0 GA7 to GA0 GB7 to GB0 RA7 to RA0 RB7 to RB0 CXA3506R 3WIRE/I2C –5– B/CbIN2 B/CbIN1 G/YIN2 G/YIN1 R/CrIN2 R/CrIN1 SOGIN2 SOGIN1 Bch Gch Rch Amplifier Block Diagram 1bit Sub Contrast 8bit Sub Contrast 8bit Sub Contrast 8bit SW SOGP SYNC SEP DRV CLP R/CrCLP 1bit SW SW SW VRB VRT B/CbOUT VRB VRT G/YOUT VRB VRT R/CrOUT SYNC ON GREEN SEPARATOR Sub Brightness Cb Offset 8bit 6bit DRV CLP B/CbCLP Sub Brightness 8bit DRV CLP G/YCLP Sub Brightness Cr Offset 8bit 6bit VTH 4bit VHYS 2bit SYNC SEP Main Contrast 8bit GCA GCA GCA CLPOFF SYNC TIP CLP CLP CLP CLP CLP CLP CLP POL SYNC SEP SW B SW G SW R 1bit CLPIN SYNC TIP CLP RGB/YUV 1bit SYNC ON GREEN SYNCP SYNC ON GREEN SYNCT1 SYNC ON GREEN SYNCT2 ADC B ADC G ADC R DACTEST 1bit SYNC SEP POWER SAVE 1bit AMP POWER SAVE DACTEST OUT CXA3506R –6– Polarity SW IREF DAC TTLIN CLPIN (TTL) 1bit SYNC POL CLP POL 1bit Polarity HOLD POL 1bit Polarity 1bit SYNCP/HSYNC 1bit HSYNC1/2 SW Polarity 1bit 1bit SYNC OUT SW SOG OUT POL SW RGBIN1/2SEL TTLIN TTLIN TTLIN SW 1bit TTLOUT SOG Enable 1bit PECLIN HOLD (TTL) SYNCIN2 (TTL) SYNC ON GREEN SYNCP SYNCIN1 (TTL) SYNC ON GREEN SYNCT1 SYNC ON GREEN SYNCT2 SOGOUT (TTL) CLKIN (PECL) XCLKIN (PECL) PLL Block Diagram Clamp Pulse 1bit PD POL Phase Detector K J Q Q RC1 XTLOAD (TTL) TTLIN 1/2 1bit M/S RESET M/S PLL Power Save 2bit DIV 1, 2, 4, 8 DIV 1, 2, 4, 8 Reset Pulse Generator SW DSYNC By-pass 1bit 1bit VCO By-pass SW DIVOUT Pulse Width VCO + 1/4 Programmable Counter 6bit Fine Delay DIVOUT Delay 12bit VCO DIV 1/256 to 1/4096 3bit Charge Pump Coarse Delay Coarse Delay 2bit PLL DIVOUT Delay DIVOUT WIDTH 1bit 2bit RC2 M M TTLOUT DSYNC Enable 1bit 1bit DSYNC HOLD DSYNC HOLD UNLOCK Detect TTLOUT 1/2XCLK Enable 1bit TTLOUT 1/2CLK Enable 1bit TTLOUT XCLK Enable 1bit TTLOUT 1bit DSYNC POL 1bit CLK Enable Polarity UNLOCK Enable 1bit SW SW SW TTLIN EVEN/ODD (TTL) UNLOCK 1/2CLK (ADC) 1/2XCLK (TTL) 1/2CLK (TTL) CLK (ADC) XCLK (TTL) CLK (TTL) DSYNC/DIVOUT (TTL) CXA3506R –7– H2 B2 G2 R2 H1 B1 G1 R1 SYNCIN2 SOGIN2 B/CbIN2 G/YIN2 R/CrIN2 SYNCIN1 SOGIN1 B/CbIN1 G/YIN1 R/CrIN1 SYNC Block Diagram SYNC SEP SYNCP1 SYNC TIP CLAMP SYNC SEP PEDESTAL CLAMP SYNCP2 SYNC TIP CLAMP PEDESTAL CLAMP SYNCT2 SW SOGP SYNCT1 1bit RGB IN 1/2 Select 4bit 2bit VTH VHYS SYNC SEP AMP BLOCK SW PLL POL SW SOGO PLL POL TTL OUT 1bit SOG Enable SYNC OUT SW 1bit SOG OUT POL 1bit 1bit 1bit SYNC POL SYNCP/HSYNC SYNCT 1bit HSYNC1/2 SW SYNCIN SW SOGT PLL BLOCK SOGOUT CXA3506R AMP B AMP G AMP R ADC Power Save 1bit VRT VRB VRT VRT VRB VRT VRB VRT VRB VRB CLK CONT ADC B ADC G ADC R CLK –8– 1/2CLK ADC Block Diagram 8 8 8 DATA FORMAT DATA INV 1bit 3bit MODE 8 8 8 BB7 to BB0 BA7 to BA0 GB7 to GB0 GA7 to GA0 RB7 to RB0 RA7 to RA0 CXA3506R CXA3506R Pin Description Pin No. Symbol I/O Typical signal Description Amplifier output signal monitor 1 B/CbOUT O 1.83V 2 ADDRESS I — 3 R/CrOUT O 1.83V 4 NC — — Not used 5 NC — — Not used 6 XPOWER SAVE I TTL Power save setting 7 DGNDREG — GND Register GND 8 DVCCREG — 5V Register power supply 9 SDA I — Control register data input 10 SCL I — Control register CLK input 11 XSENABLE I TTL Enable signal input for 3-wire control register 12 SEROUT O TTL 3-wire control register data readout 13 3WIRE/I2C I — Selection of input between I2C bus and 3-wire bus 15 AVCCADREF — 5V Reference power supply for A/D converter AVCCAD3 — 3.3V Analog power supply for A/D converter VRT O 2.9V Top reference voltage output for A/D converter DVCCAD3 — 3.3V Digital power supply for A/D converter 19, 32, 42, 54, DVCCADTTL 65, 76, 90 — 5V 20, 33, 44, 55, DGNDADTTL 67, 77, 89 — GND TTL output GND for A/D converter O TTL Data output for R-channel port A side — GND Digital GND for A/D converter 16, 94 17 18, 92 21, 22, 24 to 28, 31 RA0 to RA7 23, 30, 43, 50, DGNDAD3 59, 66, 79, 86 I2C slave address setting Amplifier output signal monitor TTL output power supply for A/D converter 29, 80 AGNDAD3 — GND Analog GND for A/D converter 34 to 41 RB0 to RB7 O TTL Data output for R-channel port B side 45 to 49, 51 to 53 BA0 to BA7 O TTL Data output for B-channel port A side 56 to 58, 60 to 64 BB0 to BB7 O TTL Data output for B-channel port B side 68 to 75 GA0 to GA7 O TTL Data output for G-channel port A side 78, 81 to 85, 87, 88 GB0 to GB7 O TTL Data output for G-channel port B side 91 DVCCAD — 5V Digital power supply for A/D converter 93 VRB O 1.9V Bottom reference voltage output for A/D converter 95 AGNDADREF — GND Reference voltage GND for A/D converter –9– CXA3506R Pin No. Symbol I/O Typical signal Description 96 DVCCPLLTTL — 5V 97 DGNDPLLTTL — GND TTL output GND for PLL 98 XCLK O TTL Inverted CLK output 99 CLK O TTL CLK output 100 1/2XCLK O TTL Inverted 1/2CLK output 101 1/2CLK O TTL 1/2CLK output 103 DSYNC/ DIVOUT O TTL DSYNC or DIVOUT signal output 104 UNLOCK O 105 SOGOUT O TTL Output for SYNC ON GREEN 106 HOLD I TTL Input for phase comparison disable signal 107 XTLOAD I TTL Programmable counter reset setting 108 EVEN/ODD I TTL Inverted pulse input of ADC sampling CLK 109 XCLKIN I PECL Inverted CLK input for testing 110 CLKIN I PECL CLK input for testing 111 SYNCIN1 I TTL Sync input 1 112 SYNCIN2 I TTL Sync input 2 113 CLPIN I TTL Clamp pulse input 114 DVCCPLL — 5V Digital power supply for PLL 115 DGNDPLL — GND 116 AVCCVCO — 5V 117 AGNDVCO — GND Analog GND for PLL VCO 118 RC1 — 2.1V External pin for PLL loop filter 119 RC2 — 2 to 4.5V External pin for PLL loop filter 120 AVCCIR — 5V Analog power supply for IREF 121 IREF I 1.2V Current setup 123 AGNDIR — GND Analog GND for IREF 124 G/YIN1 I — G/Y signal input 1 125 AVCCAMPG — 5V Power supply for G/Y amplifier block 126 G/YIN2 I — G/Y signal input 2 127 AGNDAMPG — GND 128 G/YCLP — — Clamp capacitor for brightness 129 B/CbCLP — — Clamp capacitor for brightness 130 R/CrCLP — — Clamp capacitor for brightness 132 SOGIN1 I 2.8V 133 B/CbIN1 I — TTL output power supply for PLL Open collector Unlock signal output Digital GND for PLL Analog power supply for PLL VCO GND for G/Y amplifier block SYNC ON GREEN signal input 1 B/Cb signal input 1 – 10 – CXA3506R Pin No. Symbol I/O Typical signal — 5V Description 134 AVCCAMPB 135 SOGIN2 I 2.8V 136 B/CbIN2 I — 137 AGNDAMPB — GND 139 R/CrIN1 I — R/Cr signal input 1 140 AVCCAMPR — 5V Power supply for R/Cr amplifier block 141 R/CrIN2 I — R/Cr signal input 2 142 AGNDAMPR — GND GND for R/Cr amplifier block 143 G/YOUT O 1.83V Monitor pin for amplifier output signal 144 DAC TEST OUT O 5V — GND 14, 102, 122, DPGND 131, 138 Power supply for B/Cb amplifier block SYNC ON GREEN signal input 2 B/Cb signal input 2 GND for B/Cb amplifier block DAC testing output for amplifier block control register GND – 11 – CXA3506R Pin Description and Pin Equivalent Circuit Pin No. 3 Symbol R/CrOUT I/O O Typical signal Equivalent circuit 1.83V AVCCAMP 100 3 143 G/YOUT O 1.83V 143 1 AGNDAMP 280µ B/CbOUT O 1.83V 140 AVCCAMPR — 5V 125 AVCCAMPG — 5V 134 AVCCAMPB — 5V 142 AGNDAMPR — GND 127 AGNDAMPG — GND 137 AGNDAMPB — GND 1 GND for amplifier block. DVCCPLLTTL 100k SOGOUT O TTL 105 DGNDPLLTTL DGNDPLL 132 SOGIN1 I 2.8V AVCCAMPG 132 150 135 135 SOGIN2 I 2.8V Amplifier output signal monitor. Each monitor can output either the entered signal immediately before A/D converter or the signal after switching between 2 types of input signals. The 2 types of input signals can be selected by the control register and output. These pins are emitter follower outputs, but the internal bias current is so small that a 820Ω resistor should be connected between these pins and GND to monitor high frequency signals. When not used, connect to AVCCAMP. Power supply for amplifier block. DVCCPLL 105 Description AGNDAMPG – 12 – 100µ Sync separated SYNC signal output. Separates and outputs the SYNC signal from SYNC ON GREEN input signal. (SYNC signal input from SYNCIN1 and SYNCIN2 pins can be output.) Both positive and negative polarity outputs are supported. The polarity is selected by the control register. SYNC ON GREEN signal inputs. Input via a 0.1µF capacitor. When not used, connect to AVCC. The SYNC TIP clamp level is approximately 2.0V + Vf (0.8V) = approximately 2.8V. At this time, if the pin voltage is lowered, these pins go to low impedance and current flows from the IC. When these pins are at the SYNC TIP level or higher, the clamp circuit is off and only an input base current of approximately 1.2µA flows. CXA3506R Pin No. Symbol I/O Typical signal Equivalent circuit Description Amplifier block 139 R/CrIN1 I ∗1 141 R/CrIN2 I ∗1 I ∗1 Analog input signal. Input via a 0.1µF ceramic capacitor. The typical signal level is 0.7V. Signals from 0.5V (min.) to 1.0V (max.) can be supported. IN1 and IN2 are selected by the control register. Leave these pins open when not used. RGB input and YCbCr input can be selected by the control register. ∗1 The clamp level typical values are AVCCAMP 124 G/YIN1 250 139 126 25k 141 133 124 136 126 G/YIN2 I ∗1 100 25k 500 AGNDAMP 133 136 130 B/CbIN1 B/CbIN2 R/CrCLP I I — 100 400µ 100µ ∗1 Clamp period: A clamp current of ±1.2mA (max.) flows. Signal period: A base current of 0.5µA flows to the IC. ∗1 ∗2 AVCCAMP 250 128 G/YCLP — ∗2 100k 130 128 129 100 300 500 100µ AGNDAMP 129 B/CbCLP — as follows. In case RGB is input 2.2V + Vf (0.8V) = approximately 3V In case YCbCr is input G/YIN: 2.2V + Vf (0.8V) = approximately 3V R/CrIN, B/CbIN: 2.7V + Vf (0.8V) = approximately 3.5V ∗2 Clamp capacitor connector for brightness. Connect 0.1µF ceramic capacitors between these pins and GND. ∗2 Typical levels of the clamp are as follows. In case RGB is input SUB BRIGHTNESS 00H: 2.68V 80H: 2.81V FFH: 2.94V In case YCbCr is input G/YCLP is the same as above. R/Cr, B/CbCLP are as follows. CbCr Offset 00H: 3.04V 20H: 3.07V 3FH: 3.102V Clamp period: A clamp current of ±1.2mA (max.) flows. Signal period: A base current of 0.5µA flows to the IC. – 13 – CXA3506R Pin No. Symbol I/O Typical signal Equivalent circuit Description DVCCPLL 1.5k 113 CLPIN I TTL 192 113 1.5V Clamp pulse input for the signal of analog input clamp and brightness clamp. Both positive and negative polarity inputs are supported. The polarity is selected by the control register. The input pulse width should be 200ns or more. DGNDPLL A/D converter block 99 CLK O TTL DVCCPLLTTL 98 XCLK O TTL 100k 98 99 101 100 101 1/2CLK O TTL DGNDPLLTTL DGNDPLL 100 1/2XCLK O TTL 21, 22, 24 to 28, RA0 to RA7 31 O TTL 34 to 41 RB0 to RB7 O TTL 68 to 75 GA0 to GA7 O TTL 78, 81 to 85, GB0 to GB7 87, 88 O TTL CLK output. Output the same frequency CLK as that of ADC sampling. These are complemental TTL levels. These pins can be independently controlled on and off (power save) by the control register. 1/2CLK output. Output a half frequency CLK of that of ADC sampling. These are complemental TTL levels. These pins can be independently controlled on and off (power save) by the control register. Data output for R-channel port A side. DVCCADTTL Data output for R-channel port B side. Data output for G-channel port A side. 100k Data output for G-channel port B side. DGNDADTTL Data output for B-channel port A side. 45 to 49, BA0 to BA7 51 to 53 O TTL 56 to 58, BB0 to BB7 60 to 64 O TTL Data output for B-channel port B side. Reference power supply for A/D converter. DGNDAD3 15 AVCCADREF — 5V 95 AGNDADREF — GND Reference GND for A/D converter. 16, 94 AVCCAD3 — 3.3V Analog power supply for A/D converter. 29, 80 AGNDAD3 — GND Analog GND for A/D converter. 18, 92 DVCCAD3 — 3.3V Digital power supply for A/D converter. 91 DVCCAD — 5V Digital power supply for A/D converter. – 14 – CXA3506R Pin No. I/O Typical signal 23, 30, 43, 50, DGNDAD3 59, 66, 79, 86 — GND 19, 32, 42, 54, DVCCADTTL 65, 76, 90 — 5V 20, 33, 44, 55, DGNDADTTL 67, 77, 89 — GND Symbol Equivalent circuit Description Digital GND for A/D converter. TTL output power supply for A/D converter. TTL output GND for A/D converter. AVCCADREF 90 17 VRT O 2.9V 17 2k 20µ Top reference voltage output for A/D converter input dynamic range. Connect to AVCCAD3 via a 1µF ceramic capacitor. AGNDADREF AVCCADREF 20µ 93 VRB O 1.9V 93 4k 80 AGNDADREF – 15 – Bottom reference voltage output for A/D converter input dynamic range. Connect to AVCCAD3 via a 1µF ceramic capacitor. CXA3506R Pin No. Symbol I/O Typical signal Equivalent circuit Description PLL block 111 112 SYNCIN1 SYNCIN2 I I TTL Input SYNC signal at TTL level. The input polarity is switched by the control register. Leave this pin open when not used. TTL Input SYNC signal at TTL level. The input polarity is switched by the control register. Leave this pin open when not used. TTL Input signal for phase comparison HOLD. Phase comparison is stopped, and VCO oscillation frequency is held. When not be hold, fix the pin as follows. When HOLDPOL register is "1", fix this pin to low level. When HOLDPOL register is "0", leave this pin open or fix to high level. DVCCPLL 106 HOLD I 40k 106 107 192 108 111 1.5V 112 108 107 EVEN/ODD XTLOAD I I Input the signal used to invert the A/D converter sampling CLK. Low: EVEN mode High: ODD mode Normally fix it to low level. DGNDPLL TTL Programmable counter reset. Normally fix it to high level or leave open. In programmable counter test mode, set it to low level to call up the register contents. When not used, leave this pin open or fix to high level. TTL DVCCPLL 110 CLKIN I PECL 14k 500 110 109 500 109 XCLKIN I PECL DGNDPLL – 16 – 14k CLK input for ADC operation check. Input PECL level signal complementally. When using this pin, set CLK to external input by the control register. Leave this pin open when not used. CXA3506R Pin No. Symbol I/O Typical signal Equivalent circuit DVCCPLL 103 DSYNC/ DIVOUT DVCCPLLTTL 100k O Description This pin can output either DSYNC signal or DIVOUT signal. It can be selected by the control register. In addition, the output polarity can be selected by the control register. 103 TTL DGNDPLLTTL DGNDPLL DVCCPLLTTL 104 UNLOCK — 104 — 100k DGNDPLLTTL UNLOCK signal output. Make a discrimination between lock and unlock in the analog manner by connecting the external circuit. Leave this pin open when not used. Do not connect this pin to neither power supply nor GND. DGNDPLL AVCCIR 118 RC1 — External pin for PLL loop filter. 2.1V 118 119 119 RC2 — 2 to 4.5V External pin for PLL loop filter. AGNDIR DPGND AVCCIR 121 IREF I Connect an external resistor (3kΩ) to supply a stabilized current to the inside of the IC. (charge pump current, etc.) Connect this pin to GND via 0.1µF ceramic capacitor connected as close to the pin as possible. The band gap voltage is output. 1.2V 121 AGNDIR DPGND 114 DVCCPLL — 5V 115 DGNDPLL — GND 96 DVCCPLLTTL — 5V Digital power supply for PLL. Digital GND for PLL. TTL output power supply for PLL. – 17 – CXA3506R Pin No. Symbol I/O Typical signal 97 DGNDPLLTTL — GND 120 AVCCIR — 5V 123 AGNDIR — GND 116 AVCCVCO — 5V 117 AGNDVCO — GND Equivalent circuit Description TTL output GND for PLL. Analog power supply for IREF. Analog GND for IREF. Analog power supply for PLL VCO. Analog GND for PLL VCO. Control register block DVCCREG 200k Input control register data. Switching between the I2C and 3-wire bus mode is performed by the 3WIRE/I2C pin. 4k 9 9 SDA I — DGNDREG DVCCREG 200k Input control register CLK. Switching between the I2C and 3-wire bus mode is performed by the 3WIRE/I2C pin. 4k 10 10 SCL I — 10k DGNDREG Set slave address when using I2C bus mode. DVCCREG 15µ 1k 2 ADD I — 2 15µ 15µ Slave address: 1 0 0 1 1 S2 S1 0 VCC to 3/4VCC 3/4VCC to 2/4VCC 2/4VCC to 1/4VCC 1/4VCC to GND S2 0 1 1 0 S1 1 1 0 0 Connect this pin to GND during 3-wire bus mode. DGNDREG – 18 – CXA3506R Pin No. Symbol I/O Typical signal Equivalent circuit Description DVCCREG 200k Inputs enable signal for 3-wire bus. High level: Control disabled Low level: Control enabled Connect this pin to GND when using I2C. 4k 11 11 XSENABLE I TTL DGNDREG DVCCREG Selection of input between I2C bus and 3-wire bus. 100k 100k 13 3WIRE/I2C 13 I — VCC to 2/3VCC 2/3VCC to 1/3VCC 1/3VCC to GND 100k 15µ 15µ 3-wire bus mode I2C 3V mode I2C 5V mode DGNDREG DVCCREG 12 12 SEROUT O TTL 100k When using the read mode of 3-wire bus mode, the register information written once is output in series order from the LSB of the setting sub address data. DGNDREG 7 DGNDREG — GND 8 DVCCREG — 5V GND for register. Power supply for register. DVCCREG 10µ 6 XPOWER SAVE I TTL Power save for all functions including the control register block. High level: Normal operation Low level: Power save 1k 6 DGNDREG – 19 – CXA3506R Pin No. Symbol I/O Typical signal Equivalent circuit Description DVCCREG 144 DAC TEST OUT O 5V DAC test output for control register of amplifier block. Current is output by open collector. Normally connect to AVCC. 144 DGNDREG 14, 102, 122, 131, DPGND 138 — GND This pin is connected to the die pad. Connect to the specified GND in Application Circuit. 4 NC — — Not used. Leave this pin open or connect to GND. 5 NC — — Not used. Leave this pin open or connect to GND. – 20 – CXA3506R Electrical Characteristics (Ta = 25°C, AVCC, DVCC = 5V, AVCC3, DVCC3 = 3.3V) Supply Current Item Symbol Measurement conditions Min. Typ. Max. Unit Current during operating 5V current consumption ICC5 CLK = DC — 180 240 mA 3.3V current consumption ICC3 CLK = DC — 180 226 mA Register control power save current 5V power save current consumption ICC5PS — 26 42 mA 3.3V power save current consumption ICC3PS — 3.0 7.2 mA XPOWER SAVE pin control power save current 5V power save current consumption ICC5XPS — 9.0 22 mA 3.3V power save current consumption ICC3XPS — 3.0 7.2 mA Min. Typ. Max. Unit Register Item Symbol Measurement conditions 3-wire control bus (SDA, SCL, SENABLE) High level input voltage VIH 2.0 — 5.0 V Low level input voltage VIL 0 — 0.8 V High level input current IIH –2.0 — 0 µA Low level input current IIL –5.0 — 0 µA Threshold voltage High → Low VTHHL1 — 1.3 — V Threshold voltage Low → High VTHLH1 — 1.65 — V Input capacitance CI — — 10 pF SCL clock frequency FSCL1 in WRITE/READ mode — — 10 MHz XSENABLE setup time TENS in WRITE/READ mode 3 10 — ns XSENABLE hold time TENH in WRITE/READ mode 0 10 — ns XSENABLE high level pulse width TENPW in WRITE/READ mode 300 — — ns SDA setup time TDS in WRITE/READ mode 3 10 — ns SDA hold time TDH in WRITE/READ mode 0 10 — ns SDA delay time TD in READ mode — 11 — ns – 21 – CXA3506R Register (Cont.) Item Symbol Min. Typ. Max. Unit 2.3 — 5.0 V 0 — 1.0 V High level input current IIH –2.0 — 0 µA Low level input current IIL –5.0 — 0 µA Threshold voltage High → Low VTHHL2 — 1.6 — V Threshold voltage Low → High VTHLH2 — 1.95 — V 2.0 — 5.0 V 0 — 0.8 V High level input current IIH –1.0 — 0 µA Low level input current IIL –5.0 — 0 µA Threshold voltage High → Low VTHHL3 — 1.3 — V Threshold voltage Low → High VTHLH3 — 1.65 — V 0 0.15 0.5 V Measurement conditions I2C control bus (SDA, SCL) I2C (High) mode High level input voltage VIH Low level input voltage VIL I2C (Low) mode High level input voltage VIH Low level input voltage VIL SDA low level output voltage VOL IOH = 3mA Input capacitance CI — — 10 pF SCL clock frequency FSCL2 0 50 100 kHz Bus free-time STOP → START TBUF 4.7 5.0 — µs Hold time (resend) THD;STA 4.0 5.0 — µs Hold time in SCL clock at Low state TLOW 4.7 5.0 — µs Hold time in SCL clock at High state THIGH 4.0 5.0 — µs Setup time under resend START condition TSU;STA 4.7 5.0 — µs Data hold time THD;DAT 0 5.0 — µs Data setup time TSU;DAT 250 5000 — ns Rise time TR — — 1000 ns Fall time TF — — 300 ns Setup time under STOP condition TSU;STO 4.0 5.0 — µs Capacitive load of each bus line Cb — — 400 pF START condition: After this period, first clock is generated. – 22 – CXA3506R AMP Item Symbol Measurement conditions Min. Typ. Max. Unit 53 61 69 LSB Brightness characteristics Brightness level H (ADC OUT) VBRHAD Sub Brightness G, B, R = 255 ADC output conversion level Brightness level L VBRL Sub Brightness G, B, R = 0 G, B, R OUT pin voltage 1.388 1.588 1.788 V Brightness level M VBRM Sub Brightness G, B, R = 128 G, B, R OUT pin voltage 1.63 1.83 2.03 V Brightness level H VBRH Sub Brightness G, B, R = 255 G, B, R OUT pin voltage 1.86 2.06 2.26 V Brightness level Low side variable range VBRL – VBRM — –242 — mV Brightness level High side variable range VBRH – VBRM — 230 — mV Clamp characteristics Cb, Cr clamp level M (ADC OUT) VCLMAD Cb, Cr offset = 32 ADC output conversion level 120 128 136 LSB Cb, Cr clamp level L VCLL Cb, Cr offset = 0 B, R OUT pin voltage 1.94 2.23 2.46 V Cb, Cr clamp level M VCLM Cb, Cr offset = 32 B, R OUT pin voltage 1.99 2.28 2.51 V Cb, Cr clamp level H VCLH Cb, Cr offset = 63 B, R OUT pin voltage 2.03 2.34 2.58 V Cb, Cr clamp level Low side variable range VCLL – VCLM — –60 — mV Cb, Cr clamp level High side variable range VCLH – VCLM — 60 — mV 200 — — ns VMCL Main Contrast = 0 Sub Contrast = 128 Vin = 1.2Vp-p RGB/YUV mode, G, B, R OUT 0.62 0.78 0.94 times VMCM Main Contrast = 128 Sub Contrast = 128 Vin = 0.6Vp-p RGB/YUV mode, G, B, R OUT 1.23 1.53 1.84 times VMCH Main Contrast = 255 Sub Contrast = 128 Vin = 0.45Vp-p RGB/YUV mode, G, B, R OUT 1.79 2.24 2.69 times VSCL Main Contrast = 128 Sub Contrast = 0 Vin = 0.85Vp-p RGB/YUV mode, G, B, R OUT 0.96 1.2 1.44 times Clamp pulse minimum width TWCLP Contrast characteristics Main contrast control L Main contrast control M Main contrast control H Sub contrast control L – 23 – CXA3506R AMP (Cont.) Item Measurement conditions Min. Typ. Max. Unit VSCH Main Contrast = 128 Sub Contrast = 255 Vin = 0.55Vp-p RGB/YUV mode, G, B, R OUT 1.48 1.85 2.22 times Gain difference among RGB ∆Gain Main Contrast = 128 Sub Contrast = 128 Vin = 0.6Vp-p RGB/YUV mode, G, B, R OUT –8 0 8 % Frequency response Main Contrast = 128 Sub Contrast = 128 FC – 3dB Vin = 0.6Vp-p RGB/YUV mode, G, B, R OUT — 220 — MHz Sub contrast control H Symbol Cross talk characteristics Cross talk between channels CTC Main Contrast = 128 Sub Contrast = 128 fin = 100MHz, Vin = 0.6Vp-p — –35 — dB Cross talk among RGB CTB Main Contrast = 128 Sub Contrast = 128 fin = 100MHz, Vin = 0.6Vp-p — –30 — dB Min. Typ. Max. Unit SYNCSEP Item Symbol Measurement conditions SYNC SEP input characteristics SYNC TIP input minimum amplitude VSYN 0.2 — — Vp-p SYNC TIP input minimum duty DSYN 5 — — % SYNC SEP threshold voltage VTH SYNC SEP VTH = 1000 SYNC SEP VHYS = 10 116 145 174 mV SYNC SEP hysteresis voltage VHYS SYNC SEP VTH = 1000 SYNC SEP VHYS = 10 36 45 54 mV – 24 – CXA3506R PLL Item Symbol Measurement conditions Min. Typ. Max. Unit — — 1.0 nA 10 — 100 kHz Hold characteristics RC1 pin leak current Ileak SYNC signal input characteristics SYNC signal input frequency range FSYNC VCO characteristics Clock frequency FCLK1 VCO frequency divider DIV = 1/1 80 — 120 MHz Clock frequency FCLK2 VCO frequency divider DIV = 1/2 40 — 80 MHz Clock frequency FCLK3 VCO frequency divider DIV = 1/4 14 — 40 MHz Clock frequency FCLK4 VCO frequency divider DIV = 1/8 5 — 14 MHz VCO lock range Vlock 2.0 — 4.5 V VCO gain 1 KVCO1 VCO frequency divider DIV = 1/1 300 — 500 Mrad/sv VCO gain 2 KVCO2 VCO frequency divider DIV = 1/2 150 — 250 Mrad/sv VCO gain 3 KVCO3 VCO frequency divider DIV = 1/4 75 — 125 Mrad/sv VCO gain 4 KVCO4 VCO frequency divider DIV = 1/8 37.5 — 62.5 Mrad/sv Tj1p-p Triggered at SYNC Fsync = 15.73kHz Fclk = 12.27MHz N = 780 2.4 2.7 3 ns Tj2p-p Triggered at SYNC Fsync = 31.47kHz Fclk = 25.18MHz N = 800 1.6 1.8 2.0 ns Tj3p-p Triggered at SYNC Fsync = 48.08kHz Fclk = 50.00MHz N = 1040 1.3 1.4 1.5 ns SYNC input signal – Clock output jitter (XGA) Tj4p-p Triggered at SYNC Fsync = 56.48kHz Fclk = 75.00MHz N = 1328 0.9 1.0 1.1 ns Delay sync – Clock output jitter Tj7p-p Triggered at DSYNC — — 0.1 ns Jitter characteristics SYNC input signal – Clock output jitter (NTSC) SYNC input signal – Clock output jitter (VGA) SYNC input signal – Clock output jitter (SVGA) – 25 – CXA3506R ADC Item Symbol Measurement conditions Resolution Min. Typ. Max. Unit — 8 — bit DC characteristics Integral linearity error ILE — 1.0 — LSB Differential linearity error DLE — 0.4 0.7 LSB Reference voltage Top reference voltage VRT AVccAD3 as a reference –0.3 –0.4 –0.6 V Bottom reference voltage VRB AVccAD3 as a reference –1.3 –1.4 –1.6 V Input dynamic range VTB VRT – VRB 0.9 1.0 1.1 V AC characteristics Maximum conversion frequency of Straight Data out Mode Fc 100 — — MSPS Maximum conversion frequency of DMUX Parallel Data out Mode Fc 120 — — MSPS Maximum conversion frequency of DMUX Interleaved Data out Mode Fc 120 — — MSPS Maximum conversion frequency of 4:2:2 Data out D2 Mode Fc 100 — — MSPS Maximum conversion frequency of 4:2:2 Data out Special Mode Fc 100 — — MSPS – 26 – CXA3506R I/O Item Symbol Measurement conditions Min. Typ. Max. Unit Digital input (PECL) Digital input voltage: H VIH1 DVccPLL as a reference –1.15 — — V Digital input voltage: L VIL1 DVccPLL as a reference — — –1.5 V Digital input current: H IIH1 VIH1 = DVCCPLL – 0.8V –100 — 100 µA Digital input current: L IIL1 VIL1 = DVCCPLL – 1.6V –200 — 0 µA Digital input (TTL) Digital input voltage: H VIH2 2.0 — — V Digital input voltage: L VIL2 — — 0.8 V Threshold voltage VTH — 1.5 — V Digital input current: H IIH2 VIH = 3.5V –10 — –5 µA Digital input current: L IIL2 VIL = 0.2V –20 — 0 µA VOH1 IOH = –2mA 2.4 2.95 3.3 V VOH2 IOH = –2mA 2.3 2.7 3.0 V VOH3 IOH = –2mA 2.05 2.45 2.75 V VOH4 IOH = –2mA 1.85 2.2 2.5 V VOL IOL = 1mA — 0.2 0.5 V Digital output (TTL) Digital output voltage: H Digital output voltage: L – 27 – CXA3506R Timing Characteristics Item Symbol Measurement conditions Min. Typ. Max. Unit Clock output rise time TR_CLK 0.8 to 2.0V (CLK, 1/2CLK) 0.8 1.4 2.3 ns Clock output fall time TF_CLK 2.0 to 0.8V (CLK, 1/2CLK) 1.0 1.5 2.8 ns Delay sync output rise time TR_DSYNC 0.8 to 2.0V (DSYNC, DIVOUT, SOGOUT) 0.8 1.4 2.3 ns Delay sync output fall time TF_DSYNC 2.0 to 0.8V (DSYNC, DIVOUT, SOGOUT) 1.0 1.5 2.8 ns Data output rise time TR_DATA 0.8 to 2.0V 0.9 1.2 2.0 ns Data output fall time TF_DATA 2.0 to 0.8V 0.9 1.2 2.0 ns HOLD signal setup time Ths 20 — — ns HOLD signal hold time Thh 20 — — ns Delay sync delay time coarse delay Td_1 3 — 6 CLK Delay sync delay time fine delay Td_2 1/32 — 64/32 CLK Clock output delay from SYNC input signal Td_3 CL = 9pF 6.0 7.0 8.0 ns Delay time between clock output and DSYNC/DIVOUT signal Td_4 CL = 9pF 0.8 1.0 1.3 ns DIVOUT signal output delay time Td_5 Difference between delay sync signal and DIVOUT signal 4 — 5 CLK Clock – 1/2 clock Td_6 0.9 1.2 1.6 ns 1/2 clock – Data Td_7 2.3 2.6 3.2 ns Clock – Data Td_8 2.2 2.8 3.8 ns – 28 – ANALOG SIGNAL ANALOG SIGNAL 0.1µ 0.1µ 0.1µ 0.1µ 0.1µ 0.1µ 75 75 75 75 820 DACTESTOUT G/YOUT AGNDAMPR R/CrIN2 AVCCAMPR R/CrIN1 DPGND AGNDAMPB B/CbIN2 SOGIN2 AVCCAMPB B/CbIN1 SOGIN1 DPGND R/CrCLP B/CbCLP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 63 62 118 119 57 124 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 BUS CONTROLER 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 58 123 125 59 122 60 64 117 121 65 116 61 66 115 120 67 B/CbOUT G/YCLP 71 72 114 ADDRESS AGNDAMPG EVEN/ODD 68 R/CrOUT 75 XTLOAD 113 820 NC 820 G/YIN2 HOLD 69 NC 0.1µ DSYNC/DIVOUT XPOWER SAVE AVCCAMPG DPGND DGNDREG 75 1/2XCLK SDA G/YIN1 CLK SCL 0.1µ 1/2CLK DVCCREG 4.7k XSENABLE 4.7k AGNDIR XCLK 112 SEROUT DPGND DGNDPLLTTL 70 3WIRE/I2C 100p AGNDADREF DPGND ANALOG SIGNAL DVCCPLLTTL 111 AVCCADREF IREF VRB AVCCAD3 3k DVCCAD3 VRT 1µ AVCCIR DVCCAD DVCCAD3 RC2 DVCCADTTL DVCCADTTL 0.33µ DGNDADTTL DGNDADTTL 330p GB7 RA0 RC1 GB6 RA1 3.3k DGNDAD3 DGNDAD3 AGNDVCO GB5 RA2 AVCCVCO GB4 RA3 DGNDPLL GB3 RA4 DVCCPLL GB2 RA5 CLPIN GB1 RA6 SYNCIN2 AGNDAD3 AGNDAD3 CLAMP PULSE DGNDAD3 DGNDAD3 SYNCIN1 GB0 RA7 HSYNC 110 DGNDADTTL DVCCADTTL CLKIN DVCCADTTL DGNDADTTL XCLKIN GA5 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 GA7 RB0 EXT CLK 109 SOGOUT 1µ GA6 RB1 – 29 – RB2 EXT XCLK UNLOCK 5k AVCCAD3 Electrical Characteristics Measurement Circuit (3-wire Control) RB3 RB4 RB5 RB6 RB7 DVCCADTTL DGNDAD3 DGNDADTTL BA0 BA1 BA2 BA3 BA4 DGNDAD3 BA5 BA6 BA7 DVCCADTTL DGNDADTTL BB0 BB1 BB2 GNDAD3 BB3 BB4 BB5 BB6 BB7 DVCCADTTL DGNDAD3 DGNDADTTL GA0 GA1 GA2 GA3 GA4 A A A AVCC5V DVCC5V 3.3V DGND AGND CXA3506R – 30 – 1 1 DIVOUT signal delay control Delay sync output polarity control Hold input polarity control PLL PLL PLL 1 2 PLL PLL 2 Delay control (higher order) PLL DIVOUT signal pulse width control 6 Delay control (lower order) PLL 3 2 VCO frequency divider control Charge pump current control 12 Feedback programmable counter control PLL PLL bit Function Block Control Register Functions Table 2 00: 3CLK 01: 4CLK 10: 5CLK 11: 6CLK HOLD POL DSYNC POL DIVOUT DELAY 3 4 4 0: 4CLK 1: 5CLK 0: NEGATIVE 1: POSITIVE 0: NEGATIVE 1: POSITIVE 3 3 2 000000: 1/32CLK 111111: 64/32CLK 000: 100µA 001: 200µA 010: 300µA 011: 400µA 100: 500µA 101: 600µA 110: 700µA 111: 800µA 1 1 0 Register No. 00: 1/1 01: 1/2 10: 1/4 11: 1/8 Frequency division ratio = (m + 1) × 8 + n Control Range (typ.) 00: 1CLK 01: 2CLK DIVOUT WIDTH 10: 4CLK 11: 8CLK Charge.Pump COARSE DELAY FINE DELAY DIV1, 2, 4, 8 VCO DIV Register Name O m4 D7 O m3 D6 O O O m2 D5 O O O m1 D4 O O m8 m0 D3 Data O O m7 n2 D2 O O O m6 n1 D1 O O O m5 n0 D0 CXA3506R 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Phase comparison input positive/negative control Sync input polarity control SOG OUT polarity control Clamp pulse input polarity control External clock/internal VCO switching Delay sync output/DIVOUT switching Delay sync hold function Output SOG/HSYNC switching HSYNC1, 2 input/SOGA switching HSYNC1 input/HSYNC2 input switching TTL output off function (clock) TTL output off function (inverse clock) TTL output off function (1/2 clock) TTL output off function (inverse 1/2 clock) TTL output off function (delay sync) PLL PLL PLL PLL PLL PLL PLL PLL PLL PLL PLL PLL PLL PLL PLL 1 bit Function Block 4 4 4 5 5 5 5 5 5 6 6 6 6 6 0: NEGATIVE 1: POSITIVE 0: NEGATIVE 1: POSITIVE 0: EXT CLK 1: INT VCO 0: DIVOUT DSYNC By-pass 1: DSYNC 0: NORMAL 1: HOLD 0: SYNCT 1: SYNCP/HSYNC – 31 – 0: SYNCP 1: HSYNC1, 2 0: EXT SYNC1 1: EXT SYNC2 0: TTL out OFF 1: TTL out ON 0: TTL out OFF 1: TTL out ON 0: TTL out OFF 1: TTL out ON 0: TTL out OFF 1: TTL out ON 0: TTL out OFF 1: TTL out ON DSYNC Enable 1/2XCLK Enable 1/2CLK Enable XCLK Enable CLK Enable HSYNC 1/2 SYNCP/ HSYNC SYNC OUT SW DSYNC Hold VCO By-pass CLP POL SOG OUT POL SYNC POL PD POL 0: NEGATIVE 1: POSITIVE Register No. D7 4 Control Range (typ.) 0: NEGATIVE 1: POSITIVE Register Name D6 O O D5 O O O D4 O O O D3 Data O O O D2 O O D1 O O D0 CXA3506R – 32 – 8 9 10 11 12 13 14 15 16 16 00000000: Mgain = × 0.79 11111111: Mgain = 1.21 00000000: Mgain = × 0.79 11111111: Mgain = 1.21 00000000: Mgain = × 0.79 11111111: Mgain = 1.21 00000000: VRB – 61LSB SUB BRIGHTNESS R 11111111: VRB + 61LSB 0: RGB IN 1: YCbCr IN SUB CONTRAST R 00000000: VRB – 61LSB SUB BRIGHTNESS B 11111111: VRB + 61LSB 00000000: 128LSB – 16LSB 11111111: 128LSB + 16LSB SUB CONTRAST B 00000000: VRB – 61LSB SUB BRIGHTNESS G 11111111: VRB + 61LSB 00000000: 128LSB – 16LSB 11111111: 128LSB + 16LSB SUB CONTRAST G 0: AMP OUT RGB Out Select 1: SW OUT 8 8 6 6 1 1 Sub contrast Bch Sub contrast Rch Sub brightness Gch Sub brightness Bch Sub brightness Rch Cb input clamp level adjustment in YUV mode Cr input clamp level adjustment in YUV mode YCbCr input mode clamp level switching RGB OUT output signal selection SW output and AMP output RGB2 input selection AMP AMP AMP AMP AMP AMP AMP AMP AMP AMP 1 8 8 8 8 Sub contrast Gch AMP RGB In Select YCbCr mode Cr Offset Cb Offset 16 7 00000000: Mgain = × 0.78 11111111: Mgain = × 2.24 MAIN CONTRAST 8 Main contrast AMP SOG Enable 0: IN1 1: IN2 6 1 TTL output off function (SER OUT) REGISTER 0: TTL out OFF 1: TTL out ON 1 TTL output off function (SOG OUT) PLL UNLOCK Enable SEROUT Enable 1 6 Register No. 0: TTL out OFF 1: TTL out ON Control Range (typ.) 6 Register Name 0: TTL out OFF 1: TTL out ON bit TTL output off function (UNLOCK) Function PLL Block O O O O O O O O D7 O O O O O O O O D6 O O O O O O O O O O D5 O O O O O O O O O D4 O O O O O O O O O D3 Data O O O O O O O O O O D2 O O O O O O O O O O D1 O O O O O O O O O O D0 CXA3506R – 33 – 4 1 3 SYNC SEP threshold level setting during SYNC ON GREEN ADC DATA output polarity control DATA output mode switching ADC power save AMP power save PLL power save SYNC SEP power save SYNC SEP ADC ADC ADC AMP PLL SYNC SEP TTLOUT TTLOUT CLP LEVEL 2 SYNC SEP hysteresis level setting during SYNC ON GREEN SYNC SEP 2 1 1 1 1 1 bit Brightness clamp off Function AMP Block 17 17 00: 2mV 01: 20mV 10: 45mV 11: 70mV 0000: 75mV 10mV step 1111: 215mV 19 19 19 19 0: active 1: power save 0: active 1: power save 0: active 1: power save 00: 2.20V 01: 2.45V 10: 2.70V 11: 2.95V ADC Power Save AMP Power Save PLL Power Save TTLOUT CLP SYNC SEP Power Save 19 0: active 1: power save DATA OUT MODE 18 000: Straight 001: DMUX Parallel 010: DMUX Interleaved 011: YUV4:2:2 D2 111: YUV4:2:2 Special 18 16 Register No. D7 0: ON 1: OFF Control Range (typ.) 0: all 1 → all 0(NEGATIVE) DATA OUT POL 1: all 0 → all 1(POSITIVE) SYNC SEP VTH SYNC SEP VHYS Brightness CLP Register Name D6 O O D5 O O D4 O O O O D3 Data O O O D2 O O O D1 O O O D0 CXA3506R PLL AMP – 34 – Register 10 Register 9 Register 8 Register 7 Register 6 Register 5 Register 4 Register 3 Register 2 Register 1 Register 0 Register No. 0 0 Reference SUB CONTRAST R Reference SUB CONTRAST B Reference SUB CONTRAST G Reference MAIN CONTRAST 0 0 Fine Delay Bit1 0 VCODIV Bit9 0 VCODIV Bit1 D1 0 Fine Delay Bit0 1 VCODIV Bit8 0 VCODIV Bit0 D0 1 1 1/2XCLK Enable 1 1/2CLK Enable 0 DSYNC Hold 1 PD POL 0 1 XCLK Enable 1 DSYNC By-pass 1 HOLD POL 1 1 CLK Enable 1 VCO By-pass 1 DSYNC POL 1 20 (H) 15 (H) 38 (H) FF (H) 1B (H) 3F (H) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Sub Contrast R Sub Contrast R Sub Contrast R Sub Contrast R Sub Contrast R Sub Contrast R Sub Contrast R Sub Contrast R Bit5 Bit7 Bit6 Bit4 Bit3 Bit2 Bit1 Bit0 80 (H) 1 Sub Contrast B Sub Contrast B Sub Contrast B Sub Contrast B Sub Contrast B Sub Contrast B Sub Contrast B Sub Contrast B Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 80 (H) 1 Sub Contrast G Sub Contrast G Sub Contrast G Sub Contrast G Sub Contrast G Sub Contrast G Sub Contrast G Sub Contrast G Bit5 Bit7 Bit6 Bit4 Bit3 Bit2 Bit1 Bit0 80 (H) 1 Sub Address 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 0A (H) 09 (H) 08 (H) 07 (H) 06 (H) 05 (H) 04 (H) 03 (H) 02 (H) 01 (H) 00 (H) HEX code A4 A3 A2 A1 A0 HEX code Main Contrast Main Contrast Main Contrast Main Contrast Main Contrast Main Contrast Main Contrast Main Contrast Bit6 Bit5 Bit2 Bit1 Bit0 Bit4 Bit3 Bit7 80 (H) 1 1 1 Reference DSYNC Enable UNLOCK Enable SOG Enable SEROUT Enable 1 0 Reference TTLOUT ENABLE SYNC OUT SW SYNCP/ HSYNC IN HSYNC1/2 SYNC 1 1 1 SOGOUT POL SYNC IN POL 0 1 CLP POL POLARITY 0 Reference 1 1 Reference 0 DIVOUT DELAY 0 CP Reference Fine Delay Bit2 1 VCODIV Bit10 0 VCODIV Bit2 D2 DIVOUT Width DIVOUT Width Charge Pump Charge Pump Charge Pump Bit2 Bit1 Bit0 Bit1 Bit0 23 (H) Fine Delay Bit3 Fine Delay Bit4 Fine Delay Bit5 0 1 0 Reference Coarse Delay Coarse Delay Bit0 Bit1 VCODIV Bit11 DIV1, 2, 4, 8 Bit0 DIV1, 2, 4, 8 Bit1 VCODIV2 DELAY 1 1 1 0 0 Reference VCODIV Bit3 VCODIV Bit4 VCODIV Bit5 VCODIV Bit6 VCODIV Bit7 VCODIV1 D3 Data D4 D5 D6 D7 Register Name Register Assignment CXA3506R AMP SYNC SEP ADC – 35 – POWER SAVE Register Name Register 19 Register 18 Register 17 Register 16 Register 15 Register 14 1 Reference Reference POWER SAVE Reference OUTPUT MODE Reference D2 0 RGB In1/2 Select 0 Cr Offset Bit2 0 Cb Offset Bit2 0 Sub Brightness R Bit2 0 Sub Brightness B Bit2 0 Sub Brightness G Bit2 D1 D0 0 RGB Out Select 0 Cr Offset Bit1 0 Cb Offset Bit1 0 Sub Brightness R Bit1 0 Sub Brightness B Bit1 0 80 (H) 0 YCbCr mode 0 Cr Offset Bit0 0 Cb Offset Bit0 0 00 (H) 20 (H) 20 (H) Sub Brightness R 80 (H) Bit0 0 Sub Brightness B Bit0 0 0 1 1 TTLOUT CLP TTLOUT CLP Bit1 Bit0 1 0 0 Sync Sep Power Save 0 0 PLL Power Save 0 DATA OUT DATA OUT MODE MODE Bit2 Bit1 0 0 AMP Power Save 1 DATA OUT MODE Bit0 1 03 (H) 0 ADC Power Save 30 (H) 1 DATA OUT POL 0 Sub Address 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 13 (H) 12 (H) 11 (H) 10 (H) 0F (H) 0E (H) 0D (H) 0C (H) 0B (H) HEX code A4 A3 A2 A1 A0 HEX code Sub Sub Brightness G Brightness G 80 (H) Bit1 Bit0 Sync Sep VTH Sync Sep VTH Sync Sep VTH Sync Sep VTH Sync Sep VHYS Sync Sep VHYS Bit3 Bit2 Bit1 Bit0 Bit1 Bit0 22 (H) 0 Reference SYNCSEP Brightness CLP AMP MODE 0 Cr Offset Bit3 Cr Offset Bit4 Cr Offset Bit5 CrOFFSET 0 0 0 1 Reference Sub Sub Brightness R Brightness R Bit4 Bit3 0 0 Cb Offset Bit3 0 1 Sub Brightness R Bit5 Sub Brightness B Bit3 Sub Brightness B Bit4 Cb Offset Bit4 Sub Brightness R Bit6 Sub Brightness R Bit7 0 0 0 Cb Offset Bit5 0 1 Sub Brightness B Bit5 D3 CbOFFSET Sub Brightness B Bit6 Sub Brightness B Bit7 0 D4 Sub Sub Brightness G Brightness G Bit4 Bit3 0 0 1 D5 Sub Brightness G Bit5 0 D6 Sub Brightness G Bit6 D7 Sub Brightness G Bit7 Data 0 SUB Register BRIGHTNESS R 13 Reference SUB Register BRIGHTNESS B 12 Reference SUB Register BRIGHTNESS G 11 Reference Register No. CXA3506R CXA3506R Description of Operation Control Register Programmable control can be performed for many functions of this IC. 1) Mode selection Both I2C bus and 3-wire bus mode can be supported, and either of these modes can be selected by the 3WIRE/I2C (Pin 13). 3WIRE/I2C pin voltage 0V 1/2VCC VCC (5V) Setting mode I2C (High) I2C (Low) 3-wire bus The pin threshold voltages are set at 1/3VCC and 2/3VCC. 2) Threshold voltage In I2C bus mode, both SDA (Pin 9) and SCL (Pin 10) are input. These input logic signals can have two threshold voltages by the 3-wire/I2C. These threshold voltages have the following hysteresis. SDA, SCL pin threshold voltages I2C I2C (High) mode (Low) mode Threshold voltage (Low → High) Threshold voltage (High → Low) 1.95V 1.6V Threshold voltage (Low → High) Threshold voltage (High → Low) 1.65V 1.3V In 3-wire bus mode, the threshold voltages of the logic signal input to the SDA, SCL and XSENABLE pins have the following hysteresis. SDA, SCL and XSENABLE pin threshold voltages 3-wire bus mode Threshold voltage (Low → High) Threshold voltage (High → Low) 1.65V 1.3V – 36 – CXA3506R 3-wire Bus Mode Various control can be performed by setting the internal control register values via the serial interface comprised of the three pins SDA (Pin 9), SCL (Pin 10) and XSENABLE (Pin 11). Data can be accepted when XSENABLE is low level. When XSENABLE is high level, data cannot be accepted. The SDA pins of multiple IC can also be connected to the same bus line and each IC can be controlled independently by XSENABLE. XSENABLE may change the state when SCL is high level. 1) Write mode 8-bit control data consisting of a 7-bit sub address and 1-bit READ/WRITE setting is input in series from the LSB to the SDA pin. When READ/WRITE setting is "1", data can be written to register. When this IC is used in 3-wire bus mode, the sub address is 5 bits, so always set the 2 MSB bits to "0". Input the clock to the SCL pin. Data is loaded to the SDA pin at the rising edge of this clock. The data is set in the register at the rising edge of XSENABLE. The SDA and SCL pins are also used in I2C bus control mode. TENPW XSENABLE SCL SDA A0 A1 A2 A3 A4 LSB 0 A5 0 A6 1 MSB SUB ADDRESS D0 D1 D2 D3 D4 D5 LSB READ/WRITE D6 D7 MSB DATA READ/WRITE 0: READ Mode 1: WRITE Mode TENS TENH XSENABLE SCL SDA TDS TDH Set the VCO post-stage frequency divider (DIV1, 2, 4, 8) and programmable counter (VCODIV) in the following order. The data is set when Register1 is sent. Register0 (SUB ADDRESS (H): 00) ↓ Register1 (SUB ADDRESS (H): 01) – 37 – CXA3506R 2) Read mode Input the 7-bit sub address and 1-bit READ/WRITE setting to the SDA pin. When READ/WRITE setting is "0", the 8-bit internally set data is output in series from the LSB by the SEROUT (Pin 12). While data is being output from the SEROUT pin, don't care what data is input to the SDA pin. Use the read function to check whether the data is set correctly inside the IC. TENPW XSENABLE SCL SDA A0 A1 A2 A3 0 A5 A4 LSB 0 A6 0 MSB SEROUT D0 D1 D2 D3 D4 D5 LSB SUB ADDRESS D6 D7 MSB DATA READ/WRITE READ/WRITE 0: READ Mode 1: WRITE Mode TENS TENH XSENABLE SCL SDA SEROUT TDS TDH TD The SEROUT pin is TTL output. When not using the READOUT function, the TTL output circuit can be turned off by control register. Register: SEROUT ENABLE SEROUT output status 0 1 Function off Function on Power-on Reset When the power supply rises, the power-on reset circuit operates and all the control register data is set to "1". AMP, ADC, PLL and SYNCSEP are all set to power save mode, and all the TTL output pins are set to high impedance mode. Therefore, it is possible to share the same bus interface with other digital outputs having high impedance modes. – 38 – CXA3506R I2C BUS Mode Various control can be performed by setting the internal control register values via the serial interface comprised of the SDA (Pin 9) and SCL (Pin 10). This mode has only a write mode for setting data, and there is no read mode. Therefore, address "S0" set READ/WRITE is always "0". SLAVE ADDRESS S7 S6 S5 S4 S3 S2 S1 S0 1 0 0 1 1 x x 0 Four different kinds of slave address (IC address) can be set by externally setting the ADDRESS (Pin 2) to a specific voltage. 0V ADDRESS pin voltage SLAVE ADDRESS 1/3VCC 2/3VCC VCC (5V) 1001 1000 1001 1100 1001 1110 1001 1010 The pin threshold voltages are set to 1/4VCC, 1/2VCC and 3/4VCC. An 8-bit slave address (IC address), 8-bit sub address, and a number of 8-bit data strings are input in series from the MSB to the SDA pin. When this IC is used in I2C bus mode, sub address is 5 bits, and 3 bits of MSB side are set to always "0". ACK signal is returned from the IC to confirm that the data has been received for each 8-bit data. The sub address can be designated optionally. The sub address is auto-incremented in order from the designated sub address, and the data strings are loaded in succession. To set the data at a specific separated sub address, either send the stop condition and then reset the sub address, or also send the data of unchanged portions so that the data is continuous. Only auto-increment mode is supported, and the sub address + data + sub address + data mode where only specific sub addresses are designated is not supported. 0 SDA S7 S6 S5 S4 S3 S2 S1 S0 ACK SLAVE ADDRESS MSB LSB 0 0 A7 A6 A5 A4 A3 A2 A1 A0 ACK ACK D7 D6 D5 D4 D3 D2 D1 D0 SUB ADDRESS DATA D7 D6 D5 D4 D3 D2 D1 D0 ACK DATA SCL START CONDITION STOP CONDITION • START CONDITION When SCL pin is high level, the signal input to SDA pin has a falling edge, there is START CONDITION. • STOP CONDITION When SCL pin is high level, the signal input to SDA pin has a rising edge, there is STOP CONDITION. – 39 – CXA3506R I2C BUS Control Signals SDA TBUF TLOW TR_REG TF_REG THD;STA SCL P S THD;STA Sr THD;DAT THIGH TSU;DAT TSU;STA P TSU;STO Power-on Reset When the power supply rises, the power-on reset circuit operates and all the control register data are set to "1". AMP, ADC, PLL and SYNCSEP are all set to power save mode, and all the TTL output pins are set to high impedance mode. Therefore, it is possible to share the same bus interface with other digital outputs having high impedance modes. – 40 – CXA3506R Amplifier This is a 3-channel AMP that optimizes the AC coupled RGB analog input signals and YCbCr analog input signals for ADC input. Switch input mode between RGB input or YCbCr input with the control register. The AC coupled analog input signals are synchronously clamped by the externally input clamp pulse at a pedestal level. An input capacitor of 0.1µF is recommended. Allowing two lines of input to be selected for the analog input signal, the AMP includes a high frequency, low cross talk video switch circuit for input switching. Switching is performed using a control register. When using only one line, leave the unused line open. The input band of the analog input signal is 220MHz in the –3dB bandwidth range. There are main contrast and sub-contrast of the gain used to adjust the analog input signal to full scale (1V typ.) of the ADC. Each can be adjusted to one of 256 levels using control registers. Main contrast is controlled by moving the gain of the 3 RGB channels. The each gain of the 3 RGB channels can be controlled independently. In RGB input mode, the clamp level used for the black level adjustment can be adjusted independently for the 3 channels to any of 256 levels by using sub-brightness. The ∗CLP pin∗1 is connected to the hold capacitor of the clamp circuit for the sub-brightness. A hold capacitor of 0.1µF is recommended. The ∗OUT pins∗2 can output signal immediately before input to the ADC or the signal after switching between the two lines of input select switch. Either of them can be selected by control register. As for emitter follower output, since the internal bias current is small, be sure to connect an 820Ω resistor between the ∗OUT pins∗2 and AGND in order to view the signal with a high frequency. A 75Ω driver cannot be supported. In addition, load capacitance should be 5pF or less. When the SYNC ON GREEN signal is monitored at the ∗OUT pins∗2 after the two lines of select switch, the sync amplitude is a maximum of 0.3V, for a limiter is applied at the amplifier input stage. In YCbCr signal input mode, Y can be adjusted to any of 256 levels using the sub-brightness while Cb and Cr can be adjusted to any of 64 levels using the Cb or Cr offset. A detailed description of the above registers is given below. ∗1 ∗CLP pins: Overall naming for R/Cr CLP (Pin 130), G/Y CLP (Pin 128), B/Cb CLP (Pin 129) ∗2 ∗OUT pins: Overall naming for R/Cr OUT (Pin 3), G/Y OUT (Pin 143), and B/Cb OUT (Pin 1) • Analog input signal mode switching Analog input signal supports both RGB analog input signal and YCbCr analog input signal. This register switches the clamp level of the input clamp block and the amplifier output block in each mode. However, the G/Ych perform the same processing in both RGB input mode and YCbCr input mode. Register: YCbCr mode 0 1 Analog input signal mode RGB input YCbCr input • Input channel switching Input supports 2-channel input, and the input can be selected by an internal switch. Register: RGB In Select 0 1 Analog input signal channel switching IN1 IN2 • Clamp pulse input polarity The clamp pulse input polarity can be selected by an internal switch. Register: CLP POL 0 1 Clamp pulse polarity NEGATIVE POSITIVE – 41 – CXA3506R • Brightness clamp off function Clamp operation can be set to a mode where only the post-stage brightness clamp does not operate even if a clamp pulse is input to the CLPIN (Pin 113). At this time, all three channels of the ∗CLP pins∗1 are set to high impedance simultaneously, and the signal black level can be varied in an analog manner by setting the voltages externally. However, the voltage value set here is not related to the VRT (Pin 17) and VRB (Pin 93) voltages or the ∗OUT∗2 monitor signal output DC levels. Therefore the value should be set while monitoring the ADC data output or the data after that. Register: Brightness CLP 0 1 Clamp operation Clamp operation Clamp off • Monitor signal output selection The two monitor signal outputs (∗OUT pins∗2) of the amplifier can be selected by an internal switch. One is amplifier output signal immediately before input to the ADC, and other is after switching between the two lines of select switch. Register: RGB Out select Monitor output switching 1 0 Amplifier output Switch output • Main contrast The RGB channel gains can be set collectively by an 8-bit DAC setting. Register: MAIN CONTRAST 0 ··· 128 ··· 255 Amplifier gain (typ.) SUB CONTRAST = 128 0.78 ··· 1.53 ··· 2.24 • Rch sub contrast The Rch contrast (R amplifier gain) can be adjusted independently within the range of ±21% relative to the main contrast by an 8-bit DAC setting. Register: SUB CONTRAST R 0 ··· 128 ··· 255 Rch gain adjustment (typ.) –21% ··· 0% ··· +21% • Gch sub contrast The Gch contrast (G amplifier gain) can be adjusted independently within the range of ±21% relative to the main contrast by an 8-bit DAC setting. Register: SUB CONTRAST G 0 ··· 128 ··· 255 Gch gain adjustment (typ.) –21% ··· 0% ··· +21% • Bch sub contrast The Bch contrast (B amplifier gain) can be adjusted independently within the range of ±21% relative to the main contrast by an 8-bit DAC setting. Register: SUB CONTRAST B 0 ··· 128 ··· 255 Bch gain adjustment (typ.) –21% ··· 0% ··· +21% – 42 – CXA3506R • Rch sub brightness in RGB mode The Rch sub brightness (black level voltage) can be set by an 8-bit DAC during RGB signal input. The Rch sub brightness can be varied within the range of ±25% of the ADC input dynamic range (approximately 1V) centering on VRB (Pin 93) (approximately 1.9V). Register: SUB BRIGHTNESS R 0 ··· 128 ··· 255 Level shift amount (typ.) –61LSB ··· 0LSB ··· +61LSB Register: YCbCr mode 0 Input signal mode RGB • Gch sub brightness in RGB mode The Gch sub brightness (black level voltage) can be set by an 8-bit DAC during RGB signal input. The Gch sub brightness can be varied within the range of ±25% of the ADC input dynamic range (approximately 1V) centering on VRB (Pin 93) (approximately 1.9V). Register: SUB BRIGHTNESS G 0 ··· 128 ··· 255 Level shift amount (typ.) –61LSB ··· 0LSB ··· +61LSB Register: YCbCr mode 0 Input signal mode RGB • Bch sub brightness in RGB mode The Bch sub brightness (black level voltage) can be set by an 8-bit DAC during RGB signal input. The Bch sub brightness can be varied within the range of ±25% of the ADC input dynamic range (approximately 1V) centering on VRB (Pin 93) (approximately 1.9V). Register: SUB BRIGHTNESS B 0 ··· 128 ··· 255 Level shift amount (typ.) –61LSB ··· 0LSB ··· +61LSB Register: YCbCr mode 0 Input signal mode RGB • Cbch black level shift in YCbCr mode The Cbch black level voltage can be set by a 6-bit DAC during YCbCr signal input. The Cbch black level voltage can be varied within the range of ±16LSB centering on the ADC input dynamic range center ((VRT + VRB)/2). Register: Cb Offset 0 ··· 32 ··· 63 Level shift amount (typ.) 112LSB ··· 128LSB ··· 144LSB Register: YCbCr mode 1 Input signal mode YCbCr • Crch black level shift in YCbCr mode The Crch black level voltage can be set by a 6-bit DAC during YCbCr signal input. The Crch black level voltage can be varied within the range of ±16LSB centering on the ADC input dynamic range center ((VRT + VRB)/2). Register: Cr Offset 0 ··· 32 ··· 63 Level shift amount (typ.) 112LSB ··· 128LSB ··· 144LSB Register: YCbCr mode 1 Input signal mode YCbCr – 43 – CXA3506R • Input signal connection method Output Input Pin No. Symbol Pin No. Symbol Pin 124 Pin 126 G/YIN1 G/YIN2 68 to 75 GA0 to GA7 78, 81 to 85, 87, 88 GB0 to GB7 Pin 133 Pin 136 B/CbIN1 B/CbIN2 45 to 49, 51 to 53 56 to 58, 60 to 64 Pin 139 Pin 141 R/CrIN1 R/CrIN2 21, 22, 24 to 28, 31 RA0 to RA7 34 to 41 RB0 to RB7 BA0 to BA7 BB0 to BB7 1. When inputting both RGB and YCbCr, input according to the table above. 2. SYNCSEP is connected to G/YIN. 3. When inputting RGB and not using SYNCSEP, there is no difference between the three channels so the input order may be optional. 4. When inputting Y, Cb and Cr, be sure to input according to the table above. It is possible for only the R/Cr IN and B/Cb IN pins to be clamped to the center of the ADC input dynamic range. – 44 – CXA3506R SYNCSEP The SYNCSEP function can be used to separate and output the SYNC signal that is superimposed on the SYNC ON GREEN signal (including the SYNC ON Y signal). There are two major SYNCSEP circuits. One is the circuit for creating a SYNC signal to be input to the PLL, and the other is a circuit for outputting a SYNC signal from the SOGOUT (Pin 105) so that a clamp pulse can be created externally. These SYNCSEP circuits perform processing on entirely different channels. (See the block diagram for the SYNCSEP operational description.) • SYNCSEP circuit for the PLL SYNC signal In the case of the SYNC ON GREEN signal, the SYNC ON GREEN signal is AC coupled to the G/YIN1 (Pin 124) or the G/YIN2 (Pin 126) and the sync component is separated and used as a reference. An input capacitor of 0.1µF is recommended. When a signal is input to this pin, the pedestal level is clamped by a clamp pulse input to the CLPIN (Pin 113). After this, the signal is split into a signal to the amplifier circuit and the signal to the SYNCSEP circuits, and the SYNC signal is sent through a two lines of input select switch (SW SOGP) and the SYNC signal is separated by the SYNCSEP circuits. At this time, it is possible to minimize the jitter of the SYNC signal sent to the PLL by using a control register to select the threshold level (VTH) and hysteresis level (VHYS) of the SYNCSEP circuit according to the type of noise on the superimposed SYNC signal. SOG SYNC SEP threshold (Versus pedestal level) Register: SYNC SEP VTH 0000 ··· 1111 Threshold 75mV 9.3mV step 215mV SYNC signal Pedestal level VTH SOG SYNC SEP hysteresis VHYS Register: SYNC SEP VHYS 00 01 10 11 Hysteresis 2mV 20mV 45mV 70mV The SYNC signal separated by the SYNCSEP circuits can be switched at the SW PLL circuit with an externally input SYNC signal (the SYNC signal input from the SYNCIN1 or SYNCIN2 pin) by using control registers (SYNCP/HSYNC). The selected signal is input to the PLL block. Selecting between the sync separated SYNC signal and the externally input SYNC signal Register: SYNCP/HSYNC IN 0 1 SYNC signal type Sync separated signal Externally input SYNC signal SYNC signal input pin G/YIN1 pin G/YIN2 pin SYNCIN1 pin SYNCIN2 pin – 45 – CXA3506R • SYNCSEP circuits for the SYNC signal for the clamp pulse A SYNC ON GREEN signal is input to the SOGIN1 (Pin 132) or SOGIN2 (Pin 135). The AC coupled signal is internally sync tip clamped and the minimum level (bottom of sync) is turned into the internally-set DC level (approximately 2.8V). The sync tip clamped input signal is separated from the threshold of 165mV (at SYNC DUTY 5%) above from the bottom of the sync by the SYNCSEP circuit. After this, the signal is output at TTL level from the SOGOUT pin and used as a reference signal for generating a clamp pulse. Since no clamp pulse is required for the sync tip clamp, it is possible to output a SYNC signal from the SOGOUT pin even when there is no external clamp pulse present such as when power supply is turned on. An input capacitor of 0.1µF is recommended. A control register can be used to select output either the SYNC signal separated out from the signal input from the SOGIN1 pin or the SOGIN2 pin by SW SOG O or the previously described PLL SYNC signal output from the SW PLL circuit. Output from the SOGOUT pin SYNCT1, SYNCT2/SYNCP1, SYNCP2/SYNCIN1, SYNCIN2 output selection SYNCT1, SYNCT2: The SYNC signal sync tip clamped and separated from the SOGIN1 and SOGIN2 pins SYNCP1, SYNCP2: The SYNC signal pedestal clamped and separated from the G/YIN1 and G/YIN2 pins SYNCIN1, SYNCIN2: The SYNC signal input from the SYNCIN1 and SYNCIN2 pins Register: SYNC OUT SW 1 0 Output from the SOGOUT pin SYNCT1, SYNCT2 SYNCP1, SYNCP2 or SYNCIN1, SYNCIN2 The SOGIN1, SOGIN2 and the previously described G/YIN1, G/YIN2 are interlocked as for the 2-ch selection (Register: RGB In Select). Input channel selection Register: RGB In Select 0 1 G/YIN pin selection IN1 IN2 SOGIN pin selection IN1 IN2 The polarity of signals output from the SOGOUT pin can be set by using registers. Register: SOGOUT POL 0 1 SOGOUT output polarity Negative Positive • SYNC ON GREEN output enable When the SOGOUT pin is not used, it is possible to turn off the TTL output using a control register. But it cannot be set to high impedance. Register: SOG Enable 0 1 SOGOUT output status Off On – 46 – CXA3506R PLL • SYNC signal input The SYNC (HSYNC) used by the PLL is input from the SYNC signal input pins. There are two sets of input pins, SYNCIN1 (Pin 111) and SYNCIN2 (Pin 112), which are switched by the control register. SYNCIN1 input, SYNCIN2 input switching Register: HSYNC1/2 0 1 SYNC signal input pin SYNCIN1 SYNCIN2 SYNC signals within the range from 10kHz to 100kHz can be input. The input supports both positive and negative polarity. SYNC signal input polarity Register: SYNC POL 0 1 SYNC signal input polarity Negative Positive Set the register in accordance with the polarity of the externally input SYNC. When SYNC is positive polarity, set SYNC POL to "1". (Clock is generated in sync with the rising edge of SYNC.) When SYNC is negative polarity, set SYNC POL to "0". (Clock is generated in sync with the falling edge of SYNC.) When there is no SYNC input, the VCO oscillates at random and a random pulse is output from the CLK output. LPF SYNC signal PD CP VCO A DIV 1, 2, 4 ,8 Programmable counter B Point A: VCO oscillation frequency Point B: Clock frequency • Phase detector (PD) The phase detector compares the phase of the SYNC signal with that of the programmable counter output signal. The phase comparison is performed at the edge, and a phase difference between the compared signals is output as a pulse. There is no hysteresis function for the input pins of the SYNC signal (SYNCIN1 and SYNCIN2) input to the phase detector. If necessary external waveform shaping should be done as jitter results when a noisy signal is input. Set the control register, PD POL, to "1" as for the input polarity of the phase detector. • Hold function The hold function holds the VCO input voltage and generates oscillation itself without performing phase comparison. The VCO oscillation frequency is held during this period without performing phase comparison, by inputting the HOLD signal from the HOLD (Pin 106). HOLD signal polarity can be set by using the control register: HOLD POL. Register: HOLD POL 0 1 HOLD signal input polarity Held while HOLD signal is Low Held while HOLD signal is High For details, see the hold timing diagram. – 47 – CXA3506R • Charge pump (CP) The charge pump sets charge pump current to flow for the amount of time corresponding to the pulse width output from the phase detector. The phase detector gain is determined by the charge pump current. The amount of current can be varied by using a control register. This IC is used to set the charge pump current value according to the VCO oscillation frequency as given below. [CP Setting Matrix] VCO oscillation frequency: 40MHz to 85MHz: 85MHz to 110MHz: 110MHz to 140MHz: 140MHz to 155MHz: 155MHz to 165MHz: CP setting values 200µA 300µA 400µA 500µA 600µA The VCO oscillation frequency is that at the Point A in the diagram. Register: Charge Pump Bit2 0 0 0 0 1 1 1 1 Register: Charge Pump Bit1 0 0 1 1 0 0 1 1 Register: Charge Pump Bit0 0 1 0 1 0 1 0 1 Charge pump current 100µA 200µA 300µA 400µA 500µA 600µA 700µA 800µA • Loop filter (LPF) The control voltage input to the VCO is the pulse current output from the charge pump circuit that is smoothed by an integrating circuit (loop filter). The resistor and capacitor values of the integrating circuit are as follows. (For the circuit configuration, see the application circuit.) C1 = 0.33µF C2 = 330pF R1 = 3.3kΩ For the resistor and capacitors, use a metal film chip resistor with little temperature variation and ceramic chip capacitors. In particular, the 0.33µF capacitor should be equivalent to high dielectric constant series capacitor type B or better. (Electrostatic capacitance change ratio ±10%: T = –25 to +85°C) In case of using any resistors or capacitors except those given above, it is not guaranteed. • VCO The VCO oscillation frequency range covers from 40MHz to 165MHz. – 48 – CXA3506R • VCO frequency dividers (DIV 1, 2, 4, 8) The oscillation frequency of the VCO can be divided to 1/1, 1/2, 1/4, or 1/8 according to a control register setting. Depending on the combination of the VCO oscillation frequency and VCO frequency divider, the Point B clock frequency covers an operating range of 5MHz to 120MHz. The matrix of the VCO frequency divider setting is as follows. [VCO Frequency Divider Setting Matrix] Clock frequency: DIV setting value 5MHz to 14MHz: 1/8 14MHz to 40MHz: 1/4 40MHz to 80MHz: 1/2 80MHz to 120MHz: 1/1 Register: DIV 1, 2, 4, 8 Bit1 0 0 1 1 Register: DIV 1, 2, 4, 8 Bit0 0 1 0 1 Counter frequency 1/1 1/2 1/4 1/8 • Programmable counter The clock frequency at Point B is divided and a programmable counter output signal is generated. The frequency division ratio can be set optionally by using a 12-bit control register. This is determined by using lower order 3 bits and upper order 9 bits in the following formula. Frequency division ratio = (m + 1) × 8 + n m: 9 bits (VCO DIV Bit 3 to 11) n: 3 bits (VCO DIV Bit 0 to 2) Register No. Register Name Data7 MSB Data6 Data5 Data4 Data3 Data2 Data1 Data0 LSB Register 0 VCODIV1 m4 m3 m2 m1 m0 n2 n1 n0 Register 1 VCODIV2 m8 m7 m6 m5 After the set value for the frequency division ratio is changed, that set value is loaded into the programmable counter when the output value of the programmable counter becomes "all 0". • Clock output When the input polarity of the SYNC signal is positive, the clock output is synchronized to the rising edge of the SYNC signal and is available as complementary signals CLK (Pin 99) and XCLK (Pin 98). The delay time of the clock output can be varied in the range of 1/32CLK to 64/32CLK by using a control register (see PLL timing diagram). Although the clock output can be turned off independently by using a control register, it cannot be set to high impedance. The operational frequency of the clock is up to 100MHz. Register: CLK Enable, XCLK Enable 0 1 Clock output status Off On – 49 – CXA3506R • 1/2 clock output 1/2 clock signal is a signal that resets the clock by using a reset pulse created from an internal delay sync signal and divides the clock in half. The complementary signal is output from the 1/2CLK (Pin 101) and 1/2XCLK (Pin 100). (See the PLL timing diagram). Although the 1/2 clock output can also be independently turned off by the control register, it cannot be set to high impedance. Register: 1/2CLK Enable, 1/2XCLK Enable 0 1 1/2 Clock Output Status Off On • Delay sync output Two types of delay sync signal (DSYNC and DIVOUT) can be output from the DSYNC/DIVOUT (Pin 103). This is selected by switching a control register. The DSYNC signal is output as the input SYNC signal undergone timing control. The DIVOUT signal is output as the programmable counter output undergone timing control. Both can be used as reset signals for any connected IC such as a scaling IC. Delay sync output signal (DSYNC/DIVOUT (Pin 103)) 0 Register: DSYNC By-pass Signal output from the DSYNC/DIVOUT pin 1 DIVOUT signal DSYNC signal • DSYNC signal A SYNC signal input that has been timing controlled by a clock generated by a PLL is output. Although only the forward edge is completely managed at this time with delay settings, etc., the back edge has an undefined width for one clock cycle because it latches and outputs the input SYNC signal. • DIVOUT signal A timing controlled programmable counter output signal is output. In addition to the COARSE DELAY that has been set by using the DSYNC signal, the delay time setting is output with a delay of 4 or 5 clocks. The pulse width is also managed by a clock. [Function Correspondence Table for the DSYNC Signal/DIVOUT Signal] Function DSYNC signal DIVOUT signal Register COARSE DELAY 3CLK to 6CLK 3CLK to 6CLK COARSE DELAY FINE DELAY 1/32CLK to 64/32CLK 1/32CLK to 64/32CLK FINE DELAY Pulse width Fixed (depends on input SYNC signal width) 1, 2, 4, 8CLK DIVOUT WIDTH DIVOUT DELAY — 4, 5CLK DIVOUT DELAY Output polarity On/Off On/Off DSYNC POL Output enable On/Off On/Off DSYNC Enable Output during HOLD On/Off On/Off DSYNC Hold – 50 – CXA3506R • Delay time setting (Fine Delay/Coarse Delay) The delay sync output, clock output, and 1/2 clock output can make delay time setting (Fine Delay/Coarse Delay) for the input signal. The amount of delay time is from 3CLK Delay to 6CLK Delay for Coarse Delay and from 1/32CLK to 64/32CLK for Fine Delay. The delay time (Fine Delay/Coarse Delay) can be set by using the control registers shown below. Register: FINE DELAY 000000 000001 · · · · · · · · · · 111111 Delay time 1/32CLK 2/32CLK · · · · · · · · · · 64/32CLK Register: COARSE DELAY 00 01 10 11 Delay time 3CLK 4CLK 5CLK 6CLK • DIVOUT signal output pulse width The pulse width of the DIVOUT signal output can be set to 1, 2, 4, 8 clock pulse widths by using a control register. Register: DIVOUT WIDTH 00 01 10 11 DSYNC signal width 1CLK 2CLK 4CLK 8CLK • DIVOUT signal output delay time setting The DIVOUT signal is output with 4 or 5 clock delay based on the delay time (Fine Delay/ Coarse Delay) set as described above. The clock delay time can be set by using a control register. Register: DIVOUT DELAY 0 1 Delay time 4CLK 5CLK • Delay sync output polarity The polarity of the delay sync signal output from the DSYNC/DIVOUT pin can be selected either negative or positive by using a control register. Register: DSYNC POL 0 1 Delay sync output polarity Negative Positive • Delay sync output status Although it is possible to turn off the signal output from the DSYNC/DIVOUT pin by using a control register, it cannot be set to high impedance. Register: DSYNC Enable 0 1 Delay sync output status Off On – 51 – CXA3506R • Delay sync output status during hold Register: The delay sync output during the hold period can be controlled with the DSYNC Hold register and the HOLD signal. Register: DSYNC Hold 0 1 Delay sync output status Using HOLD signal logic DSYNC signal/DIVOUT signal The output status resulting from this setting differs based on status of the DSYNC By-pass register. Register: DSYNC Hold Register: DSYNC By-pass HOLD signal logic (When HOLD POL register = 1) Delay sync output 0 0 H L 0 0 L DIVOUT signal 0 1 H L 0 1 L DSYNC signal 1 0 H DIVOUT signal 1 0 L DIVOUT signal 1 1 H DSYNC signal 1 1 L DSYNC signal The values given in the above table are for when the DSYNC POL register is set to "1". The delay sync output status is reversed when DSYNC POL is set to "0". • XTLOAD signal (reset signal) This input pin forces to reset the divider function of the programmable counter. Since this signal is not normally used, leave it open or fix to high level. When it is used, this signal is in conjunction with the HOLD signal. See the note given later regarding the combined use of these signals. XTLOAD pin L H Programmable counter status Forcible reset Count – 52 – CXA3506R Register: The DSYNC Hold register and HOLD signal can be used to control the delay sync output during the hold period. The relationship between the delay sync output and the SYNC signal is shown below. (For each of CASE 1 to 3, the DSYNC POL register is "1". In addition, the DSYNC signal output and DIVOUT signal output can be switched by using the DSYNC By-pass register.) CASE 1 SYNC signal (SYNC POL = 1) HOLD signal (1) DSYNC Hold = 1 DSYNC signal DIVOUT signal (2) DSYNC Hold = 0 DSYNC signal DIVOUT signal – 53 – CXA3506R CASE 2 SYNC signal (SYNC POL = 1) HOLD signal (1) DSYNC Hold = 1 DSYNC signal DIVOUT signal (2) DSYNC Hold = 0 DSYNC signal DIVOUT signal – 54 – CXA3506R CASE 3 SYNC signal (SYNC POL = 1) HOLD signal (1) DSYNC Hold = 1 DSYNC signal DIVOUT signal (2) DSYNC Hold = 0 DSYNC signal DIVOUT signal – 55 – CXA3506R Notes on Using the HOLD Signal and XTLOAD Signal (Reset Signal) If the cycle of the SYNC signal is lost, the phase difference between the SYNC signal and the programmable counter output in the phase detector will increase, and it will cause PLL unlock. At this time, the HOLD signal is input to the HOLD (Pin 106), phase comparison is stopped while the signal is high level (when the HOLD POL register is set to "1"), and the clock can be stably oscillated by holding the VCO oscillation frequency. Note, however, the correspondence differs depending on whether the number of locations where the SYNC signal period changes (the 0.5H region in the diagram) is odd or even. LPF SYNC signal PD CP DIV 1, 2, 4, 8 VCO Clock output Programmable counter Case 1: When the 0.5H region is even (correspondence with HOLD signal only) SYNC signal (SYNC POL = 0) H H 1 2 3 4 0.5H 0.5H 0.5H 0.5H H H Programmable counter output signal HOLD signal When the number of the 0.5H period is even, it is possible to hold the period of the programmable counter output stable by applying the HOLD signal before the frequency changes. This corresponds to the vertical blanking period of the composite sync (computer signal). Case 2: When the 0.5H region is odd (correspondence with HOLD signal + XTLOAD signal (reset signal)) SYNC signal (SYNC POL = 0) H 1 2 3 0.5H 0.5H 0.5H H H H H Programmable counter output signal HOLD signal 8CLK XTLOAD signal (reset signal) ∗ "HSYNC" and "XTLOAD" are synchronized Tw (min) = 100ns When the number of the 0.5H period is odd, if only the HOLD signal is used, the phase difference between the SYNC signal and the programmable counter output signal will increase in the extra 0.5H region and the lock will be lost momentarily. In this case, the 0.5H region is held by the HOLD signal, and it is possible to use the XTLOAD signal (reset signal) at 1H backward to the official counter period by resetting/setting the counter value. Although there are no particular restrictions on the setup time and hold time of the XTLOAD signal (reset signal), the pulse width of the XTLOAD signal (reset signal) is restricted while the HOLD signal is high. (When the HOLD POL register is set to "1".) If the rising edge of the XTLOAD signal (reset signal) is delayed by 8CLK from the falling edge of the SYNC signal, counter output will be obtained by synchronizing with the falling edge of the next SYNC signal. See the diagram for details on timing. – 56 – CXA3506R • HOLD signal timing SYNC signal (when SYNC POL = 1) SYNC signal (when SYNC POL = 0) DIVOUT signal (when DSYNC POL = 0) Thh Ths Thh Ths Thold HOLD signal (when HOLD POL = 1) VCO oscillation frequency is held without performing phase comparison. Clock output The HOLD signal setup time (Ths) is the time from the rising edge of the HOLD signal to the falling edge of the DIVOUT signal. The HOLD signal hold time (Thh) is the time from the falling edge of the DIVOUT signal to the rising edge of the HOLD signal. See the above timing diagram for details on the relationship with SYNC POL. The frequency variation of CLK while held can be calculated as given below. ∆V I +Q SW –Q C VCO ∆f Ileak SW I C · ∆V = Q = Ileak · Thold C: Loop filter capacitance ∆V: Varying voltage due to leak current Ileak: Leak current of the internal amplifier Thold: Hold time ∆V = Ileak · Thold/C ∆f = ∆V · KVCO = Ileak · Thold/C · KVCO For example, Assuming f = 100MHz, Ileak = 1nA, Thold = 1ms, C = 0.33µF, KVCO = 2π · 55 [MHz/V], ∆V = 1 · 10–9 · 1 · 10–3/(0.1 · 10–6) = 3 · 10–6 [V] ∆f = 1 · 10–9 · 1 · 10–3/(0.1 · 10–6) · 2π · 70 · 106 = 1050 [Hz] – 57 – CXA3506R • UNLOCK timing If the phase difference between the SYNC signal input and the programmable counter output signal to the phase detector (PD) increases, it becomes impossible for the VCO to maintain stable oscillation. This status is converted into the UNLOCK signal and output. It is possible to perform analog lock/unlock by connecting an external circuit to this pin. IC internal IC external Vcc I2 R1 R3 50kΩ 104 Signal from the phase detector UNLOCK detect Vcc S2 signal Q1 S1 signal R2 I1 UNLOCK signal C1 R1 = 100Ω R2 = 100kΩ C1 = 0.01µF The UNLOCK output is an open collector. By connecting the external circuit shown above to this output pin, it is possible to adjust the sensitivity of the S2 signal by varying the constants R1, R2 and C1. (The constants R1, R2 and C1 above are reference values. The resistor R3 should be 50kΩ and Q1 should be 2SC series. The operations of the three cases are described below. Case 1: When there is no phase difference (PLL locked status) The S1 signal is low and the S2 signal is high. The UNLOCK signal is low. H S1 signal L H Threshold level of the inverter S2 signal L H UNLOCK signal L Case 2: When there is a phase difference, the S1 signal will goes low and high as shown in the figure below. At this time, the falling edge slew rate of the S2 signal is determined by the current I1 flowing into this open collector. The falling edge slew rate of the S2 signal will therefore be delayed as resistor R1 increases. In addition, since the rising edge slew rate of the S2 signal is determined by the current I2, the rising edge slew rate of the S2 signal will become faster as the resistor R2 decreases. If the integrated S2 signal does not fall below the threshold level of the next inverter, the UNLOCK signal will remain low. This will therefore be judged as locked even if there is a phase difference. H S1 signal L H Threshold level of the inverter S2 signal L H UNLOCK signal L Case 3: However, even if the same phase difference as described above is assumed, the decreasing resistor R1 will increase the current I1 flowing into the open collector. The falling edge slew rate of the S2 signal will therefore become faster. In addition, if resistor R2 is increased, the rising edge slew rate of the S2 signal will become slower. If the integrated S2 signal is under the threshold level of the next inverter, the UNLOCK signal will go from low to high and the PLL will be judged as unlocked. H S1 signal L H Threshold level of the inverter S2 signal L H UNLOCK signal L – 58 – CXA3506R The CXA3506R's charge pump is a constant-current output type as shown below. When a constant-current output charge pump circuit is used inside the PLL, the phase detector (PD) output acts as a current source, and the dimension of its transmittance KPD is A/rad. Also, when considering the VCO input as a voltage, the LPF transmittance dimension must be expressed in ohms (Ω = V/A). Therefore, the PLL transmittance when a constant-current output charge pump circuit is used is as follows. VCC S1 To LPF S2 ωr 1/S θr + – PD LPF VCO KPD (A/rad) F (S) (Ω) KVCO (rad/S/V) θo N counter 1/S 1/N ω /N 0 The PLL closed loop transmittance is obtained by the following formula. θo/N θr = KPD · F (S) · KVCO · 1/N · 1/S 1 + KPD · F (S) · KVCO · 1/N · 1/S ...(1) Here, KPD, F(S) and KVCO are: KPD: Phase comparator gain (A/rad) F(S): Loop filter transmittance (Ω) KVCO: VCO gain (rad/s/V) ∗1 The reason for the 1/S inside the phase detector is as follows. θo (t)/N = ∫ ot ω0 (t)/Ndt + θo (t = 0)/N: (a) θo (t = 0) = 0 θo (t)/N = ∫ ot ω0 (t)/Ndt: (b) Performing Laplace conversion: 1 θo (S)/N = s W0 (S)/N: (c) – 59 – ω0 CXA3506R The loop filter F(S) is described below. The loop filter smoothes the output pulse from the phase detector (PD) and inputs it as the DC component to the VCO. In addition to this, however, the loop filter also functions as an important element in determining the PLL response characteristics. Typical examples of loop filters include lag filters, lag-lead filters, active filters, etc. However, the CXA3506R's LPF is a current input type active filter as shown below, so the following calculations show an actual example of deriving the PLL closed loop transmittance when using this type of filter and then using this transmittance to create a formula for setting the filter constants. Current input type active filter C R ii –A –1 Vo –Vo The filter transmittance is as follows. Gain [dB] log scale The Bode diagram for formula (2) is as follows. Vo 1 + Vo = (R + ) · ii A SC F (S) = = 1 + SRC A · SC 1+A 1 + Sτ SC · 1 τ log ω A 1+A ∴τ = RC log ω Phase [deg] 0 Here, assuming A > 1, then: F (S) = 1 + Sτ SC ........................(2) –90 Next, substituting (2) into (1) and obtaining the overall closed loop transmittance for the PLL: θo/N θr KPD · KVCO · τ NC = S2 + ωn = ζ= KPD · KVCO · τ NC 2ζωnS + ωn2 S2 + 2ζωnS + ωn2 = √ KPD · KVCO NC 1 2 ·S+ KPD · KVCO NC ...(3) KPD · KVCO ·S+ NC .................................................(4) .................................................(5) ωnτ .....................................................................(6) – 60 – –45deg CXA3506R Here, ωn and ζ are as follows. ωn characteristic angular frequency: The oscillatory angular frequency when PLL oscillation is assumed to have been maintained by the loop filter and individual loop gains is called the characteristic angular frequency: ωn. ζ damping factor: This is the PLL transient response characteristic, and serves as a measure of the PLL stability. It is determined by the loop gain and the loop filter. A capacitor C2 is added to the actual loop filter. This added capacitor C2 is used to reduce the R noise, and a value of around 1/10 to 1/1000 of C1 should be selected as necessary. Current input type active filter with added capacitor C2 C2 C1 R ii –A –1 Vo –Vo The Bode diagram for formula (3) is as follows. The filter transmittance is as follows. = 1 + C1 · R · S S ((C1 + C2) + C1 · C2 · R · S) 1 + τ1 · S S (C1 + C2) (1 + τ2 · S) Gain [dB] log scale F (S) = ...................(3) τ1 = C1 · R τ2 = 1 τ1 log ω C1 · C2 · R C1 + C2 log ω Phase [deg] 0 Here, assuming C2 = C1/100, then: τ2 = C1 · C1/100 · R C1 + C1/100 = 1 C1 · R 101 = 1 τ1 101 –90 – 61 – –45deg 1 τ2 CXA3506R Next, the various parameters inside an actual CXA3506R are obtained. The CXA3506R's charge pump output block and the LPF circuit are as follows. C2 R1 C1 119 118 CXA3506R VCC 100µA 333 to 100µA step S1 800µA To VCO 100µA S2 to 100µA step 800µA 20k 100 First, KPD is as follows. KPD = 100µ/2π or 200µ/2π or 300µ/2π or 400µ/2π or 500µ/2π or 600µ/2π or 700µ/2π or 800µ/2π (A/rad) Typical KVCO characteristics curves for the CXA3506R's internal VCO are as follows. 200 VCO frequency [MHz] VCO DIV = 1/1 150 VCO DIV = 1/2 100 VCO DIV = 1/4 50 VCO DIV = 1/8 2 3 4 VCO input voltage [V] Therefore, KVCO is as follows. KVCO = 2π · 55 or 2π · 27.5 or 2π · 13.75 or 2π · 6.875 (rad/s/V) – 62 – CXA3506R ωn and ζ calculated for various types of computer signals are shown below. Here, the various parameters are as follows. FSYNC: Input sync frequency, FCLK: Output clock frequency KPD × 2π: Phase comparator gain × 2π (KPD × 2π = 100 or 200 or 300 or 400 or 500 or 600 or 700 or 800) KVCO/2π: VCO gain (when VCO DIV = 1/1, KVCO/2π = 55) (when VCO DIV = 1/2, KVCO/2π = 55/2) (when VCO DIV = 1/4, KVCO/2π = 55/4) (when VCO DIV = 1/8, KVCO/2π = 55/8) N: Counter value, C1: Loop filter capacitance value, R1: Loop filter resistance value MODE Resolution FSYNC FCLK KPD × 2π C.Pump setting KVCO DIV N 1, 2, 4, 8 C1 /2π setting setting bit2 bit1 bit0 M/(S∗V) bit1 bit0 R1 ωn fn ζ VCO oscillation frequency kHz MHz µA NTSC 15.73 12.27 300 0 1 0 55/8 1 1 780 0.33 3.3 2.83 0.45 1.54 98.18 NTSC 15.73 18.41 200 0 0 1 55/4 1 0 1170 0.33 3.3 2.67 0.42 1.45 73.64 NTSC 15.73 24.55 300 0 1 0 55/4 1 0 1560 0.33 3.3 2.83 0.45 1.54 98.18 NTSC 15.73 27.00 300 0 1 0 55/4 1 0 1716 0.33 3.3 2.70 0.43 1.47 108.00 PAL 15.63 14.69 200 0 0 1 55/4 1 0 940 0.33 3.3 2.98 0.47 1.62 58.75 PAL 15.63 22.03 300 0 1 0 55/4 1 0 1410 0.33 3.3 2.98 0.47 1.62 88.13 PAL 15.63 29.38 400 0 1 1 55/4 1 0 1880 0.33 3.3 2.98 0.47 1.62 117.50 µF kΩ kHzrad kHz MHz PAL 15.63 27.00 300 0 1 0 55/4 0 1 1728 0.33 3.3 2.69 0.43 1.46 108.00 480p 31.47 72.00 500 1 0 0 55/2 0 1 2288 0.33 3.3 4.27 0.68 2.32 144.01 1080i 33.75 74.25 500 1 0 0 55/2 0 1 2200 0.33 3.3 4.35 0.69 2.37 148.50 720p 45.00 74.25 500 1 0 0 55/2 0 1 1650 0.33 3.3 5.03 0.80 2.74 148.50 PC-98 640 × 400 24.82 21.05 200 0 0 1 55/4 1 0 848 0.33 3.3 3.13 0.50 1.71 84.19 VGA 640 × 480 31.47 25.18 300 0 1 0 55/4 1 0 800 0.33 3.3 3.95 0.63 2.15 100.70 MAC 640 × 480 35.00 30.24 400 0 1 1 55/4 1 0 864 0.33 3.3 4.39 0.70 2.39 120.96 VESA 640 × 480 37.86 31.50 400 0 1 1 55/4 1 0 832 0.33 3.3 4.48 0.71 2.44 126.00 SVGA 800 × 600 35.16 36.00 500 1 0 0 55/4 1 0 1024 0.33 3.3 4.51 0.72 2.46 144.02 SVGA 800 × 600 37.88 40.00 600 1 0 1 55/4 1 0 1056 0.33 3.3 4.87 0.77 2.65 160.01 SVGA 800 × 600 46.88 49.51 300 0 1 0 55/2 0 1 1056 0.33 3.3 4.87 0.77 2.65 99.01 SVGA 800 × 600 48.08 50.00 300 0 1 0 55/2 0 1 1040 0.33 3.3 4.90 0.78 2.67 100.01 SVGA 800 × 600 53.67 56.25 400 0 1 1 55/2 0 1 1048 0.33 3.3 5.64 0.90 3.07 112.49 MAC 832 × 624 49.72 57.28 400 0 1 1 55/2 0 1 1152 0.33 3.3 5.38 0.86 2.93 114.55 XGA 1024 × 768 48.36 65.00 400 0 1 1 55/2 0 1 1344 0.33 3.3 4.98 0.79 2.71 129.99 XGA 1024 × 768 56.48 75.01 500 1 0 0 55/2 0 1 1328 0.33 3.3 5.60 0.89 3.05 150.01 XGA 1024 × 768 60.02 78.75 600 1 0 1 55/2 0 1 1312 0.33 3.3 6.17 0.98 3.36 157.49 MAC 1024 × 768 60.24 80.00 600 1 0 1 55/2 0 1 1328 0.33 3.3 6.14 0.98 3.34 160.00 1024 × 768 68.68 94.50 300 0 1 0 55/1 0 0 1376 0.33 3.3 6.03 0.96 3.28 94.50 XGA • CP setting matrix • DIV setting matrix Internal VCO oscillation frequency: CP setting value Output oscillation frequency: DIV setting value 40MHz to 85MHz: 200µA 5MHz to 14MHz: 1/8 85MHz to 110MHz: 300µA 14MHz to 40MHz: 1/4 110MHz to 140MHz: 400µA 40MHz to 80MHz: 1/2 140MHz to 155MHz: 500µA 80MHz to 120MHz: 1/1 155MHz to 165MHz: 600µA – 63 – CXA3506R CLK Jitter Evaluation Method The generated CLK is obtained by inputting Hsync to the CXA3506R. Apply this CLK to a digital oscilloscope and observe the CLK waveform using Hsync as the trigger. Pulse generator Hsync signal CXA3506R trigger Digital oscilloscope ch1 Clock H Back sync porch Active video Front porch Computer signal 15 to 25% of Tsync Hsync signal Tsync = 1/fsync Clock Trigger Enlarge Enlarge Enlarge Enlarge Clock Tj p-p The CLK jitter is measured at peak to peak in the long-term write mode of the digital oscilloscope as shown in the figure. The CLK jitter size varies according to the difference in the relative position with respect to Hsync. Therefore, when the observation point is changed, the CLK jitter at that point is observed. Jitter amount Tj p-p The figure below shows a typical example of the CLK jitter for the CXA3506R. The CLK jitter increases slightly at the rising edge of Hsync (in the case of positive polarity), and then settles down thereafter. However, this is not a problem as the active pixels start after about 20% of the H cycle has passed from the rising edge of Hsync. 0 1/4 · Tsync 2/4 · Tsync Observation points – 64 – 3/4 · Tsync Tsync CXA3506R A/D Converter • Analog input signal The RGB analog input signal and YCbCr analog input signal are converted to digital signals and output. Be sure to adjust the input dynamic range of the ADC in the pre-stage amplifier block by performing contrast and brightness settings for the analog signal input to the ADC. (See the item on the amplifier for details on the setting procedure.) • Sampling clock Although the sampling clock is created by a PLL (internal CLK), it is also possible to externally input a clock to the ADC (external CLK) directly for checking ADC operations. In this case, be sure to make the register settings below in order to input a PECL level clock from the CLKIN (Pin 110) and the XCLKIN (Pin 109). Register: VCO By-pass 0 1 ADC clock External CLK Internal CLK Note, however, that even if an external CLK is input under the above settings, it is impossible to run the ADC at the input clock frequency unless the PLL's VCO frequency divider is set to 1/1. Running the ADC on an external CLK is done in order to check the operations of the ADC. Normally, it should be run on the internal CLK generated by the PLL. • Reference voltage The input dynamic range of the ADC is determined based on the reference voltage from the VRT (Pin 17) and the VRB (Pin 93). Since this reference voltage is created using an internal band gap voltage, there is no need for an external reference voltage circuit. The voltage at the VRT pin is set to a voltage approximately 0.4V lower than the voltage coming from the AVCCAD3 power pin. Also, the VRB pin is set to a voltage approximately 1.0V lower than that at the VRT pin. Capacitors of 1µF or more should be connected between the AVCCAD3 power supply pins for these reference voltage pins (VRT pin and VRB pin). If the value of the capacitor is too low or no capacitor is attached, the reference voltage circuit will cause an oscillation that results in noise or malfunction because the ADC faithfully samples this oscillation. It is impossible to apply an external voltage to a reference voltage pin. Note that it is also impossible to use the voltage generated by a reference voltage pin as an external voltage source. • Operational mode The ADC output data of this IC supports five types of operational mode. Each operational mode is set by using a control register. Register: DATA OUT MODE D3 D2 D1 Straight Data out Mode 0 0 0 DMUX Parallel Data out Mode 0 0 1 DMUX Interleaved Data out Mode 0 1 0 4:2:2 Data out D2 Mode 0 1 1 4:2:2 Data out special Mode 1 1 1 For a description of each operational mode, see the next page. – 65 – CXA3506R • Description of the operational modes (Straight Data out Mode) An RGB analog input signal AC coupled is optimized by using a 3-ch AMP and the signal is input to the ADC. The analog input signal input to the ADC is sampled by using a clock generated by the PLL. The identical signal with the sampling clock for analog input signal is output from the CLK (Pin 99). The sampled analog input signal is output from the port A side of the data output with a 3-clock pipeline delay. Note that output for port B side is turned off at this time and cannot be set to high impedance. The ADC data output is output with a propagation delay (Td_8) ranges from 2.2ns (min.) to 3.8ns (max.) versus the clock output from the CLK pin. The operational frequency in Straight Data out Mode is 100MHz at the sampling clock frequency. Also, note, when operating in Straight Data out Mode, that the output on the port B side (RB0 to RB7, GB0 to GB7, and BB0 to BB7) is turned off and cannot be set to high impedance. All TTL output are set to high impedance only when this IC is put into power save mode. The following type of interface is possible when this IC is operated in Straight Data out Mode. CXA3506R Scaling IC CLK XCLK 1/2CLK 1/2XCLK 99 98 101 Td_8 2.2ns (min.) to 3.8ns (max.) 100 max. min. RA0 to RA7 GA0 to GA7 BA0 to BA7 th (min.) The hold time of the post-stage scaling IC using the interface shown above is, th (min.) = 2.2ns – 66 – CXA3506R (DMUX Parallel Data out Mode) The RGB analog input signal AC coupled is optimized by using a 3-ch AMP and the signal is input to the ADC. The analog signal input to the ADC is sampled by using a clock generated by the PLL. The identical signal with the sampling clock for analog input signal is output from the CLK (Pin 99). At each clock cycle, sampled data is divided into pins in port A side and port B side. The data output on the port A side possesses a 3-clock pipeline delay versus the sampling clock, while the data output on the port B side possesses a 2-clock pipeline delay. The output timing is the same for data output from both ports. Data is maintained for two cycles (2T) of the sampling clock. ADC data is output with a propagation delay (Td_7) ranges from 2.3ns (min.) to 3.2ns (max.) versus the clock output from the 1/2XCLK (Pin 100). An interface of the following type is possible when this IC is run in DMUX Parallel Data out Mode. Td_7 2.3ns (min.) to 3.2ns (max.) T CXA3506R CLK XCLK 1/2CLK 1/2XCLK Scaling IC 99 98 101 100 max. min. RA0 to RA7 GA0 to GA7 BA0 to BA7 ts th RB0 to RB7 GB0 to GB7 BB0 to BB7 ts th With the interface shown above, the post-stage scaling IC acquire data by using the clock signal output from the 1/2CLK pin of the ADC. In case of this interface, the setup time of the post-stage scaling IC is, ts (min.) = T – 3.2ns While the hold time is, th (min.) = T + 2.3ns – 67 – CXA3506R (DMUX Interleaved Data out Mode) The RGB analog input signal AC coupled is optimized by using a 3-ch AMP and the signal is input to the ADC. The analog signal input to the ADC is sampled by using a clock generated by the PLL. The identical signal with the sampling clock for analog input signal is output from the CLK (Pin 99). At each clock cycle, sampled data is divided into pins in port A and port B. The data output on the port A side possesses a 2-clock pipeline delay versus the sampling clock, while the data output on the port B side also possesses a 2-clock pipeline delay. Although the data output from both ports is maintained for two cycles (2T) of the sampling clock, there is one cycle (T) difference between the output timing for port A side and port B side. Data output on port A side possesses a propagation delay (Td_7) ranges from 1.3ns (min.) to 2.2ns (max.) versus the clock output from the 1/2XCLK (Pin 100), while data output on port B side possesses a propagation delay (Td_1/2clk to data) ranges from 2.3ns (min.) to 3.2ns (max.) versus the clock output from the 1/2CLK (Pin 101). An interface of the following type is possible when this IC is run in DMUX Interleaved Data out Mode. T CXA3506R CLK XCLK 1/2CLK 1/2XCLK 99 98 101 100 max. min. ∗Td RA0 to RA7 GA0 to GA7 BA0 to BA7 ts max. min. RB0 to RB7 GB0 to GB7 BB0 to BB7 Scaling IC th ∗Td ts ∗Td th Td_7 2.3ns (min.) to 3.2ns (max.) With the interface shown above, port A data is acquired into the post-stage scaling IC by using the clock signal output from the 1/2CLK pin of the ADC, while port B data is acquired by using the clock signal output from the 1/2XCLK pin. In case of this interface, the setup time of the post-stage scaling IC is, ts (min.) = T – 3.2ns While the hold time is, th (min.) = T + 2.3ns – 68 – CXA3506R (4:2:2 Data out D2 Mode) The YCbCr analog input signal AC coupled is optimized by using a 3-ch AMP and the signal is input to the ADC. The analog signal input to the ADC is sampled by using a clock generated by the PLL. The identical signal with the sampling clock for analog input signal is output from the CLK (Pin 99). In 4:2:2 Data out D2 Mode, the only Y signal is A/D converted just as in Straight Data out Mode and output to the data output ports GA0 to GA7. The Cb and Cr signals are all simultaneously A/D converted at a half sampling rate compared with the Y signal, then multiplexed within the IC, and output to the data output ports BA0 to BA7 in the order U (Cb) and V (Cr). When the SYNC ON Y signal is input, it is necessary to separate out the SYNC signal superimposed on the signal. See the operational description of SYNCSEP for details. Data output of ADC possesses a propagation delay (Td_8) ranges from 2.2ns (min.) to 3.8ns (max.) versus the clock output from the CLK pin. The operating frequency in 4:2:2 Data out D2 Mode is 100MHz as the sampling clock frequency. Although RA0 to RA7, RB0 to RB7, GB0 to GB7, and BB0 to BB7 are all put into output off mode when the IC operates in 4:2:2 Data out D2 Mode, they cannot be set to high impedance. All TTL output is set to high impedance when this IC is put into power save mode. An interface of the following type is possible when this IC is run in 4:2:2 Data out D2 Mode. CXA3506R Scaling IC CLK XCLK 99 98 1/2CLK 101 1/2XCLK Td_8 2.2ns (min.) to 3.8ns (max.) 100 max. min. GA0 to GA7 BA0 to BA7 The hold time of the post-stage scaling IC using the interface shown above is, th (min.) = 2.2ns – 69 – CXA3506R (4:2:2 Data out special Mode) The YCbCr analog input signal AC coupled is optimized by using a 3-ch AMP and the signal is input to the ADC. The analog input signal to the ADC is sampled by using a clock generated by the PLL. The identical signal with the sampling clock for analog input signal is output from the CLK (Pin 99). In 4:2:2 Data out special Mode, the only Y signal is A/D converted just as in Straight Data out Mode and output to the data output ports GA0 to GA7. The Cb and Cr signals are A/D converted at every other sampling at a half sampling rate of the Y signal, then multiplexed within the IC, and output to the data output ports BA0 to BA7 in the order U (Cb) and V (Cr). When the SYNC ON Y signal is input, it is necessary to separate out the SYNC signal superimposed on the signal. See the operational description of SYNCSEP for details. ADC data output possesses a propagation delay (Td_8) ranges from 2.2ns (min.) to 3.8ns (max.) versus the clock output from the CLK pin. The operating frequency in 4:2:2 Data out special Mode is 100MHz as the sampling clock frequency. In addition, although RA0 to RA7, RB0 to RB7, GB0 to GB7, and BB0 to BB7 are all put into output off mode when the IC operates in 4:2:2 Data out Special Mode, they cannot be set to high impedance. All TTL output is set to high impedance when this IC is put into power save mode. An interface of the following type is possible when this IC is run in 4:2:2 Data out D2 Mode. CXA3506R Scaling IC CLK XCLK 1/2CLK 1/2XCLK 99 98 101 Td_8 2.2ns (min.) to 3.8ns (max.) 100 max. min. GA0 to GA7 BA0 to BA7 The hold time of the post-stage scaling IC using the interface shown above is, th (min.) = 2.2ns – 70 – CXA3506R • EVEN/ODD function When a toggle signal created by dividing the Vsync signal in half is input to the EVEN/ODD (Pin 108), the ADC sampling clock is inverted every Vsync signal. This function can be used to configure a single frame screen from two fields by AD converting an RGB analog input signal that requires high speed and high resolution, such as a UXGA 60Hz (162MHz) or more signal, at half the frequency of the original ADC sampling rate. There are no particular control register settings when using the EVEN/ODD function. The sampling clock is inverted based on the polarity of the signal input to the EVEN/ODD pin. Be sure to input signal to the EVEN/ODD pin at TTL level. EVEN/ODD pin L H Operational mode EVEN ODD Example of Using the EVEN/ODD Function 1 EVEN field 3 5 a b c d e f g h i j k l 2 ODD field 4 2 4 6 a b c d e f g h i j k l 3 Analog input signal 1 5 6 Hsync Sampling CLK Vsync Toggle signal (EVEN/ODD pin) 1 2 3 4 a b c d e f g h i j k l EVEN/ODD frame – 71 – 5 6 CXA3506R TTL Output High Level Setting All the TTL output pins can be set to high level by the control register. All the TTL output pins are set simultaneously. The TTL output pins are as follows. RA7 to RA0, RB7 to RB0, GA7 to GA0, GB7 to GB0, BA7 to BA0, BB7 to BB0, SEROUT, SOGOUT, Delay Sync Output, 1/2CLK, 1/2XCLK, CLK and XCLK Register: TTLOUT CLP 00 01 10 11 High level (typ.) 2.2V 2.45V 2.7V 2.95V The TTL output can be input directly to a 3V power supply IC without level conversion. Set high level in accordance with the supply voltage. Power Save 1) Power save for all functions All functions of the chip can be stopped to save power by the XPOWER SAVE (Pin 6). The control register is also set to power save mode at this time. XPOWER SAVE pin L H Operating status Power save Power on The pin input level is TTL level. 2) Power save every block by using the control register The blocks except the registers can also be set to power save mode by the control register. Selects according to using state. 0 1 ADC Power Save Power on Power save AMP Power Save Power on Power save PLL Power Save Power on Power save SYNC SEP Power Save Power on Power save Register – 72 – CXA3506R TTL Output Mode during Power Save Mode All TTL output pins are set to high impedance when the IC is put into power save mode. Since this IC supports power on reset, AMP, ADC, PLL, and SYNCSEP are set to power save mode when power is turned on and all TTL output pins are set to high impedance. However, note that the TTL output pins don't change into high impedance, when control register are used to set each TTL output disable mode separately. Even though there are also modes in which data output ports are set to output off mode based on the ADC operational mode, it cannot be set to high impedance. ADC Data Output Modes XPOWER ADC Straight SAVE Power Save mode mode mode RA7 to 0 Hi-Z Hi-Z RB7 to 0 Hi-Z Hi-Z GA7 to 0 Hi-Z Hi-Z GB7 to 0 Hi-Z Hi-Z BA7 to 0 Hi-Z Hi-Z BB7 to 0 Hi-Z Hi-Z DMUX Parallel mode DMUX YUV 4:2:2 YUV 4:2:2 Interleaved D2 Special mode mode mode ∗ DATA — —∗ DATA —∗ —∗ DATA —∗ DATA DATA —∗ DATA DATA DATA DATA DATA —∗ DATA DATA DATA DATA DATA DATA —∗ DATA —∗ DATA —∗ DATA —∗ Other TTL Output Pin Modes CLK XCLK 1/2CLK XPOWER PLL CLK XCLK 1/2CLK SAVE Power Save Disable Disable Disable mode mode Hi-Z Hi-Z —∗ Signal Signal Hi-Z Hi-Z Signal —∗ Signal Hi-Z Hi-Z Signal Signal —∗ 1/2XCLK Disable DSYNC SOGOUT SEROUT UNLOCK Disable Disable Disable Disable Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal 1/2XCLK Hi-Z Hi-Z Signal Signal Signal Signal —∗ DSYNC/ DIVOUT Hi-Z Hi-Z Signal Signal Signal Signal —∗ Signal SOGOUT Hi-Z Hi-Z Signal Signal Signal Signal Signal —∗ SEROUT Hi-Z Hi-Z Signal Signal Signal Signal Signal Signal Signal —∗ UNLOCK Hi-Z Hi-Z Signal Signal Signal Signal Signal Signal Signal ∗ A dash (–) indicates output off status that cannot be set to high impedance. – 73 – Signal —∗ CXA3506R Supply Current The default value for the current consumption and the control register-based power save current (ICC5PS, ICC3PS), and power save current (ICC5XPS, ICC3XPS) when the XPOWER SAVE function is used, are indicated to each block as follows. (The current consumption values given here are the typical values for when the IC is run at a clock frequency of 80MSPS.) Block Supply pin names DVCCREG AMP (SYNCSEP) AVCCAMP∗ 5V (D) 17.2mA 17.2mA 1.2mA 5V (A) 80.0mA 0.7mA 0.7mA AVCCVCO + AVCCIR 5V (A) 16.0mA 0mA 0mA DVCCPLL + DVCCPLLTTL 5V (D) 41.4mA 2.0mA 1.0mA AVCCADREF 5V (A) 6.8mA 0.4mA 0.4mA DVCCAD + DVCCADTTL 5V (D) 73.2mA 6.0mA 6.0mA 3.3V (A) 180mA 3.0mA 3.0mA Register PLL ADC Current Register PS current XPS current Supply consumption consumption voltage consumption (typ.) AVCCAD3 + DVCCAD3 AVCCAMP∗ = AVCCAMPR + AVCCAMPG + AVCCAMPB – 74 – Td_3 (typ. 7ns) – 75 – ADC Data Output (Straight Mode) 1/2CLK (Pin 101) (N = ODD) 1/2CLK (Pin 101) (N = EVEN) DIVOUT signal (Pin 103) (DSYNC By-pass = 0, DIVOUT Delay = 1) DIVOUT signal (Pin 103) (DSYNC By-pass = 0, DIVOUT Delay = 0) RESET (Internal Signal) DSYNC signal (Pin 103) (DSYNC By-pass = 1) CLK (Pin 99) SYNCIN1 (Pin 111) SYNCIN2 (Pin 112) Analog input N–1 1 N 2 N–5 N–4 Td_1 = 3CLK N–3 Td_2 = 1/32 to 64/32CLK 1CLK N–2 0 PLL Timing Chart (Td1 = 3CLK) 4 N+2 N–2 Td_6 (typ. 1.2ns) Td_6 (typ. 1.2ns) 5 N+3 N–1 N N+1 N+4 6CLK Td_5 = 5CLK Td_5 = 4CLK Td_4 (typ. 1.0ns) N+1 3 N+6 N+2 N+7 N+3 1, 2, 4, 8CLK 1, 2, 4, 8CLK N+5 CXA3506R Td_3 (typ. 7ns) – 76 – ADC Data Output (Straight Mode) 1/2CLK (Pin 101) (N = ODD) 1/2CLK (Pin 101) (N = EVEN) DIVOUT signal (Pin 103) (DSYNC By-pass = 0, DIVOUT Delay = 1) DIVOUT signal (Pin 103) (DSYNC By-pass = 0, DIVOUT Delay = 0) RESET (Internal Signal) DSYNC signal (Pin 103) (DSYNC By-pass = 1) CLK (Pin 99) SYNCIN1 (Pin 111) SYNCIN2 (Pin 112) Analog input N–1 1 N 2 N–5 N–4 N–3 Td_1 = 4CLK Td_2 = 1/32 to 64/32CLK 1CLK N–2 0 PLL Timing Chart (Td1 = 4CLK) N–2 N+1 3 5 N+3 N–1 Td_6 (typ. 1.2ns) N+4 6CLK N N+1 N+2 N+5 Td_5 = 5CLK Td_5 = 4CLK Td_4 (typ. 1.0ns) N+2 Td_6 (typ. 1.2ns) 4 N+7 N+3 1, 2, 4, 8CLK 1, 2, 4, 8CLK N+6 CXA3506R Td_3 (typ. 7ns) – 77 – ADC Data Output (Straight Mode) 1/2CLK (Pin 101) (N = ODD) 1/2CLK (Pin 101) (N = EVEN) DIVOUT signal (Pin 103) (DSYNC By-pass = 0, DIVOUT Delay = 1) DIVOUT signal (Pin 103) (DSYNC By-pass = 0, DIVOUT Delay = 0) RESET (Internal Signal) DSYNC signal (Pin 103) (DSYNC By-pass = 1) CLK (Pin 99) SYNCIN1 (Pin 111) SYNCIN2 (Pin 112) Analog input N–1 1 N 2 N–5 N–4 N–3 N–2 N+1 3 Td_1 = 5CLK Td_2 = 1/32 to 64/32CLK 1CLK N–2 0 PLL Timing Chart (Td1 = 5CLK) 4 N–1 N+2 N Td_6 (typ. 1.2ns) N+5 N+1 N+2 N+3 N+6 Td_5 = 5CLK Td_5 = 4CLK N+4 Td_4 (typ. 1.0ns) N+3 6CLK Td_6 (typ. 1.2ns) 5 1, 2, 4, 8CLK 1, 2, 4, 8CLK N+7 CXA3506R Td_3 (typ. 7ns) – 78 – ADC Data Output (Straight Mode) 1/2CLK (Pin 101) (N = ODD) 1/2CLK (Pin 101) (N = EVEN) DIVOUT signal (Pin 103) (DSYNC By-pass = 0, DIVOUT Delay = 1) DIVOUT signal (Pin 103) (DSYNC By-pass = 0, DIVOUT Delay = 0) RESET (Internal Signal) DSYNC signal (Pin 103) (DSYNC By-pass = 1) CLK (Pin 99) SYNCIN1 (Pin 111) SYNCIN2 (Pin 112) Analog input N–1 1 N 2 N–5 N–4 N+1 3 N–3 N–2 Td_1 = 6CLK Td_2 = 1/32 to 64/32CLK 1CLK N–2 0 PLL Timing Chart (Td1 = 6CLK) 4 N–1 N+2 5 N N+3 N+5 N+1 Td_6 (typ. 1.2ns) Td_6 (typ. 1.2ns) N+6 N+2 N+7 N+3 Td_5 = 5CLK Td_5 = 4CLK Td_4 (typ. 1.0ns) N+4 6CLK 1, 2, 4, 8CLK 1, 2, 4, 8CLK CXA3506R CXA3506R ADC Timing Diagram CLK 2.0V Clock 0.8V XCLK Td_6 min. typ. max. 0.9ns to 1.2ns to 1.6ns TR_CLK TF_CLK min. 0.8ns 1.0ns typ. 1.4ns 1.5ns max. 2.3ns 2.8ns min. 0.8ns 1.0ns typ. 1.4ns 1.5ns max. 2.3ns 2.8ns typ. 1.2ns 1.2ns max. 2.0ns 2.0ns 1/2CLK 2.0V 1/2 clock 0.8V 1/2XCLK TR_CLK TF_CLK 2.0V Data 0.8V Td_8 min. typ. max. 2.2ns to 2.8ns to 3.8ns TR_DATA TF_DATA min. 0.9ns 0.9ns The timing diagram above supposes that one data cycle represents the same amount of time as one clock cycle concerning the three modes as follows: Straight Data out Mode, 4:2:2 Data out D2 Mode, and 4:2:2 Data out special Mode. – 79 – CXA3506R ADC Timing Diagram T CLK 2.0V Clock 0.8V XCLK Td_6 min. typ. max. 0.9ns to 1.2ns to 1.6ns TR_CLK TF_CLK min. 0.8ns 1.0ns typ. 1.4ns 1.5ns max. 2.3ns 2.8ns 1/2CLK 2.0V 1/2 clock 0.8V 1/2XCLK T – 2.2ns min. T + 1.3ns min. TR_CLK TF_CLK min. 0.8ns 1.0ns typ. 1.4ns 1.5ns max. 2.3ns 2.8ns 2.0V Data 0.8V Td_7 min. typ. max. 2.3ns to 2.6ns to 3.2ns TR_DATA TF_DATA min. 0.9ns 0.9ns typ. 1.2ns 1.2ns max. 2.0ns 2.0ns The timing diagram above supposes DMUX Parallel Data out Mode. It is possible for the post-stage scaling IC to acquire data by using a 1/2 clock. The output delay time in this mode is the same as that in DMUX Interleaved Data out Mode. – 80 – CXA3506R ADC Timing Diagram (Straight Data out Mode) Analog input RIN1 (139 pin) RIN2 (141 pin) GIN1 (124 pin) GIN2 (126 pin) BIN1 (133 pin) BIN2 (136 pin) N10 N2 N1 N0 N9 N3 N8 N4 N5 N7 N6 SYNCIN1 (111 pin) SYNCIN2 (112 pin) DSYNC (103 pin) CLK (99 pin) XCLK (98 pin) 1/2CLK (101 pin) 1/2XCLK (100 pin) Data out RA7 to RA0 GA7 to GA0 BA7 to BA0 RB7 to RB0 GB7 to GB0 BB7 to BB0 N2 – 81 – N3 N4 N5 N6 N7 CXA3506R ADC Timing Diagram (DMUX Parallel Data out Mode) Analog input RIN1 (139 pin) RIN2 (141 pin) GIN1 (124 pin) GIN2 (126 pin) BIN1 (133 pin) BIN2 (136 pin) N10 N2 N1 N0 N9 N3 N8 N4 N5 N7 N6 SYNCIN1 (111 pin) SYNCIN2 (112 pin) DSYNC (103 pin) CLK (99 pin) XCLK (98 pin) 1/2CLK (101 pin) 1/2XCLK (100 pin) Data out RA7 to RA0 GA7 to GA0 BA7 to BA0 RB7 to RB0 GB7 to GB0 BB7 to BB0 – 82 – N2 N4 N6 N3 N5 N7 CXA3506R ADC Timing Diagram (DMUX Interleaved Data out Mode) Analog input RIN1 (139 pin) RIN2 (141 pin) GIN1 (124 pin) GIN2 (126 pin) BIN1 (133 pin) BIN2 (136 pin) N10 N2 N1 N0 N9 N3 N8 N4 N5 N7 N6 SYNCIN1 (111 pin) SYNCIN2 (112 pin) DSYNC (103 pin) CLK (99 pin) XCLK (98 pin) 1/2CLK (101 pin) 1/2XCLK (100 pin) Data out RA7 to RA0 GA7 to GA0 BA7 to BA0 RB7 to RB0 GB7 to GB0 BB7 to BB0 N3 N2 – 83 – N5 N4 N7 N6 CXA3506R ADC Timing Diagram (4:2:2 Data out D2 Mode) Analog input RIN1 (139 pin) RIN2 (141 pin) Y10 Y2 Y1 Y9 Y3 Y8 Y4 Y0 Y5 Y7 Y6 GIN1 (124 pin) GIN2 (126 pin) Cb1 Cb9 Cb3 Cb5 BIN1 (133 pin) BIN2 (136 pin) Cr1 Cb7 Cr9 Cr3 Cr5 Cr7 SYNCIN1 (111 pin) SYNCIN2 (112 pin) DSYNC (103 pin) CLK (99 pin) XCLK (98 pin) 1/2CLK (101 pin) 1/2XCLK (100 pin) Data out GA7 to GA0 Y2 BA7 to BA0 Y3 Y4 Y5 Y6 Cb3 (U3) Cr3 (V3) Cb5 (U5) Cr5 (V5) – 84 – Y7 Y8 Cb7 (U7) Cr7 (V7) CXA3506R ADC Timing Diagram (4:2:2 Data out special Mode) Analog input RIN1 (139 pin) RIN2 (141 pin) Y10 Y2 Y9 Y3 Y1 Y8 Y4 Y0 Y5 Y7 Y6 GIN1 (124 pin) GIN2 (126 pin) Cb9 Cb3 Cb1 Cb5 Cb7 Cr10 Cr2 BIN1 (133 pin) BIN2 (136 pin) Cr8 Cr4 Cr6 SYNCIN1 (111 pin) SYNCIN2 (112 pin) DSYNC (103 pin) CLK (99 pin) XCLK (98 pin) 1/2CLK (101 pin) 1/2XCLK (100 pin) Data out GA7 to GA0 BA7 to BA0 Y2 Y3 Y4 Y5 Y6 Cr2 (V3) Cb3 (U3) Cr4 (V4) Cb5 (U5) Cr6 (V6) – 85 – Y7 Y8 Cb7 (U7) Cr8 (V8) CXA3506R ADC Timing Diagram (Straight Data out Mode, EVEN/ODD) EVEN Analog input RIN1 (139 pin) RIN2 (141 pin) GIN1 (124 pin) GIN2 (126 pin) BIN1 (133 pin) BIN2 (136 pin) N18 N10 N2 N0 N13 N8 N5 N20 N17 N12 N9 N4 N1 N19 N11 N3 N21 N16 N15 N7 N14 N6 SYNCIN1 (111 pin) SYNCIN2 (112 pin) DSYNC (103 pin) CLK (99 pin) XCLK (98 pin) 1/2CLK (101 pin) 1/2XCLK (100 pin) Data out RA7 to RA0 GA7 to GA0 BA7 to BA0 RB7 to RB0 GB7 to GB0 BB7 to BB0 N4 N6 N8 N10 N12 N14 ODD Analog input RIN1 (139 pin) RIN2 (141 pin) GIN1 (124 pin) GIN2 (126 pin) BIN1 (133 pin) BIN2 (136 pin) N0 N19 N11 N3 N1 N18 N10 N2 N9 N4 N13 N8 N5 N20 N17 N12 N21 N16 N15 N7 N14 N6 SYNCIN1 (111 pin) SYNCIN2 (112 pin) DSYNC (103 pin) CLK (99 pin) XCLK (98 pin) 1/2CLK (101 pin) 1/2XCLK (100 pin) Data out RA7 to RA0 GA7 to GA0 BA7 to BA0 RB7 to RB0 GB7 to GB0 BB7 to BB0 N5 – 86 – N7 N9 N11 N13 CXA3506R ADC Timing Diagram (DMUX Parallel Data out Mode, EVEN/ODD) EVEN Analog input RIN1 (139 pin) RIN2 (141 pin) GIN1 (124 pin) GIN2 (126 pin) BIN1 (133 pin) BIN2 (136 pin) N18 N10 N2 N3 N13 N8 N5 N0 N20 N17 N12 N9 N4 N1 N19 N11 N21 N16 N15 N7 N14 N6 SYNCIN1 (111 pin) SYNCIN2 (112 pin) DSYNC (103 pin) CLK (99 pin) XCLK (98 pin) 1/2CLK (101 pin) 1/2XCLK (100 pin) Data out RA7 to RA0 GA7 to GA0 BA7 to BA0 RB7 to RB0 GB7 to GB0 BB7 to BB0 N4 N8 N12 N6 N10 N14 ODD Analog input RIN1 (139 pin) RIN2 (141 pin) GIN1 (124 pin) GIN2 (126 pin) BIN1 (133 pin) BIN2 (136 pin) N0 N19 N11 N3 N1 N18 N10 N2 N9 N4 N8 N5 N17 N12 N13 N20 N21 N16 N15 N7 N14 N6 SYNCIN1 (111 pin) SYNCIN2 (112 pin) DSYNC (103 pin) CLK (99 pin) XCLK (98 pin) 1/2CLK (101 pin) 1/2XCLK (100 pin) Data out RA7 to RA0 GA7 to GA0 BA7 to BA0 RB7 to RB0 GB7 to GB0 BB7 to BB0 – 87 – N5 N9 N13 N7 N11 N15 CXA3506R ADC Timing Diagram (DMUX Interleaved Data out Mode, EVEN/ODD) EVEN Analog input RIN1 (139 pin) RIN2 (141 pin) GIN1 (124 pin) GIN2 (126 pin) BIN1 (133 pin) BIN2 (136 pin) N18 N10 N2 N3 N13 N8 N5 N0 N20 N17 N12 N9 N4 N1 N19 N11 N21 N16 N15 N7 N14 N6 SYNCIN1 (111 pin) SYNCIN2 (112 pin) DSYNC (103 pin) CLK (99 pin) XCLK (98 pin) 1/2CLK (101 pin) 1/2XCLK (100 pin) Data out RA7 to RA0 GA7 to GA0 BA7 to BA0 RB7 to RB0 GB7 to GB0 BB7 to BB0 N6 N10 N4 N14 N8 N12 ODD Analog input RIN1 (139 pin) RIN2 (141 pin) GIN1 (124 pin) GIN2 (126 pin) BIN1 (133 pin) BIN2 (136 pin) N0 N19 N11 N3 N1 N18 N10 N2 N13 N8 N5 N20 N17 N12 N9 N4 N21 N16 N15 N7 N14 N6 SYNCIN1 (111 pin) SYNCIN2 (112 pin) DSYNC (103 pin) CLK (99 pin) XCLK (98 pin) 1/2CLK (101 pin) 1/2XCLK (100 pin) Data out RA7 to RA0 GA7 to GA0 BA7 to BA0 RB7 to RB0 GB7 to GB0 BB7 to BB0 N7 N5 – 88 – N11 N9 N15 N13 CXA3506R Main Contrast Control Characteristics Sub Contrast Control Characteristics 2.5 30 20 Gain adjustment ratio [%] Gain [dB] 2.0 1.5 1.0 Sub contrast = 128 R, G, B OUT 0.5 10 0 –10 Main contrast = 128 R, G, B OUT –20 0 –30 0 50 100 200 150 250 0 50 Main Contrast register 200 150 250 Sub Contrast register Brightness Level Control Characteristics CbCr Clamp Level Control Characteristics 80 150 60 145 AD output conversion level (LSB) AD output conversion level (LSB) 100 40 20 0 –20 –40 –60 140 135 130 125 120 115 110 105 –80 100 50 0 100 150 200 250 0 Brightness register 10 20 30 40 50 60 CbCr offset register SYNC SEP VTH Control Characteristics SYNC SEP VHYS Control Characteristics 250 80 70 200 150 VHYS [mV] VTH [mV] 60 100 50 40 30 20 50 10 0 0 0 2 4 6 8 10 12 14 0 1 2 VHYS register VTH register – 89 – 3 CXA3506R Frequency Response Gain Temperature Characteristics 10 9 8 7 Gain fluctuation ratio [%] 6 Gain [dB] 5 3 1 –1 Main contrast = 128 Sub contrast = 128 R, G, B OUT 2 0 –2 –4 –6 –3 –5 0.1 4 Main contrast = 128 Sub contrast = 128 R, G, B OUT –8 1 10 100 –10 –10 300 0 1.5 0.5 1.0 0.5 0 –0.5 Main contrast = 128 Sub contrast = 128 R, G, B OUT 40 50 60 70 0.4 0.3 0.2 0.1 0 –0.1 Brightness = 128 –1.5 –0.2 5 –0.3 –10 5.25 0 10 20 30 40 50 60 70 Supply voltage [V] Ta – Ambient temperature [°C] Brightness Supply Voltage Characteristics CbCr Clamp Level Temperature Characteristics 1.5 0.6 1.0 0.4 AD output level fluctuation (LSB) AD output level fluctuation (LSB) 30 Brightness Level Temperature Characteristics 0.6 AD output fluctuation (LSB) Gain fluctuation ratio [%] Gain Supply Voltage Characteristics 2.0 –2.0 4.75 20 Ta – Ambient temperature [°C] Frequency [MHz] –1.0 10 0.5 0 –0.5 –1.0 0.2 0 –0.2 CbCr offset register = 32 –0.4 Brightness = 128 –1.5 4.75 5 –0.6 –10 5.25 Supply voltage [V] 0 10 20 30 40 50 60 Ta – Ambient temperature [°C] – 90 – 70 CXA3506R KVCO Characteristics CbCr Clamp Level Supply Voltage Characteristics 250 0.4 DIV = 1/1 DIV = 1/2 DIV = 1/4 DIV = 1/8 200 Output frequency [MHz] AD output level fluctuation (LSB) 0.6 0.2 0 –0.2 CbCr offset register = 32 100 50 –0.4 –0.6 4.75 150 5 0 1.5 5.25 2.0 2.5 3.0 3.5 Fine Delay vs. Control 80 72 Fine delay [1/32CLK] 64 56 48 40 32 24 16 8 0 0 8 16 24 32 40 48 56 64 Fine delay register control [1/32CLK] Jitter Peak-Peak vs. Output Frequency 2.0 1.8 Jitter peak-peak [ns] 1.6 1.4 1.2 1.0 0.8 0.6 0.4 NTSC, VGA, SVGA, XGA, 0.2 0 0 20 40 60 4.0 VCO control voltage [V] Supply voltage [V] 80 100 120 Output frequency [MHz] – 91 – DIV = 1/8, DIV = 1/4, DIV = 1/4, 1/2, DIV = 1/2, CP = 010, 100 CP = 010, 011 CP = 010, 100, 101 CP = 011, 100 4.5 5.0 CXA3506R Current Consumption vs. Temperature Characteristics Current Consumption vs. Supply Voltage Fluctuation 200 Current consumption [mA] Current consumption [mA] 200 180 ICC5 ICC3 CLK = DC 160 –10 0 25 50 180 ICC5 ICC3 CLK = DC 160 3.0 75 Ta – Ambient temperature [°C] 4.75 3.3 3.6 VCC3 5.0 5.25 VCC5 Supply voltage [V] Current Consumption vs. Frequency Response 260 Operational mode: DMUX parallel Data out Load capacitance: CL = 10pF Current consumption [mA] 240 220 200 ICC5 ICC3 180 160 20 40 60 80 100 120 FCLK – Clock frequency [MHz] – 92 – R2 R1 B2 B1 0.1µ 0.1µ 0.1µ 0.1µ 0.1µ 0.1µ 75 75 75 75 DACTESTOUT G/YOUT AGNDAMPR R/CrIN2 AVCCAMPR R/CrIN1 DPGND AGNDAMPB B/CbIN2 SOGIN2 AVCCAMPB B/CbIN1 SOGIN1 DPGND R/CrCLP 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 123 124 59 60 121 122 61 65 116 62 66 115 120 67 114 119 68 113 63 69 112 118 70 64 71 111 117 72 110 B/CbOUT 0.1µ EVEN/ODD 109 R/CrOUT B/CbCLP XTLOAD ADDRESS 0.1µ SOGOUT NC G/YCLP UNLOCK NC 0.1µ DSYNC/DIVOUT XPOWER SAVE AGNDAMPG DPGND DGNDREG 75 1/2XCLK SDA G/YIN2 1/2CLK DVCCREG 4.7k 0.1µ CLK SCL AVCCAMPG XCLK XSENABLE 4.7k 75 DGNDPLLTTL SEROUT G2 DVCCPLLTTL 3WIRE/I2C G/YIN1 AGNDADREF 1µ DPGND 0.1µ VRB AVCCAD3 AGNDIR AVCCAD3 AVCCADREF G1 DVCCAD3 VRT 1µ DPGND DVCCAD DVCCAD3 IREF DVCCADTTL DVCCADTTL 3k GB7 RA0 100p DGNDADTTL DGNDADTTL AVCCIR GB6 RA1 RC2 DGNDAD3 DGNDAD3 C2 330p GB5 RA2 RC1 GB4 RA3 R1 3.3k C1 0.33µ GB3 RA4 AGNDVCO GB2 RA5 AVCCVCO GB1 RA6 100p AGNDAD3 AGNDAD3 DGNDPLL DGNDAD3 DGNDAD3 DVCCPLL GB0 RA7 CLPIN DGNDADTTL DVCCADTTL SYNCIN2 GA7 RB0 SYNCIN1 DVCCADTTL DGNDADTTL CLKIN GA5 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 GA6 RB1 – 93 – RB2 XCLKIN HOLD Application Circuit (I2C (High) mode) RB3 RB4 RB5 RB6 RB7 DVCCADTTL DGNDAD3 DGNDADTTL BA0 BA1 BA2 BA3 BA4 DGNDAD3 BA5 BA6 BA7 DVCCADTTL DGNDADTTL BB0 BB1 BB2 GNDAD3 BB3 BB4 BB5 BB6 BB7 DVCCADTTL DGNDAD3 DGNDADTTL GA0 GA1 GA2 GA3 GA4 AVCC5V DVCC5V 3.3V DGND AGND Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. This is an application circuit which controls this IC with I2C (High) mode and supports RGB2 channel input. ADC operational mode supports DMUX Parallel mode or DMUX Interleaved mode. (I2C bus slave address is 10011000.) CXA3506R Cr Cb 0.1µ 0.1µ 75 75 820 TP-G 144 143 142 141 140 139 138 137 136 135 134 133 132 TP-B DACTESTOUT G/YOUT AGNDAMPR R/CrIN2 AVCCAMPR R/CrIN1 DPGND AGNDAMPB B/CbIN2 SOGIN2 AVCCAMPB B/CbIN1 SOGIN1 131 130 129 128 127 126 125 820 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 TP-R 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 123 124 59 60 122 61 121 65 116 120 66 115 62 67 114 119 68 113 63 69 112 118 70 111 64 71 110 117 72 109 B/CbOUT DPGND XTLOAD ADDRESS 0.1µ SOGOUT NC R/CrCLP HOLD R/CrOUT 820 0.1µ UNLOCK NC B/CbCLP DSYNC/DIVOUT XPOWER SAVE 0.1µ DPGND DGNDREG G/YCLP 1/2CLK DVCCREG 4.7k 0.1µ CLK SCL AGNDAMPG 1/2XCLK SDA G/YIN2 XCLK XSENABLE 4.7k AVCCAMPG DGNDPLLTTL SEROUT 75 DVCCPLLTTL 3WIRE/I2C G/YIN1 AGNDADREF 1µ DPGND 0.1µ VRB AVCCAD3 AGNDIR AVCCAD3 AVCCADREF Y DVCCAD DVCCAD3 DPGND DVCCAD3 VRT 1µ IREF DVCCADTTL DVCCADTTL 3k DGNDADTTL DGNDADTTL 100p GB7 RA0 AVCCIR GB6 RA1 RC2 DGNDAD3 DGNDAD3 C2 330p GB5 RA2 RC1 GB4 RA3 R1 3.3k C1 0.33µ GB3 RA4 AGNDVCO GB2 RA5 AVCCVCO GB1 RA6 100p AGNDAD3 AGNDAD3 DGNDPLL DGNDAD3 DGNDAD3 DVCCPLL GB0 RA7 CLPIN DGNDADTTL DVCCADTTL SYNCIN2 DVCCADTTL DGNDADTTL SYNCIN1 GA7 RB0 CLKIN GA6 RB1 – 94 – RB2 XCLKIN GA5 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 EVEN/ODD Application Circuit (3-wire bus mode) RB3 RB4 RB5 RB6 RB7 DVCCADTTL DGNDAD3 DGNDADTTL BA0 BA1 BA2 BA3 BA4 DGNDAD3 BA5 BA6 BA7 DVCCADTTL DGNDADTTL BB0 BB1 BB2 GNDAD3 BB3 BB4 BB5 BB6 BB7 DVCCADTTL DGNDAD3 DGNDADTTL GA0 GA1 GA2 GA3 GA4 AVCC5V DVCC5V 3.3V DGND AGND Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. This is an application circuit which controls this IC with 3-wire bus mode and operates ADC with 4:2:2 Data out D2 mode with respect to YcbCr analog input signal. CXA3506R CXA3506R Notes on Operation • On the PC board, prepare a solid ground pattern having as large an area as possible, and placing the IC in the center, divide this area into an analog region and digital region. • The loop filter area of the PLL block plays an important role in terms of performance. It is therefore located as close as possible to the IC pins and the periphery is guarded with AGND. Also, be sure to use capacitors and resistors for the loop filter that should be temperature compensated and do not change the values. • Be sure to use a metal film resistor for the resistor connected to IREF (Pin 121). • The wiring for SYNCIN1 (Pin 111) and SYNCIN2 (Pin 112) should be as short as possible and each needs to be shielded by ground. • Use a 0.1µF ceramic chip capacitor for the bypass capacitor attached between the power supply and ground. The capacitor should be attached to the pin as close as possible. • Use a 1µF ceramic chip capacitor for the capacitor attached to the VRT (Pin 17) and the VRB (Pin 93) and connect to the AVCCAD3 (Pin 16 and Pin 94) as close as possible. • Equalize and shorten the lines of RGB analog input signals, if possible. Each line needs to be shielded by ground. (This is the same for the R/CrCLP, G/YCLP, and B/CbCLP pins.) • A 0.1µF capacitor is recommended for attachment to the RGB analog input pins. The less the capacitance becomes, the more the sag by leak current becomes. The more the capacitance becomes, the more start up time takes in case of putting power source into the IC. (This is the same for the R/CrCLP, G/YCLP, and B/CbCLP pins.) • Design boards so that the wiring for the R/CrIN, G/YIN, and B/CbIN and R/CrOUT, G/YOUT, B/CbOUT pins is as separated as possible. • Use a pattern width that takes characteristic impedance into account for signal wires terminated at 75Ω. • There are no particular restrictions on the power-on sequence. • Although there are AVCCAD3 and DVCCAD3 as 3.3V power supply, use the same 3.3V analog power supply to each on the board. • AGNDAD3 and DGNDAD3 are the ground for AVCCAD3 and DVCCAD3, respectively. Use the same ground for AGNDAD3 and DGNDAD3. Although AGND is the ground recommended for AGNDAD3 and DGNDAD3, there are no problems in terms of operation even if connected to DGND. (The special evaluation board in the Application Circuit is connected to DGND.) • Although 5V power supply is divided into both analog and digital power supply lines, be sure to wire boards so that no potential difference arises between these power supplies. • Load capacitance of the data output wires causes the change for the worse of slew rate and noise. Be sure to use short layouts with the finest wires possible. • Put this IC into power save mode when making a connection between data output and another IC. (High impedance cannot be set when pins are disabled separately.) – 95 – CXA3506R CXA3506R Evaluation Board Overview The CXA3506R Evaluation Board is a special board designed for the easy evaluation of the CXA3506R developed for the LCD projector and monitor so that performance can be maximized. The DSUB 15-pin connector is used as the input connector that allows the direct input of a video signal from a PC. The input video signal is A/D converted by the CXA3506R and a pin for monitoring is designed onto the board so that output data can be checked directly. The 10-bit high speed D/A converters are built onto the board so that the performance of the IC can be easily checked. Picture quality can be easily evaluated by using a CRT monitor since the D/A-converted video signal is output from the DSUB 15-pin connector for output in addition to the DSYNC output of the CXA3506R. Features • Single +5V power supply (with built-in 3.3V regulator) • Allows two-line video signal input • Data output port is also used as output data monitoring pin • CXA3506R output is D/A converted and is easily monitored by a CRT • Supports 2 types of control registers (3-wire and I2C) Operating Conditions • Supply voltage: +5V (typ.) • Current consumption: 830mA (typ.) • Input signal: Separated sync video signal – 96 – – 97 – Video signal output pins Video signal input pins CON3 Video OUT CON2 Video In2 CON1 Video In1 Video signal output Hsync output Vsync output Vsync signal 2 Video signal 2 Hsync signal 2 Video signal 1 Hsync signal 1 Vsync signal 1 CXA3506R EVB Block Diagram 0.1µF 0.1µF R, G, B analog output signal 10µF Vsync signal select R, G, B analog input signal R, G, B analog input signal SW2 CXA3506R SOGOUT CON4 I2C Control register pins CON5 3Wire I/O logic SW3 0V Power save 3WIRE/I2C SW1 CLPIN CXA2016P Clamp pulse generation 5V Power supply pins DAC ×3 CXA3197R R, G, B digital output data Control signal Output data monitoring pins data output ports CXA3506R CXA3506R Using the CXA3506R Evaluation Board The CXA3506R Evaluation Board can be used to easily evaluate just by connecting a power supply, video signals, and control register signals. The procedure is described below. 1. Connect the power supply to the power connection pin. (GND/+5V) Do not apply power supply in this state. 2. Check the direction of SW1. SW1 is the power save control switch. The CXA3506R is put into power save mode when SW1 is set to the rear position (↑). Set SW1 to the forward (↓) position when using the CXA3506R. SW1 is connected to the XPOWER SAVE pin. 3. Connect the special control register signal cable. Connect the cable to CON4 when using I2C control. Set SW2 and SW3 to the forward (↓) position. While, connect the cable to CON5 when using 3-wire control. Set SW2 and SW3 to the rear (↑) position. In addition, check that the short pin (I2C) is in the "00" position in case of using I2C control. 4. Input the RGB analog signals from the CON1 pin (Video In 1). XGA60 is recommended as the initial signal because the control program default value is set for the XGA60. XGA60: Vsync 60Hz Hsync: Video signal for 48kHz N = 1344 5. The RGB analog signal for simple picture quality evaluations is output from the CON3 pin (Video Out). Be sure to connect the CON3 pin to a CRT monitor that can process a signal of XGA60 or more. 6. Turn on the power. Check a current to be about 360mA flows through the 5V power supply. If there is much more current than this, immediately turn off the power and check that there are no misconnections. 7. Run the control program. Click on "re-load" at the bottom right of the control program screen, and check a current to be about 830mA flows through the 5V power supply. If everything works normally, an processed image for picture quality evaluation appears on the CRT monitor. Reconfirm the above items from the beginning if the processed image does not appear. – 98 – CXA3506R 3-wire Control Program Installation and Startup Method [Operating Environment] Windows95 or Windows98 [Program Installation and Startup] The installation program is configured from the following four files and stored in two floppy disks. setup.exe, A3506_1.cab, A3506_2.cab, and Setup.lst 1. Copy the four files from the floppy disk onto the PC. 2. Click setup.exe. The installer will start. Follow all on-screen instructions. 3. Once installation complete, a folder titled "Project1" will be created in the Program files folder. 4. The following control window will open when the A3506.exe file starts. Use this window to make board settings in response to the printer port address of the PC. Be sure to set the address for the PC from the pull-down menu port at the top-left of the control screen. There are two types of addresses: 378 and 3BC. – 99 – CXA3506R I2C Control Program Installation and Startup Method [Operating Environment] Windows95 or Windows98 [Program Installation and Startup] The installation program consists of the following four files and is stored in two floppy disks. setup.exe, A3506_1.cab, A3506_2.cab, Setup.lst 1. Copy these four files from the floppy disk onto the PC. 2. Click setup.exe. The installer will start. Follow all on-screen instructions. 3. Once installation complete, a folder titled "Project1" will be created in the Program files folder. 4. The following control window will open when the A3506.exe file starts. Use this window to make board settings in response to the printer port address of the PC. Be sure to set the address for the PC from the pull-down menu port at the top-left of the control screen. There are two types of addresses: 378 and 3BC. – 100 – CXA3506R Notes on Using CXA3506R EVB 1. RGB analog signals input from CON1 or CON2 are A/D converted. The digital signals are D/A converted. In addition, the analog signals are output in AC coupling. Therefore, the output are the RGB analog signals output from CON3. In this reason, when the RGB analog signals output from CON3 undergo picture quality evaluation by using a CRT monitor, note that on-screen evaluation cannot be confirmed about the functions of SUB BRIGHTNESS and Cb/Cr OFFSET. This is due to the fact that the DC component disappears because the RGB analog signals are output in AC coupled after output by the D/A converter, even if the DC offset is changed. 2. The current consumption for this board immediately after turning on the board's power is approximately 360mA. Board current is 830mA when the CXA3506R control register is started after this. When turning on power to the board, be sure to check the board current and make sure that connections are correct. 3. Although this board is equipped with a –5V power supply pin, it can operate by using a single 0/+5V power supply. Be sure to leave the –5V power supply pin open. Notes Regarding the Control Program 1. When the program is accurately installed on the PC, be sure to re-check items 2 and 3 of the operational procedures above when the IC does not move. 2. If the CXA3506R does not move even after item 1 above is checked, it is possible that the control signals of the control register are not output from the PC printer board. In this case, be sure to re-check the board settings listed for item 4 under "Program Installation and Startup". – 101 – CXA3506R CXA3506R Evaluation Board Parts List Parts No. Product name Manufacturer IC1 CXA3506R SONY IC2 CXA2016S SONY IC3, 4, 5 CXA3197R SONY IC6 SN74LS04N Texas Instruments IC7 SN74LS32N Texas Instruments IC8 SN74LS08N Texas Instruments IC9 LT1086CM-3.3 Linear Technology CON1, 2, 3 D02-N15SAG-13L9 SANSHIN ELECTRONICS CON4 53053-0510 Molex CON5 53053-0610 Molex SW1 G-12AP NIHON KAIHEIKI IND. SW2 G-13AP NIHON KAIHEIKI IND. SW3 G-22AP NIHON KAIHEIKI IND. L1, 2 ZBF503D-00 TDK R1, 2 620 Chip resistor C1 to 4 10µ Tantalum capacitor R3, 4 200 Chip resistor C5 2.2µ Tantalum capacitor R5 3.3k Chip metal film resistor C6, 7 1µ Tantalum capacitor R6 3k Lead metal film resistor C8 to 10 100µ Electrolytic capacitor R7 to 12 75 Chip resistor C11, 12 0.1µ Chip capacitor R13 to 15 820 Chip resistor C13, 14 100p Chip capacitor R17, 18 75 Chip resistor C15 0.1µ Chip capacitor R19 270 Chip resistor C16 330p Chip capacitor R20, 21 12k Lead metal film resistor C17 0.33µ Chip capacitor R22 33k Chip resistor C18 to 34 0.1µ Chip capacitor R23 2.2k Chip resistor C35 1µ Chip capacitor R24, 25, 27 1k Chip resistor C36 to 44 0.1µ Chip capacitor R26, 29, 32 75 Chip resistor C45 1µ Chip capacitor R28, 31, 34 620 Chip resistor C47 0.1µ Chip capacitor R30, 33 1k Chip resistor C48, 49 0.22µ Chip capacitor R35 to 37 24k Chip resistor C50 0.1µ Chip capacitor R38, 39 24k Chip resistor C51 0.22µ Chip capacitor R40 to 44 10k Chip resistor C52 0.1µ Chip capacitor R45 820 Chip resistor C53 0.01µ Chip capacitor R47, 48 2k Chip resistor C54 3300p Chip capacitor R49, 50 3k Chip resistor C55 to 70 0.1µ Chip capacitor C71 to 75 0.1µ Chip capacitor – 102 – VSYNC2 VSYNC1 R35 24k DGND 15 10 5 11 6 1 10 5 Video IN2 15 11 6 1 CON2 R36 24k DVcc R37 24k R12 75 R10 75 R11 75 R9 75 AGND R8 75 R7 75 DGND R38 24k DVcc R39 24k C11 0.1µ AVcc C31 0.1µ C30 0.1µ C27 0.1µ C28 0.1µ C25 0.1µ C26 0.1µ AGND R6 3k CLAMP R13 820 C32 0.1µ C29 0.1µ C20 0.1µ GOUT AVcc AGND AVcc AGND AVcc C22 0.1µ AGND C23 0.1µ C24 0.1µ C21 0.1µ C18 0.1µ C12 0.1µ C13 100p C16 330p C14 100p AVcc C17 0.33µ C15 0.1µ C19 0.1µ AGND R5 3.3k DVcc DGND AVcc AGND XCLKIN CLKIN SYNCIN1 SYNCIN2 CLPIN DVccPLL DGNDPLL AVccVCO AGNDVCO RC1 RC2 AVccIR IREF DPGND AGNDIR G/YIN1 AVccAMPG G/YIN2 AGNDAMPG G/YCLP B/CbCLP R/CrCLP DPGND SOGIN1 B/CbIN1 AVvAMPB SOGIN2 B/CbIN2 AGNDAMPB DPGND R/CrIN1 AVccAMPR R/CrIN2 AGNDAMPR G/YOUT DAC TEST OUT ROUT BOUT 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 R14 820 R15 820 C33 0.1µ Video IN1 Slave address 10010 00 1/2CLK 1/2XCLK CLK XCLK DGND DVcc SDA SCL SENABLE SEROUT AVcc AGND C47 0.1µ C34 0.1µ IC1 CXA3506R AGND AVcc 3V AGND AGND SOGOUT EVEN/ODD XTLOAD DGND DSYNC UNLOCK AGND 3V C45 1µ C35 1µ C36 0.1µ CON1 10010 10 10010 11 10010 01 S1 S2 S3 S4 C37 0.1µ BA0 BA1 R4 200 SW1 XPOWER SAVE RB5 RB4 RB3 RB2 RB1 BA2 BA3 BA4 BA5 BA6 R3 200 SW2 3-Wire/I2C RB0 BA7 R2 620 GA4 GA3 GA2 GA1 GA0 DGNDADTTL DGNDAD3 DVccADTTL BB7 BB6 BB5 BB4 BB3 GNDAD3 BB2 BB1 BB0 DGNDADTTL DVccADTTL BA7 BA6 BA5 DGNDAD3 BA4 BA3 BA2 BA1 BA0 DGNDADTTL DGNDAD3 DVccADTTL RB7 RB6 RB5 RB4 RB3 C38 0.1µ R1 620 AGND RB7 RB6 C44 0.1µ C43 0.1µ RA7 RA6 RA5 C42 0.1µ 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 EVEN/ODD XTLOAD HOLD SOGOUT UNLOCK DSYNC/DIVOUT DPGND 1/2CLK 1/2XCLK CLK XCLK DGNDPLLTTL DVccPLLTTL AGNDADREF AVccAD3 VRB DVccAD3 DVccAD DVccADTTL DGNDADTTL GB7 GB6 DGNDAD3 GB5 GB4 GB3 GB2 GB1 AGNDAD3 DGNDAD3 GB0 DGNDADTTL DVccADTTL GA7 GA6 GA5 B/CbOUT ADDRESS R/CrOUT NC NC XPOWER SAVE DGNDREG DVccREG SDA SCL XSENABLE SEROUT 3WIRE/I2C DPGND AVccADREF AVccAD3 VRT DVccAD3 DVccADTTL DGNDADTTL RA0 RA1 DGNDAD3 RA2 RA3 RA4 RA5 RA6 AGNDAD3 DGNDAD3 RA7 DVccADTTL DGNDADTTL RB0 RB1 RB2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 – 103 – BB0 BB1 BB2 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 C39 0.1µ C40 0.1µ C41 0.1µ Register BB7 BB6 BB5 BB4 BB3 GA4 GA3 GA2 GA1 GA0 GA7 GA6 GA5 GB2 GB1 GB0 GB7 GB6 GB5 GB4 GB3 RA4 RA3 RA2 RA1 RA0 DVcc Video Signal RGB Data CXA3506R DGND VSYNC1 S5 Video IN1 Vsync RGB Data VSYNC2 S6 – 104 – Video Signal DSYNC Video IN2 Vsync RB0 RB1 Video OUT 15 10 5 11 6 1 CON3 AGND DGND RB2 RB3 RB4 RB5 RB6 RB7 CXA3197R IC3 C1 C2 C3 DVcc2 AVccO DB3 DB2 DB1 DB0 DIV2IN DIV2OUT CLK/T CLKP/E CLKN/E RESET/T RESETP/E RESETN/E DGND2 RA0 RA1 RA2 RA3 12 11 10 9 8 7 6 5 4 3 2 1 DA6 DA7 DA8 DA9 DGND1 NC DVcc1 PS INV RPOLARITY VOCLP AGND2 DB4 DB5 DB6 DB7 DB8 DB9 DA0 DA1 DA2 DA3 DA4 DA5 AOUTN AOUTP AGND2 VREF VSET 13 14 15 16 1/2CLK 17 18 CLK/T 19 CLKP/E 20 CLKN/E 21 22 23 24 AVcc2 C56 0.1µ C8 100µ C57 0.1µ 25 26 27 28 29 30 R26 75 C68 0.1µ 31 32 33 34 R27 1K R28 620 35 36 C58 0.1µ 48 47 46 45 44 43 42 41 40 39 38 37 RA4 RA5 RA6 RA7 DVcc C59 0.1µ DGND GB0 GB1 DGND 13 14 15 16 1/2CLK 17 18 CLK/T 19 CLKP/E 20 CLKN/E 21 22 23 24 GB2 GB3 GB4 GB5 GB6 GB7 DB3 DB2 DB1 DB0 DIV2IN DIV2OUT CLK/T CLKP/E CLKN/E RESET/T RESETP/E RESETN/E CXA3197R IC4 DA6 DA7 DA8 DA9 DGND1 NC DVcc1 PS INV RPOLARITY VOCLP AGND2 C60 0.1µ C9 100µ C61 0.1µ 48 47 46 45 44 43 42 41 40 39 38 37 C75 R49 0.1µ 3k XCLK C74 0.1µ R47 2k CLK DGND DVcc C63 0.1µ DGND R22 R20 R21 C50 C51 R19 DGND 13 14 15 16 1/2CLK 17 18 CLK/T 19 CLKP/E 20 CLKN/E 21 22 23 24 1 2 3 4 0.1µ 5 0.22µ 6 270 7 8 12k 9 12k 10 11 33k 0.22µ 0.22µ C64 0.1µ DB3 DB2 DB1 DB0 DIV2IN DIV2OUT CLK/T CLKP/E CLKN/E RESET/T RESETP/E RESETN/E AGND R18 C7 75 1µ CLKN/E R50 AGND 3k R48 2k CLKP/E DVcc GA4 GA5 GA6 GA7 C6 1µ BB0 BB1 C48 C49 CXA2016S IC5 CXA3197R DA6 DA7 DA8 DA9 DGND1 NC DVcc1 PS INV RPOLARITY VOCLP AGND2 C10 100µ C65 0.1µ 48 47 46 45 44 43 42 41 40 39 38 37 AGND 22 VSIN AVcc 21 PVC VD 20 EVC Vssin 19 CSIN Vssout 18 R23 PHC HD 17 2.2k EHC PV 16 Videoin PH 15 C52 0.1µ HDsel clpsel 14 ISC xclpout 13 ISJ clpout 12 C53 0.01µ AGND VssREF IC2 BB2 BB3 BB4 BB5 BB6 BB7 SOGOUT GA0 GA1 GA2 GA3 12 11 10 9 8 7 6 5 4 3 2 1 DB4 DB5 DB6 DB7 DB8 DB9 DA0 DA1 DA2 DA3 DA4 DA5 DGND2 C1 C2 C3 DVcc2 AVccO AOUTN AOUTP AGND2 VREF VSET AVcc2 25 26 27 28 29 30 R29 75 C69 0.1µ 31 32 33 34 R30 1K R31 620 35 36 C62 0.1µ BA0 BA1 BA2 BA3 12 11 10 9 8 7 6 5 4 3 2 1 DB4 DB5 DB6 DB7 DB8 DB9 DA0 DA1 DA2 DA3 DA4 DA5 25 DGND2 26 C1 27 C2 28 C3 29 DVcc2 30 AVccO R32 75 C70 0.1µ 31 AOUTN 32 AOUTP 33 AGND2 34 VREF R33 1K R34 620 35 VSET 36 C66 0.1µ AVcc2 C54 3300p S10 S9 S8 S7 C55 0.1µ DGND DVcc C67 0.1µ BA4 BA5 BA6 BA7 AVcc 1k AVEE AGND AVcc R25 1k R24 CLAMP R17 C5 75 2.2µ BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0 BB7 BB6 BB5 BB4 BB3 BB2 BB1 BB0 GA7 GA6 GA5 GA4 GA3 GA2 GA1 GA0 GB7 GB6 GB5 GB4 GB3 GB2 GB1 GB0 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 DSYNC 1/2CLK 1/2XCLK CLK XCLK BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0 BB7 BB6 BB5 BB4 BB3 BB2 BB1 BB0 GA7 GA6 GA5 GA4 GA3 GA2 GA1 GA0 GB7 GB6 GB5 GB4 GB3 GB2 GB1 GB0 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 DSYNC 1/2CLK 1/2XCLK CLK XCLK CXA3506R Register SEROUT SENABLE SCL SDA – 105 – SCL SDA SW6 3-Wire/I2C DGND AVEE AGND 3V R40 10k R42 10k DGND R41 10k C1 10µ 1 2 3 GND Vout Vin 5 4 3 C71 0.1µ 2 1 DVcc 74AS04 IC6D C73 0.1µ 74AS04 9 5 74AS04 3 74AS04 L2 IC6C 8 6 IC6B 4 IC6A L1 C3 10µ DVcc C72 0.1µ 6 74AS08 IC8B 74AS08 2 IC8A 1 C4 10µ C2 10µ AVcc R43 10k IC9 LT1086CM-3.3 74AS04 74AS04 74AS32 DGND DGND R45 820 SDA SCL SENABLE SEROUT IC6F 13 12 IC6E 11 10 R44 10k 2 IC7A 3 1 V3 –5V V2 0V V1 +5V 1 5 1 6 CON5 3-WIRE CON4 I 2C DVcc CXA3506R CXA3506R – 106 – CXA3506R – 107 – CXA3506R – 108 – CXA3506R – 109 – CXA3506R Package Outline Unit: mm 144PIN LQFP (PLASTIC) 22.0 ± 0.2 1.7 MAX 20.0 ± 0.1 1.4 ± 0.1 73 108 109 72 B A 37 144 1 36 0.5 b 0.08 M 0.1 S S S 0˚ to 10˚ DETAIL A 0.5 ± 0.15 (21.0) b = 0.20 ± 0.03 0.125 ± 0.04 0.1 ± 0.05 DETAIL B PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE LQFP-144P-L01 LEAD TREATMENT PALLADIUM PLATING EIAJ CODE LQFP144-P-2020 LEAD MATERIAL COPPER ALLOY PACKAGE MASS 1.3 g JEDEC CODE – 110 – Sony Corporation