CXA2066S Preamplifier for High Resolution Computer Display Description The CXA2066S is a bipolar IC developed for high resolution computer displays. 30 pin SDIP (Plastic) Features • Built-in wide band amplifier: 140MHz @ –3dB (Typ.) • Input dynamic range: 1.0Vp-p (Typ.) • High gain preamplifier (17dB) • R, G, and B incorporated in a single package • I2C bus control Contrast control Subcontrast control Brightness control OSD contrast control Cutoff control 4-channel DAC output 2 blanking level modes (0.5V fixed and Pedestal –0.6V) ABL control pin • Built-in sync separator for Sync on Green • Built-in blanking mixing function • Built-in OSD mixing function • Video period detection function • Built-in sharpness function • Built-in VBLK synchronous DAC refresh system Applications High resolution computer displays Structure Bipolar silicon monolithic IC Absolute Maximum Ratings (Ta = 25°C, GND = 0V) 14 V • Supply voltage VCC VCC2 7 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –65 to +150 °C • Allowable power dissipation PD 2.05 W Recommended Operating Conditions 12 ± 0.5 Supply voltage VCC VCC2 5 ± 0.5 V V Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E98210-PS CXA2066S Block Diagram SDA 1 2C I BUS DECORDER SCL 2 COF R 3 To each MODE switch D/A CONVERTER 30 CSYNC CONTRAST SUB CONTRAST (R) SUB CONTRAST (G) SUB CONTRAST (B) CUTOFF (R) OSD GAIN (R) CUTOFF (G) OSD GAIN (G) CUTOFF (B) OSD GAIN (B) CUTOFF (RGB) BRIGHTNESS (RGB) 29 ABL 28 S/H-R LPF COF G COF B 4 SUB CONTRAST 5 COF RGB 6 RIN 7 VCC2 8 GIN 9 27 ROUT Rch CONTRAST GAIN CONTROL DATA BLANKING MODE GAIN CONTROL AMP OSD GAIN (R) 5V OSD YS GENERATOR 26 GND-R BRIGHTNESS 25 S/H-G BLANKING BUFFER BLANKING PULSE AMP OSD SW OSD PULSE (13PIN) YS PULSE (17PIN) 24 GOUT VDET, SYNC SEP, SHARPNESS 23 GND-G SHARPNESS 12V GAIN CONT. T SW SYNC SEPARATOR SYNC IN 10 22 VCC 21 S/H-B VDET COMPARATOR 20 BOUT BIN 11 Gch CLP 12 Same as R channel 19 GND-B 18 BLKING OSD-R 13 to OSDSW Bch Same as R channel 17 YS OSD-G 14 to OSDSW to OSDSW OSD-B 15 16 VDET to OSDSW –2– CXA2066S Pin Description Pin No. Symbol Pin voltage Description Equivalent circuit VCC 1 I2C bus standard SDA (serial data) input/output. VILMAX = 1.5V VIHMIN = 3.5V VOLMAX = 0.4V 1 SDA 4k VCC 2 I2C bus standard SCL (serial clock) input. VILMAX = 1.5V VIHMIN = 3.5V 2 SCL 4k 10k VCC VCC 100 3 4 5 6 VCC COF R COF G COF B COF RGB Cut-off adjustment DAC outputs. The output DC is 1 to 4V. 3 4 5 6 VCC 1k 7 9 11 RIN GIN BIN 1.7V (when clamped) VCC VCC 14k 8k VCC VCC VCC 300 7 RGB signal inputs. Input via the capacitor. 9 11 1k 8 VCC2 5V 5V power supply. –3– CXA2066S Pin No. Symbol Pin voltage VCC SYNC IN VCC 100 VCC 10 Description Equivalent circuit 2.8V Sync on Green signal input. Input via the capacitor. 150 10 VCC VCC 10k 12 CLP 10k 10k 12 Clamp pulse (positive polarity) input. VILMAX = 0.8V VIHMIN = 2.8V VCC 13 14 15 VCC OSD-R OSD-G OSD-B 5k 10k 13 OSD control inputs. VILMAX = 0.8V VIHMIN = 2.8V 14 15 VCC2 VCC2 VCC2 VCC2 16 20k 100 5k Video detector output. Typ.; High = 4.3V Low = 0.2V VDET 16 –4– CXA2066S Pin No. Symbol Pin voltage Description Equivalent circuit VCC VCC 5k 17 YS YS (OSD_BLK) input. VILMAX = 0.8V VIHMIN = 2.8V 10k 17 VCC VCC 4k VCC 18 30k BLKING 10k 18 19 23 26 GND-B GND-G GND-R 0V Blanking pulse input. Set the V blanking pulse width to 300µs or more. VILMAX = 0.8V VIHMIN = 2.8V GNDs. VCC 0.5p VCC 20 24 27 BOUT GOUT ROUT 620 R, G, and B signal outputs. 20 24 27 VCC VCC 1k VCC 21 25 28 S/H-B S/H-G S/H-R Brightness sample-and-hold. Connect a capacitor to GND. 300 21 25 28 22 VCC 1k 12V 12V power supply. –5– CXA2066S Pin No. Symbol Pin voltage Description Equivalent circuit VCC VCC VCC VCC 25k 50k 29 ABL VCC 29 VCC2 VCC2 VCC2 15k 100 VCC2 30 ABL control input. Ground to GND when not using ABL. 25k Sync on Green signal sync separator output (positive polarity). Typ.; High = 4.3V Low = 0.2V CSYNC 30 –6– CXA2066S I2C BUS Register Definitions Slave Address SLAVE RECEIVER; 40 (HEX) Register Table SUB ADDRESS BIT7 BIT6 BIT5 BIT4 00H 01H BIT3 0 BLK MODE BIT0 BRIGHTNESS CUT OFF R 03H CUT OFF G 04H CUT OFF B VDET LEVEL OSD GAIN 06H CUT OFF RGB 07H SUB CONTRAST R 08H SUB CONTRAST G 09H SUB CONTRAST B 0AH BIT1 CONTRAST 02H 05H BIT2 V DET OFF SHP OFF SYNC OFF T SW SHP GAIN Sub Address 0000 CONTRAST (8) Controls the gain common to the R, G, and B channels. Since control is performed by multiplying with SUB CONTRAST, the white balance can be adjusted by SUB CONTRAST and the luminance can be adjusted by CONTRAST. 0: Gain minimum (–30dB or less) 255: Gain maximum (+17dB) Sub Address 0001 BLK MODE (1) Switches the blanking level. 0: Pedestal –0.6V 1: 0.5V fixed Sub Address 0001 BRIGHTNESS (6) Controls the black level common for the R, G, and B channels. 0: Black level minimum (1V) 63: Black level maximum (3V) Sub Address 0010 CUT OFF R (8) Controls Pin 3 (COF R) output voltage. 0: Output voltage minimum (1V) 255: Output voltage maximum (4V) Sub Address 0011 CUT OFF G (8) Controls Pin 4 (COF G) output voltage. 0: Output voltage minimum (1V) 255: Output voltage maximum (4V) Sub Address 0100 CUT OFF B (8) Controls Pin 5 (COF B) output voltage. 0: Output voltage minimum (1V) 255: Output voltage maximum (4V) –7– CXA2066S Sub Address 0101 VDET LEVEL (2) Controls the signal detection (VDET) slice level. 0: Slice level minimum (30mV when RIN = GIN = BIN) 3: Slice level maximum (220mV when RIN = GIN = BIN) Sub Address 0101 OSD GAIN (6) Controls the OSD gain common to the R, G, and B channels. Since control is performed by multiplying with SUB CONTRAST (upper 6 bits), white balance and tracking for the video is obtained. 0: Gain minimum (0Vp-p) 63: Gain maximum (5Vp-p) Sub Address 0110 CUT OFF RGB (8) Controls Pin 6 (COF RGB) output voltage. 0: Output voltage minimum (1V) 255: Output voltage maximum (4V) Sub Address 0111 SUB CONTRAST R (8) Controls the R channel gain. Control is performed by multiplying with CONTRAST. Use for adjusting the white balance. 0: Gain minimum (–30dB or less) 255: Gain maximum (+17dB) Sub Address 1000 SUB CONTRAST G (8) Controls the G channel gain. Control is performed by multiplying with CONTRAST. Use for adjusting the white balance. 0: Gain minimum (–30dB or less) 255: Gain maximum (+17dB) Sub Address 1001 SUB CONTRAST B (8) Controls the B channel gain. Control is performed by multiplying with CONTRAST. Use for adjusting the white balance. 0: Gain minimum (–30dB or less) 255: Gain maximum (+17dB) Sub Address 1010 VDET OFF (1) Controls the Pin 16 (VDET) output. 0: VDET output on 1: VDET output off Sub Address 1010 SHP OFF (1) Controls the sharpness function. 0: Sharpness on 1: Sharpness off Sub Address 1010 SYNC OFF (1) Controls the Pin 30 (CSYNC) output. 0: SYNC output on 1: SYNC output off Sub Address 1010 T SW (1) Controls the time constant during sharpness. 0: 50ns 1: 100ns Sub Address 1010 SHP GAIN (4) Controls the sharpness gain. 0: Gain minimum (–30dB or less) 15: Gain maximum (+7dB) –8– CXA2066S Electrical Characteristics No. 1 Measurement item Symbol Current consumption Frequency response (50MHz) ICC1 ICC2 F4 Measurement contents VCC and VCC2 pins inflow current Input signal: None Input continuous 1MHz, 50MHz, and 100MHz sine waves at 0.7Vp-p. Measure the output amplitude gain difference at this time. VOUT 50M Gain difference [dB] = 20 log VOUT 1M VOUT 100M Gain difference [dB] = 20 log VOUT 1M ( ( 2 Min. Typ. Max. Unit 65 88 110 mA 30 45 60 mA –1.7 0 1.7 ) ) dB RGB input signal (RGB input pins) Frequency response (100MHz) F5 0.7Vp-p –5.5 –1.85 1.8 4.5 5.0 5.5 Vp-p –30 35 100 mVp-p –30 35 100 mVp-p CLP potential (approximately 1.7V) GND Contrast control 1 Measure the level of the output signal amplitude VOUT when a 0.7Vp-p video signal is input. GCONT1 (ABL = 0V) VCONT1: Contrast = Sub Contrast = FF VCONT2: Contrast = 00/Sub Contrast = FF 3 Input signal Contrast control 2 4 Sub Contrast control 0.7Vp-p GCONT2 Measure the level of the output signal amplitude VOUT when a 0.7Vp-p video signal is input. (Contrast = FF/Sub Contrast = 00/ ABL = 0V) GSUB Input signal 0.7Vp-p –9– CXA2066S No. Measurement item Symbol GOSD1 5 Measurement contents Min. Typ. Max. Unit Measure the OSD level of the output signal when an OSD pulse is input. GOSD1: OSD = 3F/Sub Contrast = FF GOSD2: OSD = 00/Sub Contrast = FF 4.4 5.0 5.6 Vp-p –240 –70 80 mVp-p 0.8 1.1 1.4 RGB output signal OSD gain control OSD period OSD level GOSD2 VBRT1 6 Measure the black level of the RGB output signal. VBRT1: Brightness = 00 VBRT2: Brightness = 3F RGB output signal Brightness control V VBRT2 Black level 2.65 2.9 3.15 400 560 720 GND BLK control (BLK MODE = 0) VBLK1 Measure the BLK level of the output signal when a BLK pulse is input. 7 mV BLK level (VBLK1) BLK control (BLK MODE = 1) VBLK2 BLK level (VBLK2) GND – 10 – 200 310 420 CXA2066S No. Measurement item Symbol Sharpness gain 1 SHP1 Measurement contents Min. Typ. Max. Input a 30MHz sine wave to RGB at an amplitude of 0.1Vp-p, and measure the output level, and then calculate I/O gain. 8.9 10.9 12.9 14.6 16.6 18.6 Gain difference [dB] = 20 log Sharpness gain 2 SHP2 8 Sharpness gain 3 SHP3 Sharpness gain 4 SHP4 Output level Input level ( Unit ) (Contrast = 7F/Sub Contrast = FF/ ABL = 0V) SHP1: SHP GAIN = 0/T SW = 0 SHP2: SHP GAIN = F/T SW = 0 SHP3: SHP GAIN = 0/T SW = 1 SHP4: SHP GAIN = F/T SW = 0 dB 9.2 11.2 13.2 16.3 18.3 20.3 3.8 4.3 4.8 Input signal 0.1Vp-p CLP potential (approximately 1.7V) GND Input D range (VIN = 0.7V) VIND1 9 Input D range (VIN = 1.2V) VIND2 SYNCSEP SYNCHI output high level Measure the output level when 0.7Vp-p and 1.2Vp-p input video signals are input. (Contrast = CC, Sub Contrast = FF, Brightness = 00) Input a Sync on Green video signal to SYNCIN, and measure the CSYNC high level and low level. Vp-p 5.8 6.3 6.8 4.1 4.4 4.7 V 100 200 300 mV 42 50 10 High level SYNCSEP output low level SYNCLO SYNCSEP output rise delay SDLYR CSYNC Low level GND Input signal 11 Vth = 50% Rise delay SYNCSEP output fall delay CSYNC ns Fall delay Vth = 50% SDLYF 45 – 11 – 70 CXA2066S No. Measurement item Symbol VDET output high level VDETHI VDET output low level VDETLO Measurement contents Measure the VDET high level and low level when a 0.7Vp-p video signal is input to RGB. Min. Typ. Max. Unit 4.1 4.4 4.7 V 200 280 400 mV 17 40 12 High level VDET Low level GND VDET output rise delay VDDLYR Input signal Vth = 50% Rise delay 13 VDET VDET output fall delay VDDLYF DAC output voltage (COFF = 00) VCUT1 0.7Vp-p Fall delay ns Vth = 50% 0.9 26 50 1.1 1.3 Measure the DAC output voltage (Pins 3, 4, 5, and 6) when COFF = 00/FF. 14 DAC output voltage (COFF = FF) V 3.8 VCUT2 – 12 – 4 4.2 CXA2066S I2C BUS Logic System No. Item Symbol Min. Typ. Max. Unit 1 High level input voltage VIH 3.0 — 5.0 V 2 Low level input voltage VIL 0 — 1.5 V 3 Low level output voltage SDA, during current inflow of 3mA VOL 0 — 0.4 V 4 Maximum clock frequency fSCL 0 — 100 kHz 5 Minimum waiting time for data change 4.0 — — µs 6 Minimum waiting time for data transfer start 4.0 — — µs 7 Low level clock pulse width 4.7 — — µs 8 High level clock pulse width 4.0 — — µs 9 Minimum waiting time for start preparation 4.7 — — µs 10 Minimum data hold time 440 — — ns 11 Minimum data preparation time 250 — — ns 12 Rise time — — 1 µs 13 Fall time — — 300 ns 14 Minimum waiting time for stop preparation tBUF tHD; STA tLOW tHIGH tSU; STA tHD; DAT tSU; DAT tR tF tSU; STO 4.7 — — µs – 13 – CXA2066S Electrical Characteristics Measurement Circuit 1 SDA CSYNC 30 2 SCL ABL 29 3 COF R S/H-R 28 4 COF G ROUT 27 5 COF B GND-R 26 6 COF RGB S/H-G 25 7 RIN GOUT 24 8 VCC2 GND-G 23 SYNC SEP output 220 I2C BUS 220 0.1µF R channel output DAC output 0.1µF G channel output 0.1µF 75 5V 47µF 0.1µF 47µF 9 VCC 22 GIN 12V 0.1µF 75 0.1µF 10 SYNC IN S/H-B 21 11 BIN BOUT 20 12 CLP GND-B 19 0.1µF 0.1µF 75 B channel output 0.1µF 75 13 OSD-R BLKING 18 14 OSD-G YS 17 15 OSD-B VDET 16 – 14 – Video detector output CXA2066S Electrical Characteristics Measurement Circuit (Frequency Response) 1 SDA CSYNC 30 2 SCL ABL 29 3 COF R S/H-R 28 4 COF G ROUT 27 5 COF B GND-R 26 6 COF RGB S/H-G 25 7 RIN GOUT 24 8 VCC2 GND-G 23 SYNC SEP output 220 I2C BUS 220 0.1µF R channel output DAC output 0.1µF 1k G channel output 0.1µF 50 5V 47µF 0.1µF 1k 47µF 9 VCC 22 GIN 12V 0.1µF 50 0.1µF 10 SYNC IN S/H-B 21 11 BIN BOUT 20 12 CLP GND-B 19 0.1µF 0.1µF 1k B channel output 0.1µF 50 13 OSD-R BLKING 18 14 OSD-G YS 17 15 OSD-B VDET 16 – 15 – Video detector output CXA2066S Description of Operation 1. Sharpness function The RGB signals input to Pins 7, 9, and 11 are mixed at a ratio of 0.6G + 0.3R + 0.1B to form the Y signal. The high-frequency component is removed from this Y signal by a differentiation circuit, and the amplitude is controlled by a gain control circuit. The signal which undergoes gain control (sharpness component) has its amplitude clipped by a limiter circuit and is then added to the R, G, and B signals. SHP GAIN = 0 (HEX) or SHP OFF = 1 No sharpness component Section not sent to RGB output because of the limiter 100% Limiter level = 30% (Typ.) SHP GAIN = F (HEX) 100% 10% 50ns (T SW = 0) 100ns (T SW = 1) ∗ RGB output when RIN = GIN = BIN = 0.7Vp-p The output level is set to 100%. 2. VBLK synchronous DAC refresh system The VBLK signal is removed from the composite BLK signal which has been input to Pin 18, and the data for each control DAC is overwritten all at once in synchronization with this VBLK signal. The received I2C bus data is held by a latch until the next VBLK signal arrives. As a result, I2C bus data transmission from the microcomputer is timing-free. Set the V blanking pulse width which is input to Pin 18 at 300µs or more. – 16 – – 17 – DAC refresh signal DAC refresh enable signal Bus data transmission Vsync enable The newest transmission data before Vsync is written to the DAC. In this case, the data in (1) is written. disable Data group (1) Transmission period VBLK Synchronous DAC Refresh System The DAC is not overwritten while the bus data in the Vsync period is being transmitted. The transmitted data is held. Data group (2) Overwritten by the data in (3). If (3) is not transmitted, this is overwritten by the data in (2). Data group (3) CXA2066S CXA2066S Application Circuit 1 SDA CSYNC 30 2 SCL ABL 29 3 COF R SYNC SEP output 220 I2C BUS ABL input 220 S/H-R 28 0.1µF 4 COF G ROUT 27 5 COF B GND-R 26 6 COF RGB R channel output DAC output S/H-G 25 0.1µF R channel input 7 RIN GOUT 24 8 VCC2 GND-G 23 G channel output 0.1µF 75 47µF 5V 0.1µF G channel input 47µF 9 12V VCC 22 GIN 0.1µF 75 0.1µF Sync on Green input 10 SYNC IN S/H-B 21 0.1µF 0.1µF 75 B channel input 11 BIN BOUT 20 12 CLP GND-B 19 B channel output 0.1µF 75 Clamp pulse input OSD pulse (R channel) input 13 OSD-R BLKING 18 OSD pulse (G channel) input 14 OSD-G YS 17 OSD pulse (B channel) input 15 OSD-B VDET 16 Blanking pulse input ∗ VBLK ≥ 300µs YS input Video detector output Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 18 – CXA2066S Example of Representative Characteristics CONTRAST Control Characteristics OSD Gain Control Characteristics 5 5 SUB CONTRAST = 255 SUB CONTRAST = 127 SUB CONTRAST = 255 SUB CONTRAST = 127 OSD output amplitude [Vp-p] Output amplitude [Vp-p] 4 Video IN = 0.7Vp-p 3 2 1 0 0 50 100 150 CONTRAST DATA 200 4 3 2 1 0 250 0 SUBCONT Control Characteristics 5 200 250 Video IN = 0.7Vp-p SUB CONTRAST = FF (HEX) CONTRAST = FF (HEX) CONTRAST = 255 CONTRAST = 127 4 4 Video IN = 0.7Vp-p Output amplitude [Vp-p] Output amplitude [Vp-p] 100 150 OSD GAIN DATA ABL Control Characteristics 5 3 2 1 0 50 3 2 1 0 50 100 150 200 SUB CONTRAST DATA 0 250 – 19 – 0 1 2 3 4 Voltage Applied to Pin 29 [V] 5 CXA2066S Notes on Operation 1. Set the output for ROUT, GOUT, and BOUT for reception at high impedance. 2. Make the wiring from ROUT, GOUT, and BOUT to the power amplifier as short as possible. 3. Connect the VCC and VCC2 decoupling capacitor so that the ceramic capacitor and electrolytic capacitor are connected in parallel and the distance from the IC is as short as possible. 4. Connect the clamp capacitor for RIN, GIN, BIN, S/H-R, S/H-G, S/H-B so that the distance from the IC is as short as possible. 5. Set the output to OFF when the VDET output is not used (Set I2C BUS VDETOFF "1"). – 20 – CXA2066S Package Outline Unit: mm + 0.1 .05 0.25 – 0 30PIN SDIP (PLASTIC) + 0.4 26.9 – 0.1 30 + 0.3 8.5 – 0.1 10.16 16 0° to 15° 15 1 + 0.4 3.7 – 0.1 0.5 MIN 1.778 0.5 ± 0.1 3.0 MIN Two kinds of package surface: 1.All mat surface type. 2.All mirror surface type. 0.9 ± 0.15 PACKAGE STRUCTURE MOLDING COMPOUND EPOXY RESIN SONY CODE SDIP-30P-01 LEAD TREATMENT SOLDER/PALLADIUM PLATING EIAJ CODE SDIP030-P-0400 LEAD MATERIAL COPPER ALLOY PACKAGE MASS 1.8g JEDEC CODE NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). – 21 –