CXA2111R
LCD Signal Processor (Gamma Correction)
Description
The CXA2111R is a signal processor IC developed
for LCD panels. Gamma correction, gain and bias,
etc., can be adjusted using the I2C bus and external
adjustment pins. The output of this IC is ideal as the
input of the CXA2112R (LCD sample-and-hold
driver IC), and the sample-and-hold position, etc.,
can also be adjusted using the I2C bus.
Features
• Independent R, G and B gamma adjustment
• Three-point gamma gain and position adjustment
(one white side point, two black side points)
• Independent R, G and B output amplifier gain and
bias adjustment
• Various I2C bus-based controls and adjustment of
various characteristics by external DC input
• Input signal clamp function (variable clamp voltage)
• Black side limiter adjustment
• CXA2112R adjustment output
• Precharge output (for CXA2112R)
• High frequency response
• High slew rate output
52 pin LQFP (Plastic)
Absolute Maximum Ratings
–0.3 to +5.5 V
• Supply voltage
VCC
• Input voltage
VI –0.3 to VCC + 0.3 V
• Storage temperature
Tstg –65 to +150 °C
• Allowable power dissipation
PD
1000
mW
Operating Conditions
• Supply voltage
• Digital input voltage high
• Digital input voltage low
• Operating temperature
VCC
VH
VL
Topr
4.75 to 5.25
2.2 to VCC
0 to 0.8
–20 to +70
V
V
V
V
Applications
• Liquid crystal projectors
• Compact liquid crystal monitors
Structure
Bipolar silicon monolithic IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E97448-PS
CXA2111R
GAMG_B2P 40
AMPBBIAS
AMPGBIAS
AMPRBIAS
AMPBGAIN
AMPGGAIN
AMPRGAIN
36 35
GAMR_WHP
GAMG_WHP
38 37
GAMB_WHP
GAMB_B1P
39
GAMR_B1P
GAMR_B2P
GAMG_B1P
Pin Configuration and Block Diagram
34 33
32
31
30 29
28
27
26 BIN
γ
CLAMP
AMP
DRIVER
GAMB_B2P 41
25 CLPLEV
GAMR_WHG 42
24 GIN
γ
CLAMP
AMP
DRIVER
GAMG_WHG 43
23 ATT
GAMB_WHG 44
22 RIN
γ
CLAMP
AMP
DRIVER
GAMR_B1G 45
21 VCC
γ • AMP Adjust
CLAMP
Control
GAMG_B1G 46
20 CLPPLS
19 GND
GAMB_B1G 47
GAMR_B2G 48
18 ROUT
DAC/Control
6bit × 25
GAMG_B2G 49
Input
I/F
GAMB_B2G 50
SCL 51
DIR_CNT
INV_CNT
9
10
11
12
13
GAMOFF
DLY_CNT
8
BLKLIM
POS_CNT2
7
PRGLEV
POS_CNT1
6
PRGPLS
5
SIDLEV
4
V33
3
14 BOUT
DATEST
2
PRG/SID
SIDOUT
1
16 GOUT
15 PGND
Output
I/F
SDA 52
17 PVCC
I2C Bus
–2–
CXA2111R
Pin Description
Pin
No.
1
Symbol
I/O
Equivalent circuit
POS_CNT1
VCC
O
2
Typical
pin voltage
0 to 5V
(4 value)
VCC
VCC
1
300
2
70k
3
DLY_CNT
O
3 to 5V
VCC
25k
300
CXA2112R control.
The sample-and-hold position is
determined by the I2C data.
POS_CNT1 is the low-order 4-value
output and POS_CNT2 is the highorder 4-value output for a total of 16value control.
I2C data input (2 bits)
00
01
10
11
POS_CNT2
VCC
Description
3
Pin output
L
↓
↓
H
CXA2112R control.
The clock delay time is controlled by
output analog value using I2C data.
I2C data input (6 bits)
all 0
↓
all 1
Pin output
5V
↓
3V
CXA2112R control.
The scan direction is determined by
the I2C data.
4
DIR_CNT
VCC
VCC
O
L/H
(0V/5V)
300
Pin output
H
L
4
5
5
20k
I2C data input (1 bit)
0
1
CXA2112R control.
The clock polarity is determined by the
I2C data.
INV_CNT
I2C data input (1 bit)
0
1
Pin output
H
L
VCC
VCC
Output for CXA2112R.
This pin outputs the precharge signal.
6
SIDOUT
7
DATEST
O 2.3 to 3.3V
6
Pin 6 output
Pin 10 input
Level controlled by Pin 11
H
Level controlled by Pin 9
L
DAC test output.
Set the I2C data to "1". This pin is
normally open.
–3–
CXA2111R
Pin
No.
Symbol
I/O
Typical
pin voltage
Equivalent circuit
Description
VCC
VCC
8
V33
9
SIDLEV
O
3.3V
Output for CXA2112R.
This pin outputs 3.3V.
8
VCC
VCC
50k
50k
I
0 to 5V
11
11
These pins determine the Pin 6 output
level.
See Pin 6.
9
75k
100µ
PRGLEV
VCC
VCC
10
PRGPLS
I
L/H
L: 0 to 0.8V
H: 2.2 to 5V
BLKLIM
I
This pin determines the Pin 6 output.
See Pin 6.
Set to low or high when using SIDOUT
(Pin 6) as a DC output.
750µ
Output black level (low level side) limit
voltage control.
Apply voltage of 1V DC or more.
300
10
VCC
VCC
12
25µ
1 to 5V
1.6k
12
VCC
I2C data input
(1bit)
VCC
13
GAMOFF
I
L/H
L: 0 to 0.8V
H: 2.2 to 5V
Gamma characteristics ON/OFF setting.
Pin 13 input
γ mode
H
L
H
L
γ ON
γ OFF
γ OFF
γ OFF
50k
0
300
13
1
14
BOUT
14
16
GOUT
PVCC
PVCC
O 1.8 to 3.3V
50
B channel output.
G channel output.
16
18
18
ROUT
15
PGND
GND
17
PVcc
5V
19
GND
GND
GND
R channel output.
GND.
5V
GND.
–4–
CXA2111R
Pin
No.
Symbol
I/O
Typical
pin voltage
Equivalent circuit
VCC
VCC
20
CLPPLS
21
Vcc
22
RIN
24
GIN
I
L/H
L: 0 to 0.8V
H: 2.2 to 5V
50µ
300
Pin input
H
L
VCC
G channel input.
300
170µ
BIN
B channel input.
VCC
VCC
23
ATT
I
L/H
L: 0 to 0.8V
H: 2.2 to 5V
50µ
VCC
50µ
CLPLEV
I
0 to 5V
60k
25
20k
2.5V
27
28
AMPRGAIN
Input signal gain control.
This pin also supports 2Vp-p input.
Pin input Clamp block gain Signal level
For 1Vp-p
H
0dB
For 2Vp-p
L
–6dB
300
23
VCC
25
R channel input.
22
24
26
26
Clamp function
ON
OFF
5V
VCC
1.5 to 3.5V
Input signal clamp pulse input.
Set to low when not using the clamp
function.
20
5V
I
Description
Clamp voltage control during clamp
operation.
Pin input
5V
↓
2.5V (open)
↓
0V
Clamp voltage
2.5V
↓
2.0V
↓
1.5V
VCC
27
AMPGGAIN
2.5V
Amplifier gain control.
Independent control for R, G and B.
Equivalent to 2.5V input when open.
2.5V
Amplifier bias control.
Independent control for R, G and B.
Equivalent to 2.5V input when open.
25k
28
29
29
AMPBGAIN
I
30
31
0 to 5V
AMPRBIAS
AMPGBIAS
VCC
30
25k
31
32
32
AMPBBIAS
–5–
CXA2111R
Pin
No.
Symbol
33
GAMR_WHP
I/O
Typical
pin voltage
Equivalent circuit
Description
VCC
2.5V
34
33
GAMG_WHP
25k
34
Gamma white position control.
Independent control for R, G and B.
Equivalent to 2.5V input when open.
35
35
GAMB_WHP
36
GAMR_B1P
37
GAMG_B1P
38
GAMB_B1P
39
GAMR_B2P
40
GAMG_B2P
41
GAMB_B2P
Gamma black 1 position control.
Independent control for R, G and B.
Equivalent to 2.5V input when open.
I
0 to 5V
43 36
Gamma black 2 position control.
Independent control for R, G and B.
Equivalent to 2.5V input when open.
VCC
44 37
45 38
42
GAMR_WHG
43
GAMG_WHG
47 40
44
GAMB_WHG
48 41
45
GAMR_B1G
46
GAMG_B1G
47
GAMB_B1G
48
GAMR_B2G
49
GAMG_B2G
50
GAMB_B2G
51
SCL
2.5V
25k
Gamma white gain control.
Independent control for R, G and B.
Equivalent to 2.5V input when open.
46 39
49 42
Gamma black 1 gain control.
Independent control for R, G and B.
Equivalent to 2.5V input when open.
50
Gamma black 2 gain control.
Independent control for R, G and B.
Equivalent to 2.5V input when open.
VCC
I
I2C bus clock input.
50µ
L/H
(0V/5V)
52
SDA
I/O
4k
51
52
I2C bus data input.
–6–
CXA2111R
I2C Bus Format
Slave address: 0111 0110 (76h)
Sub address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
∗∗∗00000 (00h)
AMPRGAIN
∗∗∗00001 (01h)
AMPGGAIN
∗∗∗00010 (02h)
AMPBGAIN
∗∗∗00011 (03h)
AMPRBIAS
∗∗∗00100 (04h)
AMPGBIAS
∗∗∗00101 (05h)
AMPBBIAS
∗∗∗00110 (06h)
GAMR_WHP
∗∗∗00111 (07h)
GAMG_WHP
∗∗∗01000 (08h)
GAMB_WHP
∗∗∗01001 (09h)
GAMR_B1P
∗∗∗01010 (0Ah)
GAMG_B1P
∗∗∗01011 (0Bh)
GAMB_B1P
∗∗∗01100 (0Ch)
GAMR_B2P
∗∗∗01101 (0Dh)
GAMG_B2P
∗∗∗01110 (0Eh)
GAMB_B2P
∗∗∗01111 (0Fh)
GAMR_WHG
∗∗∗10000 (10h)
GAMG_WHG
∗∗∗10001 (11h)
GAMB_WHG
∗∗∗10010 (12h)
GAMR_B1G
∗∗∗10011 (13h)
GAMG_B1G
∗∗∗10100 (14h)
GAMB_B1G
∗∗∗10101 (15h)
GAMR_B2G
GAMOFF DATEST
∗∗∗10110 (16h)
GAMG_B2G
POS_CNT2
∗∗∗10111 (17h)
GAMB_B2G
POS_CNT1
∗∗∗11000 (18h)
DLY_CNT
DIR_CNT INV_CNT
–7–
CXA2111R
Electrical Characteristics (See the Electrical Characteristics Measurement Circuit.)
No.
Item
(VCC, PVCC = 5V, Ta = 25°C)
MeasuSymbol rement Measurement conditions and measurement outline
point
Min.
Typ.
[Gamma gain (white, black 1, black 2) = max.,
amplifier gain = max.]
V22, 24, and 26 = 2.5V, V27 to 29 and 42 to 50 =
5V, V30 to 41 = open, Measure the I21 current.
80
135
1
Current
consumption
Icc
2
Digital input
voltage high
Vih
Excluding the I2C bus pins (Pins 51 and 52).
3
Digital input
voltage low
Vil
Excluding the I2C bus pins (Pins 51 and 52).
4
Maximum input
voltage amplitude
Vix
Pins 22, 24 and 26 input
5
Maximum output
voltage amplitude
Vox
6
I21
Max. Unit
180
mA
2.2
Vcc
V
GND
0.8
V
2
V
V
V14
V16
V18
Pins 14, 16 and 18 output
1.5
Gamma white gain
Ggwx
max.
V14
V16
V18
V27 to 29 and 36 to 44 = 5V, V30 to 35 = open, V45 to 50 = 0V
Calculate Vwx/Vo (a) for the maximum Vwx at Vo (e),
Vo (f) and Vo (g).
6.0
7.4
9.2
7
Gamma black 1
gain max.
Ggb1x
V14
V16
V18
V27 to 29, 39 to 41 and 45 to 47 = 5V, V30 to 32 and
36 to 38 = open, V33 to 35, 42 to 44 and 48 to 50 = 0V.
Calculate Vb1x/Vo (i) for the maximum Vb1x at Vo (c),
Vo (d) Vo (e) and Vo (f).
8.0
9.5
11.6 times
8
Gamma black 2
gain max.
Ggb2x
V14
V16
V18
V27 to 29, 36 to 38 and 48 to 50 = 5V, V30 to 32 =
3.75V, V33 to 35 and 42 to 47 = 0V, V39 to 41 = 3.3V
16.0
Calculate Vb2x/Vo (h) for the maximum Vb2x at Vo (a),
Vo (b) and Vo (c).
19.7
26.8 times
9
Amplifier gain max. Gax
V14
V16
V18
V13 = 0V, V27 to 29 = 0V, V30 to 50 = open
Calculate Vo (j)/0.1.
1.65
2.26
3.25 times
10
Amplifier gain min. Gan
V14
V16
V18
V13 = 0V, V27 to 29 = 5V, V30 to 50 = open
Calculate Vo (j)/0.1.
0.28
0.35
0.46 times
11
Amplifier bias
output variable
range
V14
V16
V18
V13 = 0V, V22, 24 and 26 = 2.5V,
V27 to 29 = 0.75V, V33 to 50 = open
V14, 16 and 18 voltages when V30 to 32 = 0V,
open and 5V.
Calculate Vb (0V) – Vb (open) and Vb (5V) – Vb
(open) at Vb (0V), Vb (open) and Vb (5V).
±0.80 ±0.96 ±1.15
12
Gamma white gain
Ggwxi
I2C max.
V14
V16
V18
V27 to 29 and 36 to 44 = 5V, V30 to 35 and 42 to
44 = open, V45 to 50 = 0V, I2C data = 3Fh
Calculate Vwxi/Vo (a) for the maximum Vwxi at
Vo (e), Vo (f) and Vo (g).
5.85
7.21
8.65
13
Gamma white gain
Ggwni
I2C min.
V14
V16
V18
V27 to 29 and 36 to 44 = 5V, V30 to 35 and 42 to
44 = open, V45 to 50 = 0V, I2C data = 00h
Calculate Vwni/Vo (a) for the maximum Vwni at
Vo (e), Vo (f) and Vo (g).
3.80
4.71
5.65 times
V14
Ggb1xi V16
V18
V27 to 29, 39 to 41 and 45 to 47 = 5V, V30 to 32,
36 to 38 and 45 to 47 = open, V33 to 35, 42 to 44
and 48 to 50 = 0V, I2C data = 3Fh
Calculate Vb1xi/Vo (i) for the maximum Vb1xi at
Vo (c), Vo (d) Vo (e) and Vo (f).
7.6
9.11
10.7 times
V27 to 29, 39 to 41 and 45 to 47 = 5V, V30 to 32,
36 to 38 and 45 to 47 = open, V33 to 35, 42 to 44
and 48 to 50 = 0V, I2C data = 00h
Calculate Vb1ni/Vo (i) for the maximum Vb1ni at
Vo (c), Vo (d) Vo (e) and Vo (f).
5.05
6.02
7.00 times
V27 to 29, 36 to 38 and 48 to 50 = 5V, V30 to 32 =
3.75V, V33 to 35 and 42 to 47 = 0V, V39 to 41 =
3.3V, V48 to 50 = open, I2C data = 3Fh
Calculate Vb2xi/Vo (h) for the maximum Vb2xi at
Vo (a), Vo (b) and Vo (c).
15.8
19.5
23.2 times
14
15
16
Gamma black 1
gain I2C max.
Gamma black 1
gain I2C min.
Gamma black 2
gain I2C max.
Vab
V14
Ggb1ni V16
V18
V14
Ggb2xi V16
V18
–8–
times
V
times
CXA2111R
No.
Item
MeasuSymbol rement Measurement conditions and measurement outline
point
V27 to 29, 36 to 38 and 48 to 50 = 5V, V30 to 32 =
V14 3.75V, V33 to 35 and 42 to 47 = 0V, V39 to 41 =
Ggb2ni V16 3.3V, V48 to 50 = open, I2C data = 3Fh
V18 Calculate Vb2xi/Vo (h) for the maximum Vb2xi at
Vo (a), Vo (b) and Vo (c).
Min.
Typ.
Max. Unit
11.3
14.0
16.7 times
17
Gamma black 2
gain I2C min.
18
Amplifier gain
I2C max.
Gaxi
V14
V16
V18
V13 = 0V, V27 to 50 = open, I2C data = 00h
Calculate Vo (j)/0.1.
0.44
0.55
0.67 times
19
Amplifier gain
I2C min.
Gani
V14
V16
V18
V13 = 0V, V27 to 50 = open, I2C data = 3Fh
Calculate Vo (j)/0.1.
0.30
0.39
0.47 times
20
Amplifier bias I2C
output variable
range
Vabi
V14
V16
V18
V13 = 0V, V22, 24 and 26 = 2.5V, V27 to 29 = 0.75V,
V30 to 50 = open
V14, 16 and 18 voltages when I2C data = 00h, 20h and 3Fh.
Calculate Vbi (00h) – Vbi (20h) and Vbi (3Fh) –
Vbi (20h) at Vbi (00h), Vbi (20h) and Vbi (3Fh).
±0.34 ±0.39 ±0.45
21
Frequency
response
Gf
V14
V16
V18
[Gamma OFF, amplifier gain min., ratio of 100MHz to 20MHz]
V13 = 0V, V27 to 29 = 5V, V30 to 50 = open
Calculate 20∗LOG {Vo (k)/Vo (j)}.
–2.7
22
Clamp voltage
min.
Vcn
Vr
Vg
Vb
SW22, 24, 26 = b, SW25 = ON
V20 = 5V, V25 = 0V
1.35
1.45
1.55
V
23
Clamp voltage
max.
Vcx
Vr
Vg
Vb
SW22, 24, 26 = b, SW25 = ON
V20 = 5V, V25 = 5V
2.75
2.85
2.95
V
24
Black limiter
voltage
Vbl
V14
V16
V18
V12 = 1.3V, V13 = 0V, V22, 24, 26 = 2V,
V27 to 29 = 0.75V, V30 to 32 = 0V, V33 to 50 = open
1.00
1.19
1.35
V
25
Output maximum
voltage value
Vwl
(white limiter voltage)
V14
V16
V18
V13, 27 to 29 = 0V, V22, 24, 26 = 3.1V,
V30 to 32 = 5V, V33 to 50 = open
3.50
3.71
4.00
V
26
SIDOUT output min.
Vsn
V6
V9 = V11 = 0.5 V, V10 = 0V or 5V
1.75
1.98
2.15
V
27
SIDOUT output max. Vsx
V6
V9 = V11 = 4.5 V, V10 = 0V or 5V
3.30
3.48
3.65
V
28
I2C DAC (6-bit)
DLE
Dle
DAC output when DAC data = 00h, 1Fh, 20h and 3Fh.
Calculate | {V (20h) – V (1Fh)}/[{V (3Fh) – V (00h}/63] |
– 1 at V (00h), V (1Fh), V (20h) and V (3Fh).
–0.9
0.6
LSB
29
Output rise/fall
time
<Reference data>
Trf
30
Gamma position max.
(white/black 1/black 2) Pgx
<Reference data>
With input DC 2.0 to 3.0V set as 0 to 100 IRE
V33 to V41 = 0V
31
Gamma position min.
(white/black 1/black 2) Pgn
<Reference data>
With input DC 2.0 to 3.0V set as 0 to 100 IRE
V33 to V41 = 5V
32
Gamma position
I2C max. (white)
<Reference data>
Pgwxi
With input DC 2.0 to 3.0V set as 0 to 100 IRE
V33 to 35 = open, I2C data = 3Fh
100
IRE
33
Gamma position
I2C min. (white)
<Reference data>
Pgwni
With input DC 2.0 to 3.0V set as 0 to 100 IRE
V33 to 35 = open, I2C data = 00h
40
IRE
34
Gamma position I2C
max. (black 1/black 2) Pgbxi
<Reference data>
With input DC 2.0 to 3.0V set as 0 to 100 IRE
V36 to 41 = open, I2C data = 00h
70
IRE
35
Gamma position I2C
min. (black 1/black 2)
<Reference data>
With input DC 2.0 to 3.0V set as 0 to 100 IRE
V36 to 41 = open, I2C data = 3Fh
0
IRE
Pgbni
V14
V16
V18
Gamma OFF, gain adjusted so that 1Vp-p pulse
input results in 1.5Vp-p output, output 3pF load
–9–
V
dB
ns
4
IRE
100
0
IRE
GAMB_WHG
GAMR_B1G
GAMG_B1G
GAMB_B1G
GAMR_B2G
GAMG_B2G
GAMB_B2G
DLY_CNT
POS_CNT1
POS_CNT2
DIR_CNT
INV_CNT
GAMOFF
DATEST
18
19
20
21
22
23
24
25
26
27
28
29
30
31
GAMB_B1P
12
GAMG_WHG
GAMG_B1P
11
17
GAMR_B1P
10
GAMR_WHG
GAMB_WHP
9
16
GAMG_WHP
8
GAMB_B2P
GAMR_WHP
7
15
AMPBBIAS
6
GAMG_B2P
AMPGBIAS
5
14
AMPRBIAS
4
GAMR_B2P
AMPBGAIN
3
13
AMPGGAIN
2
1
0
0
0
00
00
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
20h
20h
20h
00h
00h
00h
V52
V51
V50
V49
V48
V47
V46
V45
V44
V43
V42
V41
V40
50
49
48
47
46
45
44
43
42
41
40
SCL
51
I2C input
(clock)
SDA
52
I2C input
(data)
GAMB_B2G
GAMG_B2G
GAMR_B2G
GAMB_B1G
GAMG_B1G
GAMR_B1G
GAMB_WHG
GAMG_WHG
GAMR_WHG
GAMB_B2P
GAMG_B2P
38
V38
V37
37
35
V35
CLAMP
Control
CLAMP
CLAMP
CLAMP
AMP
AMP
AMP
V6
9
8
7
6
V9
PRG/SID
DRIVER
DRIVER
DRIVER
5
Bus
V31
31
4
I2C
6bit × 25
DAC/Control
γ • AMP Adjust
γ
γ
γ
V32
32
to DAC/Control
33
V33
3
34
V34
2
Output
I/F
36
V36
1
Input
I/F
to DAC/Control
V39
39
GAMR_B2P
POS_CNT1
Data
GAMB_B1P
POS_CNT2
Item
GAMG_B1P
DLY_CNT
AMPRGAIN
GAMR_B1P
DIR_CNT
1
GAMB_WHP
INV_CNT
No.
GAMG_WHP
SIDOUT
Slave address = 76h
GAMR_WHP
DATEST
<I2C standard data>
AMPBBIAS
V33
V30
V10
11
29
V11
V29
10
30
AMPRBIAS
PRGPLS
AMPGBIAS
SIDLEV
AMPBGAIN
PRGLEV
12
V27
27
AMPRGAIN
V12
1V
13
V13
5V
to CLAMP
Control
to CLAMP
Control
to CLAMP
Control
V28
28
AMPGGAIN
BLKLIM
– 10 –
GAMOFF
Electrical Characteristics Measurement Circuit
14
15
16
17
18
19
20
21
22
23
24
25
26
BOUT
0.1µ
PGND
GOUT
PVCC
ROUT
0.1µ
GND
CLPPLS
VCC
RIN
ATT
GIN
CLPLEV
BIN
0.1µ
Vb
V26
V18
V14
V16
47µ/16V
I21 V21 5V
V20 0V
47µ/16V
V22
V23 5V
0.1µ
0.1µ
a SW22
b
b
SW25
V24
a SW24
a SW26
V25 5V
b
Vr
Vg
2.15Vdc + 0.1Vp-p 20MHz
2.25Vdc + 0.1Vp-p 20MHz
2.35Vdc + 0.1Vp-p 20MHz
2.45Vdc + 0.1Vp-p 20MHz
2.55Vdc + 0.1Vp-p 20MHz
2.65Vdc + 0.1Vp-p 20MHz
2.75Vdc + 0.1Vp-p 20MHz
2.85Vdc + 0.1Vp-p 20MHz
2.95Vdc + 0.1Vp-p 20MHz
2.5Vdc + 0.1Vp-p 20MHz
2.5Vdc + 0.1Vp-p 100MHz
In addition, the V14, 16 and 18
output levels for the above inputs
(x) are labeled Vo (x).
(a)
(b)
(c)
(d)
(e)
(f)
(g)
(h)
(i)
(j)
(k)
The following sine wave signals
are defined as the V22, 24 and
26 inputs.
CXA2111R
CXA2111R
Description of Operation
1. Gamma control
The bend positions and respective gains of one
white side point and two black side points can be
varied.
Control is performed independently for R, G and B
by the I2C bus or by external DC.
In addition, the gamma function can easily be
forced OFF (by Pin 13 or the I2C bus).
White gain
Gamma
OFF
Black 1 position
White position
Black 2 position
Black 1 gain
Black 2 gain
2. Amplifier gain and bias control
After adjusting the gamma, the signal gain and DC voltage can also be adjusted.
3. SIDOUT
SIDOUT generates the precharge signal.
After the CXA2111R determines the DC level (Pins 9 and 11) and the pulse width (Pin 10), the signal is
inverted by the CXA2112R and applied to the LCD panel.
See the Example of Representative Characteristics for the DC level.
PRGPLS input
(Pin 10)
Voltage determined by Pin 9
SIDOUT output
(Pin 6)
Voltage determined by Pin 11
Output example
4. I2C bus
The various gamma and amplifier controls can be performed in accordance with the I2C Bus Format table.
In addition, the sample-and-hold position and other items can also be controlled by connecting the
CXA2112R.
– 11 –
CXA2111R
Notes on Operation
1. External DC voltage adjustment, I2C adjustment and variable ranges
(a) When varying the external DC voltage
Setting the I2C data to the standard setting values (listed in the Electrical Characteristics Measurement
Circuit) is recommended when performing the various adjustments using the external pins (Pins 27 to 50).
Note that setting data that differs from these standard setting values may clip one side of the variable
ranges below.
(b) When varying the I2C setting
The variable ranges when the external pins are open or 2.5V are as shown in the table below. The I2C
variable range position can be altered by changing the voltage applied to the external pins. However, note
that characteristics in excess of the range in (a) above cannot be obtained.
(a) External voltage adjustment (b) I2C adjustment (external pins open or 2.5V)
× 7.4
5V
γ white gain
×1
5V
γ black 1 gain
×1
3Fh
× 4.71
00h
0V
(I2C standard setting 00h)
× 9.5
× 7.21
The variable position can be altered
by changing the external voltage.
× 9.11
3Fh
× 6.02
00h
× 19.5
3Fh
× 14.0
00h
0V
(I2C standard setting 00h)
× 19.7
5V
γ black 2 gain
×1
0V
(I2C standard setting 00h)
– 12 –
CXA2111R
(a) External voltage adjustment (b) I2C adjustment (external pins open or 2.5V)
100 IRE
0V
γ white position
0 IRE
100 IRE
3Fh
40 IRE
00h
70 IRE
00h
0 IRE
3Fh
70 IRE
00h
0 IRE
3Fh
5V
(I2C standard setting 00h)
100 IRE
0V
γ black 1 position
0 IRE
5V
(I2C standard setting 00h)
100 IRE
0V
γ black 2 position
0 IRE
5V
(I2C standard setting 00h)
Note) The 0 to 100 IRE levels here correspond to the following values when ATT (Pin 23) is high.
Clamp OFF: Input 2 to 3V (1Vp-p)
Clamp ON: Input 1Vp-p (however, Pin 25 = open or 2.5V)
– 13 –
CXA2111R
(a) External voltage adjustment (b) I2C adjustment (external pins open or 2.5V)
× 2.26
0V
× 0.55
00h
× 0.39
3Fh
+0.39V
00h
0V
20h
–0.39V
3Fh
Amplifier gain
× 0.35
5V
(I2C standard setting 00h)
+0.96V
0V
Amplifier bias
(relative variation)
–0.96V
5V
2.5V
0V
(I2C standard setting 20h)
2. Input signal level and clamp
Set Pin 23 (ATT) low when the input amplitude exceeds 1Vp-p (up to 2Vp-p).
In this case, care should be taken for the clamp voltage setting (Pin 25) when applying the clamp. See the
figure below.
(The input pin voltage should not exceed the range of 1.5V DC to 3.5V DC.)
Pin 25 setting voltage range
2.5Vdc ± 2.5V
(0 to 5V)
2.5Vdc ± 0V
1Vp-p
2Vp-p
Input level
3. I2C bus
The CXA2111R requires I2C bus control.
The initial values must be set after power-on even when using only external DC adjustment.
– 14 –
CXA2111R
38
39
GAMG_B2P
GAMB_B2P
GAMR_WHG
GAMG_WHG
GAMB_WHG
37
35
36
GAMG_B1G
GAMB_B1G
30
29
28
AMPRGAIN
AMPGGAIN
AMPBGAIN
AMPRBIAS
AMPGBIAS
31
27
26
to DAC/Control
41
25
to CLAMP
Control
42
CLAMP
γ
AMP
DRIVER
CLAMP
γ
AMP
DRIVER
43
24
23
to CLAMP
Control
44
22
γ
CLAMP
GAMR_B1G
32
33
34
40
AMPBBIAS
GAMR_WHP
GAMG_WHP
GAMB_WHP
GAMR_B1P
GAMG_B1P
GAMB_B1P
GAMR_B2P
Application Circuit
45
AMP
BIN
0.1µ
CLPLEV
GIN
0.1µ
ATT
RIN
0.1µ
DRIVER
21
to DAC/Control
5V
VCC
47µ/16V
CLAMP
Control
46
γ • AMP Adjust
20
to CLAMP
Control
DAC/Control
47
19
CLPPLS
0.1µ
GND
Clamp
pulse
6bit × 25
GAMR_B2G
GAMG_B2G
Input
I/F
48
I2C Bus
18
49
17
ROUT
47
PVCC
47µ/16V
15
52
14
15k
∗
8
9
10
11
12
13
GAMOFF
7
BLKLIM
6
PRGLEV
5
PRGPLS
4
SIDLEV
3
V33
2
POS_CNT2
POS_CNT1
1
DATEST
SDA
16
51
SIDOUT
I2C bus
(data)
PRG/SID
INV_CNT
SCL
DIR_CNT
I2C bus
(clock)
Output
I/F
50
DLY_CNT
GAMB_B2G
GOUT
47
0.1µ
PGND
BOUT
47
CXA2112R
15k
∗
1
2
49
13
52
39
42
48
CXA2112R
∗ When using two CXA2112R, connect the ICs directly
without inserting resistors.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 15 –
CXA2111R
Example of Representative Characteristics (Vcc = 5V, Ta = 25°C)
R/G/B gamma white gain
(I2C: standard setting)
R/G/B gamma black 1 gain
(I2C: standard setting)
9
10
8
9
8
7
6
Gain [times]
Gain [times]
7
5
4
6
5
4
3
3
2
2
1
1
0
1
2
3
4
5
Control pin voltage (Pins 42, 43 and 44) [V]
0
1
2
3
4
5
Control pin voltage (Pins 45, 46 and 47) [V]
R/G/B gamma white gain I2C characteristics
(Control pins = open)
R/G/B gamma black 2 gain
(I2C: standard setting)
8.0
25
7.5
20
Gain [times]
Gain [times]
7.0
15
10
6.5
6.0
5.5
5
5.0
0
4.5
0
1
2
3
4
5
Control pin voltage (pins 48, 49 and 50) [V]
00
9.5
21
9.0
20
8.5
19
8.0
18
7.5
7.0
10
20
18
28
I2C setting [HEX]
30
38
3F
R/G/B gamma black 2 gain I2C characteristics
(Control pins = open)
Gain [times]
Gain [times]
R/G/B gamma black 1 gain I2C characteristics
(Control pins = open)
08
17
16
6.5
15
6.0
14
5.5
13
00
08
10
18
28 30
20
I2C setting [HEX]
38
3F
00
– 16 –
08
10
18
28
20
I2C setting [HEX]
30
38
3F
CXA2111R
R/G/B amplifier gain I2C characteristics
(Control pins = open)
R/G/B amplifier gain
(I2C: Standard setting)
3.0
0.60
2.5
0.55
Gain [times]
Gain [times]
2.0
1.5
0.50
0.45
1.0
0.40
0.5
0
0.35
0
1
2
3
4
5
Control pin voltage (Pins 27, 28 and 29) [V]
00
R/G/B output black limiter voltage
08
10
18
20
28
I2C setting [HEX]
30
38
3F
R/G/B input clamp voltage characteristics
4.0
3.0
2.8
3.5
Clamp voltage [V]
Output voltage [V]
2.6
3.0
2.5
2.0
2.4
2.2
When Pin 25 =
open
2.0
1.8
1.5
1.6
1.0
1.4
1.0
1.5
2.0 2.5 3.0 3.5 4.0
Pin 12 (BLKLIM) voltage [V]
4.5
5.0
0
5
R/G/B frequency response
(Gamma OFF, amplifier gain = min.)
Pin 6 (SIDOUT) output
4.0
–7
3.5
–8
3.0
–9
Gain [dB]
Pin 6 voltage [V]
1
2
3
4
Pin 25 (CLPLEV) voltage [V]
2.5
–10
–11
2.0
–12
1.5
0
1
2
3
4
Control voltage (Pin 9/11) [V]
5
– 17 –
0.1
1
10
Frequency [MHz]
100
CXA2111R
Package Outline
Unit: mm
52PIN LQFP(PLASTIC)
+ 0.1
1.5 0
12.0 ± 0.2
∗ 10.0 ± 0.1
0.1
39
27
26
40
B
A
52
14
13
1
0.65
+ 0.08
0.32 – 0.07
0.13 M
0° to 10°
(0.3)
(0.125)
+ 0.04
0.145 – 0.025
+ 0.08
0.32 – 0.07
(0.5)
(11.0)
0.1 ± 0.1
0.6 ± 0.15
0.25
DETAIL A
DETAIL B
NOTE: Dimension “∗” does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
LQFP-52P-L01
LEAD TREATMENT
PALLADIUM PLATING
EIAJ CODE
LQFP052-P-1010
LEAD MATERIAL
COPPER ALLOY
PACKAGE MASS
0.3g
JEDEC CODE
– 18 –