CXA2112R LCD Driver For the availability of this product, please contact the sales office. Description The CXA2112R is a driver IC developed for use in the 6-input/12-input Sony polysilicon TFT LCD panel (LCX016/017). It has a line invert amplifier and analog de-multiplexers, timing generator and output buffers required for these. CXA2112R can directly drive analog inputs of LCX016/017. It is used one IC with the LCX016, and two ICs with the LCX017. The VCOM setting circuit and pre-charge pulse waveform generator are also on-chip. 64 pin LQFP (Plastic) Features • High-speed signal processing supports XGA high refresh signal (dot clock to 100MHz) • Overall wide band response • Low output deviation by on-chip output offset cancel circuit • Small phase delay difference between inverted signal and non-inverted signal • On-chip timing generator with ECL • Dot clock phase adjustment function • VCOM voltage generation circuit • Pre-charge pulse waveform generation circuit Absolute Maximum Ratings • Supply voltage • Supply voltage • Operating temperature • Storage temperature • Allowable power dissipation Operating Conditions • Supply voltage • Supply voltage VCC VDD PD 16 5.5 –20 to +70 –65 to +150 2300 VCC VDD 15 to 15.5 4.75 to 5.25 V V °C °C mW (single layered board mounted) V V Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E97801A81-PS CXA2112R OFFSET VIDEO_IN INV_OUT SH_IN FRP VCC SID_OFST D.P D.P SID_IN SID_OUT ISET NC SIGCEN VCOMOFST VCOMOUT Block Diagram 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 DLY_CNT 49 32 GND2 MCLK 50 INVERT AMP 31 SH_OUT1 MCLK/ 51 SID BIAS 30 NC VCOM INV_CNT 52 29 SH_OUT2 S/H VDD 53 S/H BUFFER 28 NC D OFFSET CANCEL CLOCK DELAY CLK_OUT 54 S/H 27 SH_OUT3 S/H S/H S/H BUFFER CLK_OUT/ 55 26 PVCC OFFSET CANCEL D.P 56 S/H S/H D.P 57 CLK_IN 59 S/H 24 D.P S/H S/H 23 PGND BUFFER 22 NC OFFSET CANCEL TIMING GENERATOR NC 60 25 D.P BUFFER OFFSET CANCEL S/H Pulses DGND 58 S/H S/H S/H CLK_IN/ 61 S/H BUFFER 21 SH_OUT4 OFFSET CANCEL PRG 62 S/H offset cancel mode timing S/H 20 NC S/H BUFFER 19 SH_OUT5 OFFSET CANCEL NC 63 18 NC NC 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 POS_CNT1 POS_CNT2 NEXT_OUT NEXT_IN F/R_CNT GND NC D.P D.P S/12_CNT NC ENB DIR_CNT NC NC NC 17 SH_OUT6 –2– CXA2112R Pin Description Pin No. Symbol 1 POS_CNT1 I/O Equivalent circuit Description VDD VDD I 2 Standard voltage level See Table A-1. 60k 1 2k 1.6V 20µ 2 Sample-and-hold position setting. See Tables A-1, A-2 and A-3. POS_CNT2 20µ 10µ VDD 3 NEXT_OUT O VDD 3 Approx. 4V Connect as closely as possible to NEXT_IN. 600µ VDD 0.7k VDD 4 NEXT_IN I Connect as closely as possible to NEXT_OUT. 4 16k 5 F/R_CNT I High: ≥ 2.5V Low: ≤ 0.8V OPEN High VDD VDD VDD VDD 10k 100k VDD 100k Before/after decision for 12-output. See Table B. 100k 6-output/12-output switch. High: 6-output Low: 12-output. See Table B. 10k 20k 10 S/12_CNT I High: ≥ 2.5V Low: ≤ 0.8V OPEN High 5 25µ 10 VDD VDD 150k VDD 50k 12 ENB I High: ≥ 2.5V Low: ≤ 0.8V 145 12 50k –3– Horizontal sync signal ENB input. Refer to Timing Chart. CXA2112R Pin No. Symbol I/O Standard voltage level Equivalent circuit Description VDD 13 DIR_CNT I High: ≥ 2.5V Low: ≤ 0.8V OPEN High 10k 100k VDD 100k VDD VDD VDD 10k Scan direction switch. High: forward scan Low: reverse scan 20k 13 25µ 100k 6 GND 17 SH_OUT6 19 SH_OUT5 21 SH_OUT4 27 SH_OUT3 29 SH_OUT2 31 SH_OUT1 GND Analog GND. PVCC PVCC 17 27 O 4k 19 29 2.5 to 11.5V 21 31 Output. 4k 2p 4k VCC VCC 70µ 33 VCOMOUT O 5 to 8V VCC 10µ VCC 500 80µ VCC 2k 34 40k 200k 1p 500 100k VCC 34 VCOMOFST I 0 to 10V 145 33 VCC 10k 35 SIGCEN I 7V 35 20µ –4– VCOM output. Can be set to VSIGCEN to VSIGCEN –2V by Pin 34 input. VSIGCEN: voltage set by Pin 35. VCOM output setting. Deviation from SIGCEN input is 0 for input setting of 0V. VCOM is set at the minus side from VSIGCEN at high voltage. Center voltage of signal inversion setting. Output signal is inverted, centered around this voltage, by FRP high/low. Normally, set to 7V. CXA2112R Pin No. Symbol I/O Standard voltage level Equivalent circuit VCC VCC 45µ 10µ VCC 37 ISET I Description 1.35V 2k 145 37 4p Vcc circuit bias current setting. Normally, connect 27kΩ (±1%) between this pin and GND. VCC 75k VCC SID signal waveform output. Connect to an external buffer for panel. 0.2p 38 SID_OUT O 2.5 to 11.5V 38 75k 0.2p 23 PGND GND Power GND. 26 PVCC 15.5V Power Vcc. Connect directly to Vcc. 32 GND2 GND Analog GND. VCC 19.5k 39 SID_IN I 2.3 to 3.3V 91k 7V VCC 39 SID signal input. 78k 19.5k VCC 42 SID_OFST I 30k 3.3V SID signal input offset setting. 42 10µ VDD VDD 44 FRP I VDD High: ≥ 2.5V Low: ≤ 0.8V 100k 50k 10k 44 50k –5– Invert pulse input. High: inverse Low: non-inverse Refer to Timing Chart. CXA2112R Pin No. Symbol I/O Standard voltage level Equivalent circuit VCC 45 SH_IN I 2.5 to 11.5V Description 1.9k Sample-and-hold circuit common input. Should not be less than 2V. 45 200 VCC VCC VCC 560µ VCC 46 INV_OUT O 2.5 to 11.5V Invert amplifier output. 46 620µ VCC VCC 300µ 47 VIDEO_IN I 2.0 to 3.3V Invert amplifier input. 145 47 VCC 30k 48 OFFSET I 3.3V 48 10µ Video signal input offset setting. Inputs 100% white level. VDD VDD 2k 49 49 DLY_CNT I 3 to 5V Dot clock phase adjustment. 50µ 43 VCC 15V power supply. 15.5V –6– CXA2112R Pin No. Symbol I/O Standard voltage level Equivalent circuit Description VDD 50 MCLK VDD 20k I PECL differential 1k Dot clock input. 100µ VDD 51 10µ 50 20k MCLK/ 51 1k VDD VDD 52 INV_CNT I High: ≥ 2.5V Low: ≤ 0.8V 10µ Dot clock phase invert control. 2k 52 VDD 54 CLK_OUT I 55 VDD – 0.3V to VDD Phase adjusted dot clock output. 54 55 CLK_OUT/ 1m VDD VDD VDD 59 VDD CLK_IN 2k 2k 145 I 59 VDD – 0.3V to VDD 61 CLK_IN/ On-chip timing generator clock input. Connect directly to Pins 54 and 55. 100µ VDD 145 I 61 VDD VDD VDD 62 PRG I High: ≥ 2.5V Low: ≤ 0.8V 150k 50k 145 62 50k –7– Horizontal sync signal PRG input. Refer to Timing Chart. CXA2112R Pin No. Symbol 53 VDD 58 DGND 8, 9, 24, 25, D.P 40, 41, 56, 57 I/O Standard voltage level Equivalent circuit 5V Description 5V power supply. Digital GND. Die pad. Used as thermal radiator on board. Connect to GND. GND 7, 11, 14, 15, 16, 18, 20, 22, NC 28, 30, 36, 60, 63, 64 No connection. Not connected to anything. –8– CXA2112R Electrical Characteristics (See Electrical Characteristics Measurement Circuit.) VDD = 5V, VCC = 15.5V, VSIGCEN = 7V, Ta = 25°C Item No. Symbol Measurement points Measurement contents Min. Typ. Max. Unit 1 VDD current consumption IDD IVDD IDD = IVDD 22 32 42 mA 2 Vcc current consumption ICC IVCC1 IVCC2 ICC = IVCC1 + IVCC2 30 41 52 mA 3 Invert amplifier gain AINV VINV VIN AINV = VINV (AC)/VIN — 2.7 — times VINV Input a square wave from VIN so that VINV output amplitude is 3.5Vp-p. Measure slew rate at 10 to 90% of output waveform rise or fall. (for inverse or non-inverse) — 700 — V/µs — 90 — MHz 4 Invert amplifier slew rate 5 Invert amplifier output band width BWINV VINV Input 2.5V DC, 100mVp-p AC from Pin 47 (VIDEO_IN) and measure VINV. The frequency that is –3dB to 100kHz. (for inverse/ non-inverse) 6 Output delay deviation for inverse/non-inverse TDIFF VINV Invert amplifier delay time difference for inverse and noninverse. — 2 4 ns 7 SID gain ASID VSID VSID_IN ASID = VSID (AC)/VSID_IN — 4 — times — 30 — V/µs Vsig – 2 or less — Vsig V SRINV 8 SID output slew rate SRSID VSID Input invert pulse to Pin 44 (FRP), load capacity C7 = 47pF, and apply DC input voltage to VSID_IN so that VSID is 2.5V/11.5V. Measure slew rate at 10 to 90% of output waveform rise or fall. 9 VCOM adjustable range VCOM VCOM VCOM output voltage when Pin 34 (VCOMOFST) is changed from 0 to 10V. 10 Farst stage S/H slew rate SRSH1 — First stage S/H slew rate on Block Diagram. — 700 — V/µs — 150 — V/µs — 3 10 mVp-p 100 115 11 SH_OUT slew rate SROUT VOUT1 to VOUT6 Input a square wave from VIN so that VOUT1 to VOUT6 output amplitude is 3.5Vp-p. Measure slew rate at 10 to 90% of output waveform rise or fall. (load 270pF, for inverse or non-inverse) 12 Output deviation between channels ∗ DOUT VOUT1 to VOUT6 Apply DC voltage to VIN so that VINV (SH_IN) is 6V. 13 Dot clock input highest frequency fCLKH fCLK Highest frequency for fCLK output at correct timing. 14 Dot clock input lowest frequency fCLKL fCLK Lowest frequency for fCLK output at correct timing. 15 Maximum output voltage VMAX VOUT1 to VOUT6 Maximum voltage at which sample-and-hold output (SH_OUT1 to SH_OUT6) can be output. 16 Minimum output voltage VMIN VOUT1 to VOUT6 Minimum voltage at which sample-and-hold output (SH_OUT1 to SH_OUT6) can be output. –9– 12 13 MHz 20 V 13.5 2 MHz 2.5 V CXA2112R ∗ Minimum VOUT1 to VOUT6 value subtracted from maximum VOUT1 to VOUT6 value. Unless otherwise specified, pin setting conditions are as follows. (48) OFFSET = 3.3V, (47) VIDEO_IN = 2.0V, (42) SID_OFST = 3.3V, (39) SID_IN = 2.3V, (35) SIGCEN = 7.0V, (34) VCOMOFST = 0.0V, (1) POS_CNT1 = 0.0V, (2) POS_CNT2 = 0.0V, (5) F/R_CNT = 5.0V, (10) S/12_CNT = 5.0V, (13) DIR_CNT = 5.0V, (49) DLY_CNT = 4.0V, (52) INV_CNT = 5.0V, (44) FRP = 0.0V, fCLK = 65MHz – 10 – CXA2112R Electrical Characteristics Measurement Circuit VCC VSID_IN 2.3V 20k VCC VINV 20k VCC 48 DLY_CNT P MCLK N MCLK/ INV_CNT VDD CLK_OUT CLK_OUT/ D.P D.P DGND CLK_IN NC 43 42 41 40 35 34 VCOMOUT VCOMOFST SIGCEN ISET NC 36 33 31 51 SID BIAS 30 VCOM 52 29 S/H 53 S/H S/H BUFFER 28 D OFFSET CANCEL CLOCK DELAY 54 27 S/H S/H S/H BUFFER 55 26 OFFSET CANCEL 56 S/H S/H 57 S/H Pulses 58 59 S/H 25 BUFFER 24 S/H S/H 23 BUFFER 22 OFFSET CANCEL TIMING GENERATOR 60 S/H OFFSET CANCEL S/H S/H S/H BUFFER 21 OFFSET CANCEL 61 NC 37 38 39 INVERT AMP 50 CLK_IN/ PRG SID_OUT D.P SID_IN VCC 44 D.P SID_OFST FRP SH_IN 45 VCOM 32 62 S/H offset cancel mode timing S/H 20 S/H BUFFER 19 OFFSET CANCEL 63 18 NC 64 17 VDD 15 GND2 SH_OUT1 VOUT1 NC C1 270pF SH_OUT2 VOUT2 NC C2 270pF SH_OUT3 PVCC VOUT3 IVCC2 VCC D.P C3 270pF D.P PGND NC SH_OUT4 VOUT4 NC C4 270pF SH_OUT5 VOUT5 NC C5 270pF SH_OUT6 VOUT6 C6 270pF 16 NC 14 NC 13 NC 12 DIR_CNT 11 ENB 10 NC D.P D.P NC GND 9 8 7 S/12_CNT 6 5 4 3 F/R_CNT 2 NEXT_IN 1 POS_CNT2 VDD 46 NEXT_OUT SW4 47 IVCC1 49 POS_CNT1 VDD INV_OUT OFFSET VIDEO_IN C7 2V Frequency fCLK VSID 3.3V VIN DIFF BUFFER2 27k 3.3V VDD VDD SW1 SW3 VCC VDD SW2 15.5V – 11 – 5V CXA2112R Description of Operation 1. INVERT_AMP The VIDEO signal from VIDEO_IN (Pin 47) is amplified about 2.7 times at INVERT_AMP. Its output is INV_OUT (Pin 46). Status of INVERT_AMP is determined by FRP (Pin 44) input (high: inverse, low: noninverse). Invert operation is carried out with SIGCEN (Pin 35) potential as center voltage of signal inversion. OFFSET (Pin 48) input voltage corresponds to 100% white level of the signal input to VIDEO_IN. When used in combination with the CXA2111R, connect the CXA2111R V33 (Pin 8) output to the CXA2112R OFFSET. When use DA converter output as the VIDEO signal, connect DA converter maximum output voltage (normally, DA converter's supply voltage). OFFSET level VIDEO IN VIN FRP Output level when input is up to OFFSET level approx. 2.7 × VIN approx. 1V INV_OUT SIGCEN potential approx. 1V 2. SID The signal input to SID_IN (Pin 39) is folded by SIGCEN potential, the same as for INVERT_AMP operation, and outputs to SID_OUT (Pin 38). Gain is about 4 times. SID_OFST (Pin 42) operates in the same way as OFFSET input for INVERT_AMP. In combination with the CXA2111R, connect the CXA2111R SID_OUT (Pin 6) to the CXA2112R SID_IN, and CXA2111R V33 (Pin 8) to the CXA2112R SID_OFST. – 12 – CXA2112R SID_OFST level SID IN VSID_IN FRP Output level when input is up to SID_OFST level approx. 4 × VSID_IN approx. 1V approx. 1V SIGCEN potential The SID output is prepared for the Sony LCD panel's (LCX017 and LCX016) uniformity improvement signal input (Psig input). SID_OUT does not have the capability to drive those pins directly. Connect via a buffer. 3. VCOM VCOM generates the DC voltage applied to the Sony LCD panel COM electrode. VCOMOUT (Pin 33) voltage is set as the deviation relative to SIGCEN voltage. When VCOMOFST (Pin 34) is changed from 0 to 10V, VCOMOUT changes from (SIGCEN potential) to (SIGCEN potential) – 2V. – 13 – CXA2112R 4. De-Multiplexer SH_IN (Pin 45) input is de-multiplexed in order from SH_OUT1 (Pin 31) to SH_OUT6 (Pin 17) according to internal timing generator setting, and then is output. Output phase is made simultaneous by the 3-stage sample-and-hold circuit. The waveform example below shows this operation for forward scan, 6-output de-multiplexing. A D G C K F H J SH_IN B E I L CLK_IN 1 2 3 4 5 6 7 8 9 10 11 12 A 13 14 15 G SH_OUT1 0V H SH_OUT2 B 0V C SH_OUT3 I 0V D J SH_OUT4 0V K SH_OUT5 E 0V F SH_OUT6 L 0V Depending on the operation mode setting, scan direction (SH_OUT1 → SH_OUT6 and SH_OUT6 → SH_OUT1), number of outputs (6-output/12-output) and sample-and-hold position (output phase) can be changed. – 14 – CXA2112R 5. Operation Mode Setting 1) For each RGB channel, LCX016 requires demultiplexed 6 analog outputs (one CXA2112R), and LCX017 needs 12 (two CXA2112R). In either case, scan direction switching, sample-and-hold position and phase can be controlled. The mode input pin settings for each case are shown below. Fixed Mode Setting LCX016 6-outputs S/12_CNT (Pin 10) F/R_CNT (Pin 5) NEXT_IN (Pin 4) NEXT_OUT (Pin 3) LCX017 "FRONT" half of 12 outputs∗2 "REAR" half of 12 outputs∗2 Low Low High Low High X∗1 Short ∗2 "FRONT": input data sampling begins from "FRONT" chip for forward scan direction (DIR_CNT high). Connect to the other NEXT_OUT Connect to the other NEXT_IN Table B ∗1 X: Don't Care 2) Scan direction switching DIR_CNT (Pin 13) high gives forward scan, and low gives reverse scan. For forward scan, the input signal level time series is output in descending order from SH_OUT1, and for reverse scan, in descending order from SH_OUT6. For 12-output, SH_OUT6 and SH_OUT1 operated as if connected in order. 3) Sample-and-hold position setting Output's phase can be changed by the voltage applied to POS_CNT1 (Pin 1) and POS_CNT2 (Pin 2). This setting is done for adjustment of the LCD panel input signal timing. Each input pin has 4 setting values, for a total of 16 settings. POS_CNT1 is lower, POS_CNT2 is upper, and each setting values are as shown in Table A-1. Setting Voltage Range for Sample-and-Hold Position Setting value Threshold 0 GND to 0.75V 1 1.15 to 1.50V 2 1.70 to 2.55V 3 2.95 to VDD Table A-1 – 15 – CXA2112R There are two ways to use these pins. A. Connect directly to the CXA2111R. Connect to the corresponding CXA2111R pins POS_CNT1 and POS_CNT2. This allows bit setting via the CXA2111R register controlled by I2C bus. B. Connect to CMOS logic. Connect CMOS logic as shown in the diagram. See Table A-2. CMOS Logic Connection Setting Value and CMOS Output Pins Setting value a CXA2112R b a 0 L L 1 Hi-Z L 2 Hi-Z H 3 H H Supply voltage C M VMOS O S b R1 1 POS_CNT1 (2) (POS_CNT2) Table A-2 R1 sets the level for setting values 1 and 2. The appropriate resistance value changes depending on numbers of CXA2112R are driven by one CMOS logic (1-channel or RGB 3-channel drive, or one CXA2112R (6outputs/ch) or two CXA2112R (12-outputs/ch)). Recommended resistance values are given in Table A-3. CMOS Logic Connection Usage of CXA2112R and Threshold Setting Resistor R1 RGB 1-channel drive RGB 3-channel drive 6-outputs 12-outputs 6-outputs 12-outputs R1 value 270kΩ 150kΩ Table A-3 100kΩ 47kΩ VMOS = 3.3 to 5V – 16 – CXA2112R 6. Dot Clock Phase Adjustment The CXA2112R has phase adjustment function for input dot clock to achieve high precision and stable operation. High definition images with no jitter and flicker can be reproduced by this adjustment. De-multiplexer operation timing is generated from the clock input to CLK_IN (Pin 59) and CLK_IN/ (Pin 61) (ECL differential). By connecting CLK_OUT (Pin 54) and CLK_OUT/ (Pin 55) to CLK IN/, phase adjusted clock can be used for its timing generation. The CLOCK DELAY block is a PLL clock generator that uses MCLK (Pin 50) and MCLK/ (Pin 51) ECL differential input clock as reference. The CLK_OUT polarity, inverted/non-inverted can be switched by high/low of INV_CNT (Pin 52) input. Also, in the DLY_CNT (Pin 49) input voltage range of 3 to 5V, CLK_OUT phase relative to MCLK can be changed continuously 180deg. (PHDLY in the diagram below.) It also has the advantage that an MCLK with noise can be shaped and used on the board. MCLK PHDLY CLK_OUT SH_IN 7. Usage of CXA2112R in 12-outputs Two CXA2112Rs are required for 12-outputs, as shown in Application Circuit 2. Please note that the following precautions. • Input the same clock to both ICs' timing generator clock input pins CLK_IN and CLK_IN/. To be concrete, connect one CLK_OUT and CLK_OUT/ to both ICs' CLK_IN and CLK_IN/. At this time, the other CLK_OUT and CLK_OUT/ are not used, but be sure to input the same clock to MCLK and MCLK/ inputs. • Connect both ICs' SH_INs to only one ICs' INV_OUT. At that time, connect the other ICs' VIDEO_IN and OFFSET to 5V. In the same way, connect the other ICs' SID_IN and SID_OFST to 5V. • When only one IC is used for all of INVET_AMP, SID and VCOM, the FRP input on the other IC does not have to be at the timing in the above paragraph, but can be connected to GND. • Short ENB, PRG, POS_CNT1, POS_CNT2, DIR_CNT, INV_CNT and DLY_CNT at both ICs, and apply the same signals. – 17 – CXA2112R Notes on Operation 1. Signal input timings to the timing generator Input Signal Timing Chart 30CLK or more ENB PRG 60CLK or more 4CLK or more FRP 0 to 5CLK Maintain the relationship in the timing chart. While PRG is high, video input signal must not be changed. The same name output from Sony's LCD timing generators CXD2442Q and CXD2453Q satisfy the above conditions. If the above timing does not be satisfied, timing violation may cause decay of characteristics or IC damage in some case. Especially do not input FRP pulse without ENB and PRG input. We strongly recommend to verify the design on this timings and presence of ENB and PRG. 2. Notes on Mounting • Please be sure that the wiring for internal timing generator link pins NEXT_IN (Pin 4) and NEXT_OUT (Pin 3) is as short as possible, in especially 12-outputs. Also, do not locate a large amplitude high-speed signal path (such as CMOS logic) near the wiring. • The eight pins 8, 9, 24, 25, 40, 41, 56 and 57 are connected to the "die pad" inside the package. A good thermal radiation effect can be achieved by a thick connection to GND plane. • Be sure to short PVcc (Pin 26) and Vcc (Pin 43) so that they go on and off simultaneously. 3. Input Video Signal • Please be sure that the video signal amplitude (0% black level to 100% white level) which inputs to sample and hold (SH_IN (Pin 45)) does not exceed 3.5VPP. Also, as for inputting to sample and hold, do not apply DC level of 2V or lower during operation. – 18 – CXA2112R Application Circuit 1 BUFFER VCC 47µ 0.1µ 3.3k 3.3 3.3 100 VCC 1 3.3k 5.1k 10k 0.1µ VCC 5.1k 20k 0.1µ 48 47 46 43 44 41 40 36 VCOMOFST 35 34 VCOMOUT NC 37 38 SIGCEN SID_OUT 39 27k ISET D.P SID_IN SID_OFST 42 D.P FRP 45 VCC INV_OUT SH_IN OFFSET CLK H 32 CXA3106Q VIDEO_IN 0.1µ 33 CLK L 31 DLY_CNT MCLK SID_OUT 6 MCLK/ V33 8 INV_CNT VDD R_OUT 18 CLK_OUT G_OUT 16 CLK_OUT/ B_OUT 14 CXA2111R D.P VDD DLY_CNT 3 INV_CNT 5 D.P 10µ DGND 0.1µ CLK_IN POS_CNT1 1 POS_CNT2 2 NC 32 49 INVERT AMP 50 31 51 SID BIAS 4 29 S/H 53 S/H NC BUFFER OFFSET CANCEL CLOCK DELAY 54 S/H 28 D 27 S/H S/H S/H BUFFER 55 26 OFFSET CANCEL 56 S/H S/H 57 S/H Pulses 58 59 S/H 25 BUFFER 24 S/H S/H 23 BUFFER 22 OFFSET CANCEL TIMING GENERATOR 60 S/H OFFSET CANCEL S/H S/H CLK_IN/ PRG VCOM 52 S/H BUFFER 21 OFFSET CANCEL 61 DIR_CNT 30 62 S/H offset cancel mode timing S/H 20 S/H BUFFER 19 OFFSET CANCEL 63 18 NC Open or High (5V) 15 NC 14 SH_OUT1 NC SH_OUT2 NC 1 PSIG SH_OUT3 PVCC 24 COM VCC D.P 7 SIG1 D.P 0.1µ 10µ PGND 5 SIG2 NC 3 SIG3 SH_OUT4 2 SIG4 NC 4 SIG5 SH_OUT5 6 SIG6 NC SH_OUT6 16 NC 13 NC 12 DIR_CNT 11 NC D.P Open or High (5V) 10 ENB 9 8 S/12_CNT NC 7 D.P 6 GND 5 4 3 F/R_CNT 2 NEXT_IN ENB 60 1 NEXT_OUT PRG 29 17 POS_CNT1 CXD2442Q 64 POS_CNT2 FRP 30 GND2 VCC VDD 15.5V 5V Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 19 – LCX016 LCD panel CXA2112R VCC Application Circuit 2 20k VCC 20k BUFFER SID_OUT 6 R_OUT 18 48 DLY_CNT DLY_CNT 3 MCLK CXA2111R V33 8 MCLK/ INV_CNT INV_CNT 5 VDD 4 VDD CLK_OUT CLK_OUT/ POS_CNT2 2 D.P POS_CNT1 1 D.P DGND CLK_IN NC 46 43 44 42 40 36 35 34 33 32 31 51 SID BIAS 30 VCOM 52 29 S/H 53 S/H BUFFER 28 D OFFSET CANCEL CLOCK DELAY 54 S/H 27 S/H S/H S/H BUFFER 55 26 OFFSET CANCEL 56 S/H S/H 57 59 S/H S/H 24 S/H 23 BUFFER 22 OFFSET CANCEL TIMING GENERATOR 60 25 BUFFER OFFSET CANCEL S/H Pulses 58 S/H S/H S/H S/H BUFFER 21 OFFSET CANCEL 62 S/H offset cancel mode timing S/H 20 S/H BUFFER 19 OFFSET CANCEL 63 18 NC 64 15 GND2 SH_OUT1 3 VSIG1 4 VSIG2 5 VSIG3 6 VSIG4 7 VSIG5 8 VSIG6 NC SH_OUT2 NC SH_OUT3 PVCC VCC D.P D.P PGND NC SH_OUT4 NC SH_OUT5 NC SH_OUT6 16 NC NC ENB 14 NC 13 12 11 DIR_CNT D.P 10 NC NC D.P GND 9 8 7 S/12_CNT 6 5 4 3 F/R_CNT POS_CNT1 ENB 47 2 NEXT_IN 1 PRG 48 POS_CNT2 CXD2453Q 17 NEXT_OUT FRP 45 PSIG 31 COM VCOMOUT SIGCEN ISET NC 37 38 INVERT AMP 61 NC 39 27k 49 50 CLK_IN/ PRG SID_IN D.P 41 SID_OUT SID_OFST D.P FRP 45 VCC INV_OUT 47 SH_IN OFFSET G_OUT 16 DIR_CNT VIDEO_IN B_OUT 14 VCOMOFST 1 VCC VDD 1 60 NC NC NC ENB DIR_CNT NC S/12_CNT D.P NC D.P F/R_CNT GND S/H TIMING GENERATOR 59 S/H S/H Pulses 58 S/H S/H 21 BUFFER OFFSET CANCEL S/H 22 S/H BUFFER 23 OFFSET CANCEL 57 S/H 56 S/H 24 S/H BUFFER 25 OFFSET CANCEL 26 55 S/H CLOCK DELAY 54 S/H BUFFER 27 OFFSET CANCEL D 53 S/H 28 S/H S/H S/H BUFFER 29 52 SID 51 BIAS VCOM 30 INVERT AMP 50 31 32 49 47 46 45 44 43 42 41 40 39 VDD 37 36 27k VCC VDD 38 VDD 35 34 SH_OUT6 14 VSIG12 NC SH_OUT5 13 VSIG11 NC SH_OUT4 12 VSIG10 NC PGND D.P D.P PVCC VCC SH_OUT3 11 VSIG9 NC SH_OUT2 10 VSIG8 NC SH_OUT1 9 VSIG7 GND2 33 VCOMOUT OFFSET 48 SIGCEN MCLK DLY_CNT 19 20 VCOMOFST MCLK/ 16 BUFFER NC INV_CNT 15 18 S/H ISET VDD S/H SID_OUT VDD 14 OFFSET CANCEL D.P CLK_OUT S/H 61 SID_IN CLK_OUT/ offset cancel mode timing 62 D.P D.P 13 12 11 OFFSET CANCEL SID_OFST D.P 63 VCC DGND 10 17 FRP NC CLK_IN 9 8 7 64 SH_IN PRG CLK_IN/ 6 5 4 3 INV_OUT NC 2 VIDEO_IN NC NEXT_IN CLK L 31 NEXT_OUT CLK H 32 CXA3106Q POS_CNT2 POS_CNT1 LCX017 VDD VCC VDD 15.5V 5V Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 20 – CXA2112R Example of Representative Characteristics (VCC = 15.5V, VDD = 5.0V, SIGCEN = 7.0V, Ta = 25°C) CLK_OUT phase to MCLK vs. DLY_CNT voltage (1) CLK_OUT phase to MCLK vs. DLY_CNT voltage (2) 180 180 Phase [deg] 120 INV_CNT = High 60 INV_CNT = Low 0 –60 INV_CNT = High –120 fCLK = 100MHz 120 Phase [deg] fCLK = 20MHz 60 INV_CNT = Low 0 INV_CNT = High –60 –120 INV_CNT = Low –180 2.5 –180 3 3.5 4 4.5 DLY_CNT (Pin 49) voltage [V] 5 2.5 SID_OUT voltage vs. SID_OFST voltage (1) SID_OUT voltage vs. SID_OFST voltage (2) SID_IN = 2.300V 14 SID_OUT (Pin 38) voltage [V] SID_OUT (Pin 38) voltage [V] 5 12 16 12 FRP = High 10 8 6 4 FRP = Low 2 SID_IN = 4.000V 10 FRP = High 8 6 4 FRP = Low 2 0 0 0 1 2 3 4 SID_OFST (Pin 42) voltage [V] 0 5 1 2 3 4 SID_OFST (Pin 42) voltage [V] 5 SID_OUT voltage vs. SID_IN voltage (2) SID_OUT voltage vs. SID_IN voltage (1) 16 16 SID_OFST = 3.300V 14 SID_OUT (Pin 38) voltage [V] SID_OUT (Pin 38) voltage [V] 3 3.5 4 4.5 DLY_CNT (Pin 49) voltage [V] 12 FRP = High 10 8 6 FRP = Low 4 2 14 SID_OFST = 5.000V 12 FRP = High 10 8 6 4 FRP = Low 2 0 0 0 1 2 3 4 SID_IN (Pin 39) voltage [V] 0 5 – 21 – 1 2 3 4 SID_IN (Pin 39) voltage [V] 5 CXA2112R INV_OUT voltage vs. OFFSET voltage (1) INV_OUT voltage vs. OFFSET voltage (2) 14 VIDEO_IN = 1.800V INV_OUT (Pin 46) voltage [V] INV_OUT (Pin 46) voltage [V] 14 12 FRP = High 10 8 6 4 FRP = Low 2 0 1 2 3 4 OFFSET (Pin48) voltage [V] 8 6 4 FRP = Low 2 5 0 INV_OUT voltage vs. VIDEO_IN voltage (1) 1 2 3 4 OFFSET (Pin48) voltage [V] 5 INV_OUT voltage vs. VIDEO_IN voltage (2) 14 14 OFFSET = 3.300V INV_OUT (Pin 46) voltage [V] INV_OUT (Pin 46) voltage [V] FRP = High 10 0 0 12 FRP = High 10 8 6 4 FRP = Low 2 0 OFFSET =5.000V 12 FRP = High 10 8 6 4 FRP = Low 2 0 0 1 2 3 4 VIDEO_IN (Pin 47) voltage [V] 5 0 VCOMOUT voltage vs. VCOMOFST voltage 8 VCOMOUT (Pin 33) voltage [V] VIDEO_IN = 3.500V 12 7 6 5 4 3 2 1 0 0 2 4 6 12 14 8 10 VCOMOFST (Pin 34) voltage [V] – 22 – 1 2 3 4 VIDEO_IN (Pin 47) voltage [V] 5 CXA2112R Package Outline Unit: mm 64PIN LQFP (PLASTIC) 16.0 ± 0.2 ∗ 1.7MAX 14.0 ± 0.1 0.1 33 48 32 (15.0) 49 B A 17 64 16 + 0.08 0.37 – 0.07 (0.5) 1 0.8 0.13 M 0.25 (0.5) 0° to 10° 0.6 ± 0.2 (0.35) DETAIL A (0.125) + 0.08 0.37 – 0.07 0.145 ± 0.04 0.1 ± 0.1 DETAIL B NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE LQFP-64P-L02 LEAD TREATMENT EIAJ CODE LQFP064-P-1414 LEAD MATERIAL COPPER ALLOY PACKAGE MASS 0.7g JEDEC CODE PALLADIUM PLATING NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). – 23 –