SONY CXA2550M/N

CXA2550M/N
RF Amplifier for CD Players
Description
The CXA2550M/N is an IC developed for compact
disc players. This IC incorporates an RF amplifier,
focus error amplifier, tracking error amplifier, APC
circuit and RF level control circuit. (The voltageconverted optical pickup output is supported.)
CXA2550M
20 pin SOP (Plastic)
Features
• Low power consumption (35mW at 3.5V)
• APC circuit
• RF level control circuit
• Both single power supply and dual power supply
operations possible.
CXA2550N
20 pin SSOP (Plastic)
Absolute Maximum Ratings (Ta = 25°C)
12
V
• Supply voltage
VCC
• Operating temperature Topr
–20 to +75
°C
• Storage temperature
Tstg
–65 to +150
°C
• Allowable power dissipation
PD (SOP) 620
mW
(SSOP) 370
mW
Structure
Bipolar silicon monolithic IC
Applications
Compact disc players
Operating Conditions
Supply voltage
VCC – VEE
3.0 to 4.0
V
11 TE
12 FE_BIAS
TRACKING
ERROR
VC AMP
7
8
9
F
E
EI
15k
VC 10
6
VEE
VC
49
VC
5
PD2
VC
VEE
96k
30k
30k
30k
95k
26k
12p
VC
260k
12p
VC
13k
VCC
24p
VC
87k
32k
2k
32k
13k
VEE
VC
260k
30k
24p
154k
FOCUS
ERROR
AMP
174k
13 FE
14 RFM
15 RF O
VEE
25k
8k 6p
10k
4
PD1
VC VC
8k 6p
2k
3
PD
VC
2
LD
10k
2k
VEE
VREF 1.25V
VC
2k
VC
6k
54k
VC
15k
16 RF I
17 RFTC
13.4k
50µA
670mV
10k
56k
10k
10k
55k
10k
VEE
1
AGCVTH
APC PD AMP
VCC
1k
56k APC LD
AMP
VCC
VCC
20 VCC
19 LD_ON
18 AGCCONT
(50%/30%/OFF)
Block Diagram and Pin Configuration (Top View)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E97514B25
CXA2550M/N
Pin Description
Pin
No.
Symbol
I/O
Description
Equivalent circuit
50µ
Reference level variable pin for RF
level control.
The reference level can be varied by
the external resistor.
147
1
AGCVTH
—
1
13.4k
10µ
10k
2
LD
O
APC amplifier output pin.
2
1k
20µ
8µ
3
PD
I
55k
147
3
APC amplifier input pin.
10k
10k
4
5
6
PD1
PD2
VEE
I
I
—
100µ
Inversion input pin for RF I-V
amplifiers.
Connect these pins to the
photodiodes A + C and B + D
respectively. The current is supplied.
VEE
VEE pin.
4
5
6
–2–
CXA2550M/N
Pin
No.
Symbol
I/O
Description
Equivalent circuit
12p
260k
7
8
F
E
I
I
Inversion input pin for F and E I-V
amplifiers.
Connect these pins to the
photodiodes F and E respectively.
The current is supplied.
7
8
10µ
13k
26k
9
EI
147
—
260k
Gain adjustment pin for I-V amplifier.
9
VCC
VCC
200µ
10
VC
50
O
120
15k
10
120
16k
DC voltage output pin of
(Vcc + VEE)/2.
Connect to GND for ±1.75 power
supply; connect a smoothing
capacitor for single +3.5V power
supply.
VEE
11
TE
O
11
96k
300µ
–3–
Tracking error amplifier output pin.
E-F signal is output.
CXA2550M/N
Pin
No.
Symbol
I/O
Description
Equivalent circuit
32k
164k
12
12
FE_BIAS
I
24p
Bias adjustment pin for inverted side
of focus error amplifier.
174k
10µ
24p
13
FE
O
Focus error amplifier output pin.
13
174k
300µ
2k
2k
147
14
RFM
I
14
850
RF amplifier inverted side input pin.
RF amplifier gain is determined by
the resistor connected between this
pin and RFO pin.
1m
15
RF O
O
147
RF amplifier output pin.
15
60k
1m
–4–
CXA2550M/N
Pin
No.
Symbol
I/O
Description
Equivalent circuit
147
16
16
RF I
I
The RF amplifier output RFO is input
with its capacitance coupled.
15k
20µ
17
RFTC
—
147
50µ
External time-constant pin for RF
level control.
17
50µ
10µ
15µ
15µ
RF level control ON (limit level of
50%/30%)/OFF switching pin.
OFF for Vcc, 30% for open or Vc
and 50% for VEE.
147
18
AGCCONT
I
18
50k
7µ
50µ
147
19
LD_ON
I
19
VREF
20
VCC
20
VCC
–5–
APC amplifier ON/OFF switching
pin.
OFF for Vcc and ON for VEE.
Vcc pin.
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
O
5
O
6
7
V15-4
V15-5
V13-1
V13-2
Maximum output
amplitude H
Maximum output
amplitude L
Offset voltage
Voltage gain 1
V2-5
0.8mA
V2-2
Output voltage 2
Maximum output
amplitude
V2-1
Output voltage 1
O O
0µA
1V
1V
2.7V
2.7V
V11-6
Maximum output
amplitude L
O
0µA
V11-5
Maximum output
amplitude H
V2-3
2.7V
570µA
V11-4
Voltage gain
difference
Output voltage 3
2.7V
450µA
V11-3
Voltage gain 2
O
V11-2
Voltage gain 1
300mV
V11-1
O
Offset voltage 1
E3
V13-6
300mV
E2
Maximum output
amplitude H
O
–300mV
300mV
E1
V13-5
I2
Maximum output
amplitude L
O
O
O
I1
V13-4
O
O
O O
O O
8
Bias conditions
Voltage gain
difference
V13-3
V15-3
Frequency
response
V15-1
O
O
4
IEE
O
3
O O
2
O
V15-2
Voltage gain 2
1
SW conditions
ICC
Voltage gain
Offset voltage 1
Current
consumption
RF amplifier
FE amplifier
TE amplifier
–6–
APC
1
No. Measurement item Symbol
Electrical Characteristics
2.0V
0.5V
2.0V
2.0V
E4
Measurement pin
—
–120.0
16.4
Output DC
measurement
Output DC
measurement
Output AC
measurement
15
13 Input resistance 33kΩ
13 Input 1kHz 120mVp-p
7.3
7.3
Output AC
measurement
Output AC
measurement
11 Input 1kHz 240mVp-p
11 Input 1kHz 240mVp-p
2
2 LD OFF
2
2
11
11
11
1400 1590
–600
Output DC
measurement
Output DC
measurement
—
970
470
Output DC
measurement
—
–830 –330
—
Output DC
measurement
—
0
10.3
10.3
0
—
—
0
19.4
19.4
0
—
—
—
19.7
–10
Output DC
measurement
1.25
Output DC
measurement
–3.0
–50
Output DC
measurement
11 Input resistance 390kΩ
V11-4 = V11-2 –
V11-3
1.25
13
13
Output DC
measurement
–3.0
—
V13-4 = V13-2 –
V13-3
Output DC
measurement
13
13 Input 1kHz 120mVp-p
16.4
1.45
Output DC
measurement
15
Output AC
measurement
–3
15 Input 3MHz 120mVpp
Output AC
measurement
–50.0
16.7
Output DC
measurement
9.8
Typ.
13.23 mA
Max. Unit
V
V
dB
dB
mV
100
—
1470
170
–1.25
—
3.0
13.3
13.3
50
—
–1.25
3.0
22.4
22.4
mV
mV
mV
mV
V
V
dB
dB
dB
mV
V
V
dB
dB
dB
120.0 mV
–1.25
—
—
22.7
60.0
–13.23 –9.8 –6.37 mA
6.37
Min.
Output AC
measurement
15 Input 1kHz 120mVp-p
15 Input resistance 33kΩ
6 Input GND
20 Input GND
Description of I/O waveform
and measurement method
(Ta = 25°C, VCC = 1.75V, VEE = –1.75V, VC = GND)
CXA2550M/N
V2-10
–30% limit
30
29
V18-1
V18-2
V18-3
High Level
Middle Level
Low Level
Center output voltage V10-1
V2-9
–50% limit
31
V2-8
V2-7
30% limit
50% limit
28
27
26
25
24
AGCCONT
RF level control
No. Measurement item Symbol
1
3
O O
O O
2
4
5
O
O
6
SW conditions
O
7
O
O
8
I1
E1
320µA
230µA
700µA 50mV
800µA 50mV
I2
800mV
800mV
E2
Bias conditions
2.0V
2.0V
2.0V
0.5V/
2.7V
2.2V/
2.7V
2.0V
0.5V/
2.7V
1.3V/
2.7V
E4
E3
Measurement pin
—
—
—
—
1.3
–100
—
100
0.5
2.2
—
1204 1700
2.7
700
Level control:
–30% – Level control OFF
1471 1900
mV
V
V
V
mV
mV
mV
mV
Max. Unit
–1700 –1163 –200
700
Output DC
measurement
Typ.
–1900 –1322 –100
Level control:
–50% – Level control OFF
Level control:
30% – Level control OFF
Level control:
50% – Level control OFF
Min.
Note) O in the SW conditions 7 represents the OFF state.
10
18
18
18
2
2
2
2
Description of I/O waveform
and measurement method
CXA2550M/N
–7–
I1
0.8mA
I2
R1
300
VCC VCC VEE GND
S1
PD1
4
C1
33µ
S3
S2
VEE GND
R3
33k
R2
33k
R4
390k
S4
AC
7
6
PD2
5
R5
390k
E
GND
S6
8
S5
2
1
3
11
12
13
14
15
16
17
18
VCC
AGCVTH
S8
19
E3
R9
5.5k
R7
10k
LD_ON
LD
20
E4
E2
R8
10k
AGCCONT
PD
VEE
R10
10k
RFTC
E1
9
GND
S7
10
R6
10k
GND
RF I
C2
0.1µ
GND
RF O
VEE
R11
1M
GND
RFM
VEE
–8–
F
C3
33µ
VEE VEE GND GND GND
FE
VEE
FE_BIAS
EI
GND
TE
VC
Electrical Characteristics Measurement Circuit
CXA2550M/N
CXA2550M/N
Description of Functions
RF Amplifier
The photodiode current input to the input pins (PD1, PD2) are current-to-voltage (I-V) converted by the
equivalent resistance of 58kΩ at PD I-V amplifiers, respectively. The signal is added by the RF summing
amplifier and then the I-V converted output voltage of the photodiode (A + B + C + D) is output to RFO pin.
This pin is used check the eye pattern.
Cp
RFM
5.5k
14
15
RFO
58k
33k PD1
I-V
2k
VA
4
PD1 IV AMP
RF SUMMING AMP
58k
33k PD2
I-V
2k
VB
5
PD2 IV AMP
GND
The frequency response of the RF output signal can be equalized by adding the capacitance (Cp) to RFI pin.
The low frequency component of the RFO output voltage is as follows;
VRFO = –2.75 × (VA + VB)
= 159.5kΩ × (iPD1 + iPD2)
Focus Error Amplifier
The difference between the RF I-V amplifier output VA and VB is obtained and the I-V converted voltage of the
photodiode (A + C – B – D) is output.
24p
174k
– (B + D)
– (A + C)
VB
32k
13 FE
VA
32k
24p
87k
164k
FE BIAS
12
VEE
VCC
47k
The FE output voltage (low frequency) is as follows;
VFE = 5.4 × (VA – VB)
= (iPD2 – iPD1) × 315kΩ
–9–
CXA2550M/N
Tracking Error Amplifier
Each signal current from the photodiodes E and F is I-V converted and input to Pins 7 and 8 via a resistor
which determines the gain. The signal is amplified by the gain amplifier, operated by the tracking error
amplifier and then the (F-E) signal is output to Pin 11.
RF1 260k
RF2 13k
12p
220k
F
I-V
RF3
26k
96k
30k
7
11 TE
30k
RE1 260k RE2 13k
96k
12p
220k
I-V
E
8
RE3
26k
9
EI
270k
R1
22k
4.7k
R2
The balance adjustment is performed by varying the combined resistance value of the feedback resistors,
which are T type-configured at the E I-V amplifier, by using the external resistance value of EI pin.
F I-V amplifier feedback resistance value = RF1 + RF2 +
RF1 × RF2
= 403kΩ
RF3
E I-V amplifier feedback resistance value = (RE1 // R1) + RE2 + (RE1 // R1) × RE2
(RE3 // R2)
Leave EI pin open when the balance adjustment is not executed in this IC.
The gain for F I-V and E I-V amplifiers becomes the same when EI pin is left open.
– 10 –
CXA2550M/N
Center Voltage Generation Circuit
This circuit provides the center potential when this IC is used at single power supply. The maximum current is
approximately ±3mA. The output impedance is approximately 50Ω.
VCC
30k
VR
50
10
30k
VEE
APC & Laser Power Control
VCC
R1
22
C2
100µ
LD
2
L1
10µH
R10
56k
PD
3
C1
1µ
R2
500
LD
R3
100
19
LD_ON
MICROCOMPUTER
AGCCONT
MICROCOMPUTER
R8
10k
R5
55k
R4
10k
PD
GND
VCC
R6
1k
130mV
VEE
R12
56k
R11
10k
VEE
VREF
VEE
VL
R14
12.5k
RF I
1.1Vp-p
18
16
C3
0.01µ
R7
6k
RF O
15
RF
50µ
R9
54k
670mV
R15
13.4k
VEE
1
17
RFTC
R13
1M
AGCVTH
C4
1µ
VEE VEE
• APC
When the laser diode is driven by a constant current, the optical power output has extremely large negative
temperature characteristics. The APC circuit is used to maintain the optical power output at a constant level.
The laser diode current is controlled according to the monitor photo diode output.
APC is set to ON by connecting the LD_ON pin to VCC; OFF by connecting it to VCC.
– 11 –
CXA2550M/N
C3
SSP
RFM
FE
FE_BIAS
F
E
EI
VC
5
6
7
8
9
10
E
22k
I_V
R5
270k
R5
220k
R4
I_V
F
D
I_V
GND
C
B
A
33µ/6.3V
R3
R2
100
I_V
500
PD
LD
10µH
TE
RF O
VEE
4
220k
RF I
PD2
3
33k
2
33k
1
1µ/6.3V
VC
TRK E
GAIN
VC
R5
4.7k
VCC
11
RFTC
12
PD1
13
AGCCONT
14
PD
15
LD_ON
16
LD
VCC
17
100µ/6.3V
11
47k
18
AGCVTH
19
GND
5.5k
0.01µ
20
FOCUS
BIAS
SSP
SSP
R9
0.1µ
1M
R11
VCC
GND
33µ/6.3V
GND
VCC
MICROCOMPUTER
+3.5V
MICROCOMPUTER
Application Circuit
• For single power supply +3.5V
GND
GND
VC
5.5k
SSP
FOCUS
BIAS
VEE
FE
FE_BIAS
E
EI
VC
6
7
8
9
10
R5
22k
I_V
E
F
GND
270k
R5
I_V
R4
D
C
B
I_V
VEE
33µ/6.3V
R3
R2
I_V
100
500
A
TRK E
GAIN
GND
4.7k
GND
R5
LD
PD
10µH
TE
RFM
F
5
220k
RF O
VEE
4
220k
RF I
PD2
3
33k
2
33k
1
1µ/6.3V
VCC
11
RFTC
12
PD1
13
AGCCONT
14
PD
15
LD_ON
16
LD
17
100µ/6.3V
11
47k
18
AGCVTH
19
VCC
0.01µ
20
VCC
R9
0.1µ
1M
VCC
R11
33µ/6.3V
SSP
SSP
VEE
C3
MICROCOMPUTER
+1.75V
GND
MICROCOMPUTER
• For dual power supply ±1.75V
GND
VEE
GND
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 12 –
CXA2550M/N
• LASER POWER CONTROL (LPC)
The RF level is stabilized by attaching an offset to the APC VL and controlling the laser power in sync with the
RF level fluctuations.
The RF O and RF I levels are compared and the larger of the two is smoothed by the RFTC's external CR.
This signal is then compared with the reference level.
The laser power is controlled by attaching an offset to VL according to the results of comparison with the
reference level.
Set the reference level to 670mV. (center voltage reference)
When the reference level is changed, connect the external resistor to the AGCVTH pin (Pin 1). The reference
level can be lowered by connecting the resistor between Pin 1 and the center output voltage or between Pin
20 and VCC.
The AGCCONT pin (pin 18) is used to switch the level of the laser power control circuit; OFF, ON (laser power
limit of 30%) and ON (laser power limit of 50%)
Note) For the laser power limit, 50% is recommended for PD IC; 30% for LC.
LPC
LPC limit
H (VCC)
OFF
—
M (VC or OPEN)
ON
30%
Approximately 1.27V ± 350mV
L (VEE)
ON
50%
Approximately 1.27V ± 570mV
AGCCONT
VL variable range
Approximately 1.27V
Notes on Operation
1. Power supply
The CXA2550M/N can be used either at dual power supply or single power supply. The table below shows the
connection of power supply for each case.
VCC
VEE
VC
Dual power supply
+power supply
–power supply
GND
Single power supply
Power supply
GND
OPEN
2. RF amplifier
In this circuit, the IC internal phase compensation value is set so as to support the voltage output-type pickup.
Therefore, when the current output-type pickup is used, the capacitance of optical pickup and leads etc. are
attached to PD1 and PD2 pins and oscillation may occur.
3. laser power control
The RF level is stabilized by attaching an offset to the APC VL and controlling the laser power in sync with the
RF level fluctuations. Therefore, use this circuit in the state where the focus servo is applied.
The laser life is shortened by increasing the laser power when the less light is reflected from the disc. It is
recommended that the typical laser power value is set lower to maintain the laser life.
Take care of the laser maximum ratings when using the laser power control circuit.
– 13 –
CXA2550M/N
Package Outline
Unit: mm
CXA2550M
20PIN SOP (PLASTIC) 300mil
+ 0.4
12.45 – 0.1
20
+ 0.4
1.85 – 0.15
11
6.9
+ 0.2
0.1 – 0.05
10
0.45 ± 0.1
+ 0.1
0.2 – 0.05
1.27
0.5 ± 0.2
1
7.9 ± 0.4
+ 0.3
5.3 – 0.1
0.15
± 0.12 M
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY / PHENOL RESIN
SONY CODE
SOP-20P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
∗SOP020-P-0300-A
LEAD MATERIAL
COPPER ALLOY
PACKAGE WEIGHT
0.3g
JEDEC CODE
SCT Ass'y
20PIN SOP (PLASTIC) 300mil
+ 0.4
12.45 – 0.1
20
+ 0.4
1.85 – 0.15
11
6.9
+ 0.2
0.1 – 0.05
10
0.45 ± 0.1
+ 0.1
0.2 – 0.05
1.27
0.5 ± 0.2
1
7.9 ± 0.4
+ 0.3
5.3 – 0.1
0.15
± 0.12 M
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY / PHENOL RESIN
SONY CODE
SOP-20P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
∗SOP020-P-0300-A
LEAD MATERIAL
COPPER ALLOY
PACKAGE WEIGHT
0.3g
JEDEC CODE
LEAD PLATING SPECIFICATIONS
ITEM
SPEC.
LEAD MATERIAL
COPPER ALLOY
SOLDER COMPOSITION
Sn-Bi Bi:1-4wt%
PLATING THICKNESS
5-18µm
– 14 –
CXA2550M/N
Package Outline
Unit: mm
CXA2550N
20PIN SSOP (PLASTIC)
+ 0.2
1.25 – 0.1
∗6.5 ± 0.1
0.1
11
20
1
6.4 ± 0.2
∗4.4 ± 0.1
A
10
0.65
b
b=0.22 ± 0.03
0.5 ± 0.2
0.1 ± 0.1
+ 0.03
0.15 – 0.01
0.13 M
DETAIL B : PALLADIUM
NOTE: Dimension "∗" does not include mold protrusion.
0˚ to 10˚
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
SSOP-20P-L01
LEAD TREATMENT
PALLADIUM PLATING
EIAJ CODE
SSOP020-P-0044
LEAD MATERIAL
COPPER ALLOY
PACKAGE MASS
0.1g
JEDEC CODE
– 15 –
Sony Corporation