CXA3108AQ L-band Down Converter IC with On-Chip PLL Description The CXA3108AQ is a monolithic IC that downconverts the L-band (1 to 2 GHz) 1st IF to 2nd IF for satellite broadcast receivers. It integrates a local oscillator circuit, double-balanced mixer, IF AGC amplifier and tuning PLL onto a single chip. This IC supports both analog and digital satellite broadcasts, and achieves reduction in the number of tuner components and smaller size. Features • On-chip tuning PLL • Supports 2.65 GHz oscillator frequency • Noise figure: 12.5 dB typ. (for IF full gain) • • • • • IF AGC gain variation: 46 dB typ. Wide band IF AGC amplifier (60 to 500 MHz) Two IF outputs PLL supports I2C protocol On-chip high voltage drive transistor for charge pump 40 pin QFP (Plastic) Absolute Maximum Ratings (Ta=25 °C) • Supply voltage VCC –0.3 to +5.5 V • Storage temperature Tstg –55 to +150 °C • Allowable power dissipation PD 730 mW (when mounted on a substrate) Operating Conditions • Supply voltage VCC • Operating temperature Topr 4.75 to 5.30 –25 to +75 V °C Applications • Analog satellite broadcast tuners (BS/CS) • Digital satellite broadcast tuners (DSS/DVB, etc.) Structure Bipolar silicon monolithic IC Notes on Handling This IC has a weak electrostatic discharge strength. Take care when handling the IC. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E99904-TE CXA3108AQ XTAL 31 DGND1 32 NC BUSSW DVCC1 ADSW SCL SDA ADC LOCK DVCC2 STSW CPO VT Block Diagram and Pin Configuration 30 29 28 27 26 25 24 23 22 21 20 EXTIN2 Divider 11bit REF OSC Phase Detector 19 EXTIN1 33 I2C Receiver 34 Lock Det 18 DGND2 Shift Register 17 GND Charge Pump Buffer Output Port Driver Divider 17 bit STSW PS1 35 PS2 36 PS3 37 PS4 38 16 OSCB2 Prescaler 1/2, 1/1 14 OSCE1 13 OSCB1 Buffer GND 39 IFOUT2 40 15 OSCE2 OSC Buffer 12 RFVCC SAW Driver IF AGC AMP OUTPUT SW SAW Driver MIX 11 BIAS IFVCC2 7 8 9 10 RFGND IFSW 6 IFGND1 IFGND2 5 RFIN2 4 RFIN1 3 IFAGC 2 IFVCC1 1 IFOUT1 IF VCC —2— CXA3108AQ Pin Description Pin No. Symbol Pin voltage [V] IFOUT1 2.5 (IFSW 0 V) 4.7 (IFSW 5 V) 40 IFOUT2 4.7 (IFSW 0 V) 2.5 (IFSW 5 V) 2 IFGND2 0 1 Equivalent circuit Description 4 IFVCC2 IF outputs. 1 40 IF output circuit GND. 4 IFVCC2 30k 3 IFSW 4 5 IFVCC2 IFVCC1 0 or 5 3 100k 5 5 Selects whether IF output is Pin 1 or Pin 40. When this pin is connected to GND, the IF signal is output from Pin 1; when connected to VCC, the IF signal is output from Pin 40. IF output circuit power supply. IF amplifier circuit power supply. 5 IFVCC1 6 6 IFAGC 0 to 4 AGC signal input. 40k 40k 7 RFIN1 1.7 7 8 2k 2k RF inputs. 8 RFIN2 9 10 IFGND1 RFGND 1.7 0 0 IF amplifier circuit GND. RF block GND. —3— CXA3108AQ Pin No. Symbol Pin voltage [V] Equivalent circuit 12 Description RFVCC Oscillator circuit current adjustment. Connect this pin to GND via a capacitor. 200 11 BIAS 1.8 12 RFVCC 5 13 OSCB1 2.2 11 RF block power supply. 13 14 OSCE1 14 15 16 1.5 Oscillator pins. 2.5k 15 OSCE2 1.5 16 OSCB2 2.2 17 18 GND DGND2 0 0 19 EXTIN1 2.5 2.5k GND. Charge pump GND. 30 DVCC1 25k 19 5k 5k 20k 20 EXTIN2 VT 25k 24 — 200 500 20k 22 CPO PLL external inputs. 2.5 DVCC2 21 20 — —4— NPN transistor output for varicap diode drive. 22 21 Charge pump output. Connect a loop filter. CXA3108AQ Pin No. Symbol Pin voltage [V] Equivalent circuit Description 23 STSW — Selects either the internal oscillator circuit or external input for input to PLL. When this pin is open or connected to VCC, the internal oscillator circuit is selected; when connected to GND, external input is selected. 24 DVCC2 5 Charge pump power supply. 30 DVCC1 20k 23 30 DVCC1 25 LOCK 5.0 (LOCK) 0.2 (UNLOCK) 25 30 26 ADC — LOCK detection. High when locked, Low when unlocked. DVCC1 ADC input. 26 30 DVCC1 5k 27 SDA — DATA input. 27 20 2.5k 40k —5— CXA3108AQ Pin No. Symbol Pin voltage [V] Equivalent circuit 30 28 SCL — Description DVCC1 CLOCK input. 28 30 DVCC1 150k 29 ADSW 1.3 I2C bus address selection. 29 50k 30 DVCC1 5 PLL circuit power supply. 30 DVCC1 30p 60k 31 XTAL 4.4 32 33 DGND1 NC 0 — 30p 31 Crystal connection for reference oscillator. PLL circuit GND. —6— CXA3108AQ Pin No. Symbol Pin voltage [V] Equivalent circuit 30 34 BUSSW 35 PS1 — DVCC1 PLL circuit GND. Connect directly to GND. 34 30 DVCC1 36 PS2 37 PS3 38 PS4 39 GND Description 5.0 (OFF) 0.2 (ON) 35 36 Output ports. 37 38 0 GND. —7— CXA3108AQ Electrical Characteristics Circuit Current Item (VCC=5 V, Ta=25 °C) Symbol Circuit current A AICC Circuit current D DICC Measurement conditions Analog circuit current Sum of RFVCC, IFVCC1 and IFVCC2 currents PLL circuit current Sum of DVCC1 and DVCC2 currents Min. Typ. Max. Unit 42 62 82 mA 18 30 40 mA Measurement conditions fin=950 MHz, fIF=480 MHz IFAGC=4 V (Full Gain) fin=1450 MHz, fIF=480 MHz IFAGC=4 V (Full Gain) fin=2150 MHz, fIF=480 MHz IFAGC=4 V (Full Gain) fin=950 MHz, fIF=480 MHz IFAGC=4 V (Full Gain) fin=1450 MHz, fIF=480 MHz IFAGC=4 V (Full Gain) fin=2150 MHz, fIF=480 MHz IFAGC=4 V (Full Gain) Min. Typ. Max. Unit 15 21 25 dB 14 20 24 dB 18 24 28 dB 13 16 dB 13 16 dB 13 16 dB OSC/MIX/IF Amplifier Blocks Item Symbol CG1 Conversion gain CG2 CG3 NF1 Noise figure NF2 NF3 IFAGC gain variation range AGC IF maximum output PoSAT RF pin local oscillator leak IF pin local oscillator leak RFLK1 RFLK2 RFLK3 IFLK1 IFLK2 IFLK3 Tertiary intermodulation IM3 distortion Local oscillator phase noise RF input impedance CN1 CN2 rπ Cπ 35 fIF=480 MHz, 50 Ω load saturated output fOSC=1430 to 1830 MHz fOSC=1830 to 2230 MHz fOSC=2230 to 2630 MHz fOSC=1430 to 1830 MHz fOSC=1830 to 2230 MHz fOSC=2230 to 2630 MHz Pin=–25 dBm IFAGC=4 V (Full Gain) fin=935 MHz, 940 MHz fout=475 MHz, 480 MHz S/I of 480 MHz and 475 MHz fOSC=1430 MHz 10 kHz offset fOSC=1430 MHz 100 kHz offset f=950 MHz f=950 MHz —8— 50 dB 9 dBm –20 –20 –25 –18 –18 –20 38 dBm dBm dBm dBm dBm dBm 45 dB 80 dBc/Hz 100 dBc/Hz 12.9 1.84 Ω pF CXA3108AQ PLL Block Item External local input level SDA, SCL High level input voltage Low level input voltage High level input current Low level input current SDA Low output voltage Clock input hysteresis CPO (charge pump) Output current 1 Output current 2 ADC Input current LOCK High output voltage Low output voltage REFOSC Oscillator frequency range Input capacitance Drive level PS1 to PS4 Pull-in current Leak current Symbol EXT VIH VIL IIH IIL LSDA CIHYS Measurement conditions Typ. –20 3 GND Byte 4/bit 6=0 and for 3WB Byte 4/bit 6 IADC Input voltage=5 V VLKH VLKL Load resistance 10 kΩ, for LOCK Load resistance 10 kΩ, for UNLOCK FXTOSC CXTOSC VXTOSC Max. Unit dBm V V µA µA V V µA µA 0.25 0.4 VCC 1.5 –0.1 –2 0.4 0.65 ±35 ±125 ±50 ±180 ±75 ±270 VIH=VCC VIL=GND Sink current=3 mA ICPO1 ICPO2 SinkPS LeakPS Min. 0 –1 0.2 3 µA VCC 0.5 V V 12 MHz pF mV 1 200 mA nA Max. Unit 400 kHz ns ns ns ns ns ns ns ns ns ns 14 200 When ON When OFF Bus Timing Item Bus SCL clock frequency Start waiting time Start hold time Low hold time High hold time Start setup time Data hold time Data setup time Rise time Fall time Stop setup time Symbol Measurement conditions Min. Typ. I2C fSCL tWSTA tHSTA tLOW tHIGH tSSTA tHDAT tSDAT tR tF tSSTO 0 1300 600 1300 600 600 1300 600 300 300 600 —9— IFout1 1n IFSW CXA3108AQ 68n EXTIN2 20 1n 40 1 IFOUT1 IFOUT2 39 GND 38 PS4 37 PS3 36 PS2 35 PS1 34 BUSSW 2 3 4 5 7 6 100p 100p 9 8 10 1n BIAS 11 RFVCC 12 OSCB1 13 OSCE1 14 OSCE2 15 OSCB2 16 GND 17 DGND2 18 IFVCC1 33 NC RFIN2 EXTIN1 19 XTAL IFGND1 32 DGND1 31 IFAGC IFAGC 100p 21 22 23 24 25 26 27 28 29 30 DVCC1 6.2k 330n ADSW 10k SCL IFGND1 SDA SCL ADC SDA LOCK IFVCC2 DVCC2 ADCin STSW RFGND —10— RFin IFout2 5V LOCK CPO RFIN1 VT Electrical Characteristics Measurement Circuit 0.1µ 15p 15p 1n 1n 1µ 1k 1T379 1k 1T379 1k 10k 30V 5V EXTIN CXA3108AQ CXA3108AQ Description of Functions The CXA3108AQ is a tuner IC for satellite broadcast receivers. It converts the RF signal down-converted to 1st IF (1 to 2 GHz) at the LNB to 2nd IF, so that only the desired reception frequency is selected and detected. This IC combines the mixer, local oscillator and IF amplifier (variable gain) circuits required for frequency conversion to 2nd IF, and the PLL circuit which controls the local oscillator frequency onto a single chip. The function of each block is described below. 1. Mixer Circuit This circuit outputs the frequency difference between the signal input to RF IN and the local oscillator signal. A double-balanced mixer with minimal local oscillator signal leak is used. RF input is equivalent to a differential amplifier with emitter grounding. 2. Local Oscillator Circuit A Colpitts oscillator with differential operation is used for the oscillator circuit, so it is stable relative to supply voltage fluctuation, and undesired radiation is suppressed. This circuit also contains a capacitor which is part of the resonance circuit, so there is minimal parasitic oscillation and design of external circuits is easier. 3. IF Amplifier Circuit This circuit amplifies the mixer IF output, and is comprised of an AGC amplifier stage and low impedance output stage. The gain can be varied by the AGC pin voltage (range 0 to 4 V) at the AGC amplifier stage. The maximum gain is approximately 20 dB (voltage gain between RF IN and IF OUT), and the gain variation width is 30 dB or more. The output stage has two unbalanced outputs, and can directly connect two SAW filters with different pass bandwidths. Output pin selection is determined by the IF SW pin voltage. The IF amplifier circuit is a wide band amplifier circuit, and can be used in the IF frequency range of 60 to 500 MHz. 4. PLL Circuit-1 (normal operation: when the STSW pin is open or connected to VCC) The PLL circuit fixes the local oscillator frequency to the desired frequency. It consists of the prescaler, main divider, reference divider, phase comparator, charge pump and reference oscillator. The control format supports the I2C bus protocol. When the power (DVCC1) is turned on, the power-on reset circuit activates and the frequency division data and control data are all initialized to 0. The power-on reset threshold is 3 V at normal temperature (Ta=25 °C). 5. PLL Circuit-2 (external input PLL operation: when the STSW pin is connected to GND) When the STSW pin is connected to GND, the PLL enters independent operation mode where the PLL only is used with the oscillator signal input from the external signal input pin. —11— CXA3108AQ Description of PLL Block 1. Programming 1-1. The main divider frequency division ratio is obtained according to the following formulas. fosc = fref × (16M + S) or fosc = fref × 2 × (16M + S) (when PE = 1) fosc : local oscillator frequency fref : comparison frequency 2 : prescaler fixed frequency division ratio (when PE = 1) M : main divider frequency division ratio S : swallow counter frequency division ratio The variable frequency division ranges of M and S are as follows. S ≤ M ≤ 4095 0 ≤ S ≤ 15 During PLL independent operation (STSW = GND), the prescaler halving frequency division cannot be added. 1-2. I2C Bus This IC conforms to the standard I2C bus format, and bidirectional bus control is possible consisting of a write mode in which various data are received and a read mode in which various data are sent. Write and read modes are recognized according to the setting of the final bit (R/W bit) of the address byte. Write mode is set when the R/W bit is “0”, and read mode is set when the R/W bit is “1”. 1-2-1. Address Setting The responding address can be changed by the ADSW pin voltage to allow more than one PLL in a system. <Table 1> Address ADSW pin voltage 0 to 0.1 VCC OPEN 0.4 VCC to 0.6 VCC 0.9 VCC to VCC MA1 0 0 1 1 MA0 0 1 0 1 —12— CXA3108AQ 1-2-2. Data format Write mode is used to receive various data. In this mode, byte 1 contains the address data, bytes 2 and 3 contain the frequency data, and bytes 4 and 5 contain the various control data. These data are latch transferred in the manner of byte 1, byte 2 + byte 3, byte 4, and byte 5. When the correct address is received, the data is recognized as frequency data if the first bit of the next byte is “0”, and as control data if this bit is “1”. Also, when data transmission is stopped part-way, the previously programmed data is valid. Therefore, once the control data has been programmed, 3-byte commands consisting of the address and frequency data are possible. Further, even if the I2C bus stop conditions are not met, data can be input by sending the start conditions and the new address. In read mode, the power-on reset operation status, phase comparator locked/unlocked status and 5value A/D converter input pin voltage status are transmitted to the master. Power-on reset is set to “1” when the supply voltage (DVCC1) power supply is cut off. If DVCC1 is 3 V or higher and the status is output in the read mode, this bit is reset to “0”. Write mode: slave receiver MODE Address byte Divider byte 1 Divider byte 2 Control byte 1 Control byte 2 MSB bit7 1 0 M3 1 OS bit6 1 M10 M2 M12 CP bit5 0 M9 M1 M11 0 bit4 0 M8 M0 PE 0 bit3 0 M7 S3 R3 P4 bit2 MA1 M6 S2 R2 P3 bit1 MA0 M5 S1 R1 P2 LSB bit0 0 M4 S0 R0 P1 bit7 1 PR bit6 1 FL bit5 0 1 bit4 0 1 bit3 0 1 bit2 MA1 A2 bit1 MA0 A1 bit0 1 A0 Read mode: slave transmitter MODE Address byte Status byte —13— A A A A A CXA3108AQ P1 to P4 M0 to M12 S0 to S3 OS CP PE PR FL A0 to A2 R0 to R3 : : : : : : : : : : port control main divider frequency division ratio setting swallow counter frequency division ratio setting varicap output OFF (when “1”) charge pump current switching prescaler halving frequency division added (when “1”) power-on reset lock detection signal 5-value ADC data (ADC pin voltage conversion: Table 2) reference divider frequency division ratio selection (Table 3) <Table 2> ADC Conversion Table ADC pin voltage 0 to 0.15VCC 0.15 VCC to 0.3 VCC 0.3 VCC to 0.45 VCC 0.45 VCC to 0.6 VCC 0.6 VCC to VCC A2 0 0 0 0 1 A1 0 0 1 1 0 A0 0 1 0 1 0 <Table 3> Reference Divider Frequency Division Ratio R3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 R1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 R0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 —14— Frequency division ratio 2 4 8 16 32 64 128 256 — 5 10 20 40 80 160 320 CXA3108AQ I2C Bus Timing Chart tWSTA SDA tR tSSTA tF tSSTO SCL tHSTA START tLOW tHIGH tSDAT CLOCK tHDAT DATA CHANGE tSSTA =Start setup time tWSTA =Start waiting time tHSTA =Start hold time tLOW =LOW clock pulse width tHIGH =HIGH clock pulse width tSDAT tHDAT tSSTO tR tF —15— =Data setup time =Data hold time =Stop setup time =Rise time =Fall time STOP CXA3108AQ Example of Representative Characteristics Current consumption characteristics ICC - Current consumption [mA] 100 95 90 85 75 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 VCC Supply voltage [V] Conversion gain IF=480MHz, AGC=4V 25 CG - Conversion gain [dB] IFOUT 20 15 10 5 0.8 1 1.2 1.4 1.6 RF input frequency [GHz] NF characteristics IF=480 MHz, AGC=4V Untuned input, DSB display NF - Noise figure [dB] 20 15 10 5 0 0.8 1 1.2 1.4 1.6 1.8 2 RF input frequency [GHz] —16— 2.2 1.8 2 2.2 CXA3108AQ RF pin local oscillator leak characteristics RF pin local oscillator leak [dBm] –10 –20 –30 –40 –50 –60 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 fOSC - Local oscillator frequency [GHz] IFOUT pin local oscillator leak characteristics AGC=4V IFOUT pin local oscillator leak [dBm] –10 –20 –30 –40 –50 –60 1.4 1.6 1.8 2 2.2 2.4 fOSC - Local oscillator frequency [GHz] Input/output characteristics (untuned input, AGC=4V) 20 10 Fundamental wave (480MHz) 0 IF output level [dBm] –10 –20 –30 –40 –50 –60 Tertiary intermodulation distortion component (470MHz) –70 –60 –50 –40 –30 –20 –10 0 10 RF input level [dBm] (935MHz, 940MHz) —17— 2.6 2.8 CXA3108AQ Input Impedance 3 2150MHz 1 950MHz 2 1450MHz Output Impedance 479.5MHz 1 —18— CXA3108AQ Unit : mm 40PIN QFP (PLASTIC) + 0.35 1.5 – 0.15 + 0.1 0.127 – 0.05 9.0 ± 0.4 + 0.4 7.0 – 0.1 0.1 21 30 20 31 A 11 40 1 + 0.15 0.3 – 0.1 0.65 10 0.24 M (8.0) + 0.15 0.1 – 0.1 0° to 10° 0.5 ± 0.2 Package Outline DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE QFP-40P-L01 LEAD TREATMENT SOLDER / PALLADIUM PLATING EIAJ CODE QFP040-P-0707 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.2g JEDEC CODE —19—