SONY CXA3627ER

CXA3627ER
All Band Tuner IC with On-chip PLL
Description
The CXA3627ER is a monolithic TV tuner IC which
integrates local oscillator and mixer circuits for VHF
band, local oscillator and mixer circuits for UHF
band, an IF amplifier and a tuning PLL onto a single
chip, enabling further miniaturization of the tuner by
adopting a small package.
Features
• Low power consumption (5V, 63mA typ.)
• Low noise figure, low distortion characteristics
• High gain/low gain selectable
• Supports IF double-tuned/adjacent channel trap
• Balanced oscillator circuits with excellent oscillation
stability
• On-chip PLL supports I2C bus
• On-chip high voltage drive transistor for charge
pump
• Frequency step selectable from 31.25, 50 or
62.5kHz (when using a 4MHz crystal)
• Low-phase noise synthesizer
• On-chip 4-output band switch (output voltage: 5V,
current capacity: 13mA)
• 32-pin VQFN small package
• UHF band switch output switchable
32 pin VQFN (Plastic)
Absolute Maximum Ratings
• Supply voltage
VCC
• Operating temperature Topr
• Storage temperature
Tstg
• Allowable power dissipation
PD
Operating Conditions
Supply voltage
VCC
–0.3 to +5.5
–25 to +75
–55 to +150
610
V
°C
°C
mW
4.75 to 5.30
V
Applications
• TV tuners
• VCR tuners
• CATV tuners
Structure
Bipolar silicon monolithic IC
Note: This IC has pins whose electrostatic discharge strength is weak as the operating frequency is high
and the high-frequency process is used for this IC. Take care of handling the IC.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E02846B45
CXA3627ER
BS2
BS1
SDA
SCL
NC
IFOUT
ADSW
BS3
Block Diagram and Pin Configuration
32
31
30
29
28
27
26
25
IFIN1 1
IF AMP
IFIN2 2
Divider
1/128, 160, 256
Shift
Register
I2C Bus
Interface
REF
OSC
24 REFOSC
VCC 3
Charge
Pump
Phase
Detector
Band SW
Driver
22 VT
MIXOUT1 4
Programmable
Divider
14/15 bit
MIXOUT2 5
Prescaler
1/2
21 GND2
VHF
MIX
GND1 6
23 CPO
20 UOSCB2
19 UOSCE2
VHFOSC
UHF
MIX
VHFIN 7
18 UOSCE1
BYP 8
17 UOSCB1
–2–
UHFIN1
UHFIN2
NC
13
14
15
16
VOSCB2
12
VOSCC2
11
VOSCC1
10
VOSCB1
9
BS4
UHFOSC
CXA3627ER
Pin Description
Pin
No.
Symbol
Pin voltage
[V]
Equivalent circuit
Description
3
1
1
IFIN1
1.6k
2
IF inputs.
These pins must be connected
to the mixer outputs via
coupling capacitance.
2.0
2
IFIN2
3
VCC
—
—
Power supply.
4
4
5
MIXOUT1
Mixer outputs.
These pins output the signal in
open collector format, and they
must be connected to the
power supply via a load.
—
5
MIXOUT2
6
GND1
—
VHFIN
2.4 during
VHF reception
0.0 during
UHF reception
7
—
Analog circuit GND.
3
10k
15p
100
VHF input.
The input format is unbalanced
input.
7
3k
8
BYP
3k
3.8
(when open)
8
–3–
VHF input GND and selection
of band switching.
GND: BS4 UHF
Open: BS3 UHF
CXA3627ER
Pin
No.
Symbol
Pin voltage
[V]
Equivalent circuit
Description
3
9
BS4
9
25
25
100k
BS3
Band switch outputs.
This pin corresponding to the
selected band goes High.
High: 4.9
Low: 0.0
3
31
BS1
31
32
32
BS2
10
UHFIN1
3
11
UHFIN2
12
NC
13
14
15
16
VOSCB1
VOSCC1
11
3k
—
VOSCC2
4.0 during
VHF reception
VCC during
UHF reception
VOSCB2
2.3 during
VHF reception
2.5 during
UHF reception
3k
—
2.3 during
VHF reception
2.5 during
UHF reception
4.0 during
VHF reception
VCC during
UHF reception
UHF inputs.
Input a balanced signal to
Pins 14 and 15, or ground
either of Pin 14 or 15 with a
capacitor and input the signal
to the other pin.
10
0.0 during
VHF reception
2.3 during
UHF reception
16
15
14
13
3
20
20
External resonance circuit
connection for VHF oscillator.
5k
5k
–4–
CXA3627ER
Pin
No.
17
18
Symbol
Pin voltage
[V]
UOSCB1
2.4 during
VHF reception
2.2 during
UHF reception
UOSCE1
2.0 during
VHF reception
1.5 during
UHF reception
Equivalent circuit
Description
3
20
19
18
External resonance circuit
connection for UHF oscillator.
17
19
UOSCE2
2.0 during
VHF reception
1.5 during
UHF reception
20
UOSCB2
2.4 during
VHF reception
2.2 during
UHF reception
24
GND2
3k
3k
—
—
PLL circuit GND.
Varicap drive voltage output.
This pin outputs the signal in
open collector format, and it
must be connected to the
tuning power supply via a load.
3
22
VT
—
23
22
70
23
CPO
Charge pump output.
Connects the loop filter.
2.0
3
30k
25p
100
24
REFOSC
4.4
Crystal connection for
reference oscillator.
24
38p
3
150k
26
ADSW
1.25
(when open)
Address selection.
Controls address bits 1 and 2.
26
50k
5p
–5–
CXA3627ER
Pin
No.
Symbol
Pin voltage
[V]
Equivalent circuit
Description
3
27
IFOUT
2.8
28
NC
—
IF output.
27
—
3
29
SCL
—
Clock input.
40k
29
3
30
SDA
40k
—
Data input.
30
5p
–6–
CXA3627ER
Electrical Characteristics (See the Electrical Characteristics Measurement Circuit.)
(Vcc = 5V, IFVCC = 5V, Ta = 25°C)
Circuit Current
Item
Symbol
Measurement conditions
Min.
Typ.
Max.
Unit
Iccv
VCC current
Band switch output open during VHF operation
41
64
88
mA
Iccu
VCC current
Band switch output open during UHF operation
40
63
87
mA
Measurement conditions
Min.
Typ.
Max.
Unit
Circuit current
OSC/MIX/IF Amplifier Block
Item
Conversion gain∗1
Noise figure∗1, ∗2
1% cross
modulation 1∗1, ∗3
Maximum output
power
Symbol
CG1
VHF operation fRF = 55MHz
High gain mode
19.0
22.0
25.0
dB
CG2
VHF operation fRF = 360MHz High gain mode
19.5
22.5
25.5
dB
CG3
UHF operation fRF = 360MHz High gain mode
23.0
26.0
29.0
dB
CG4
UHF operation fRF = 800MHz High gain mode
23.0
26.0
29.0
dB
CG5
VHF operation fRF = 55MHz
Low gain mode
17.0
20.0
23.0
dB
CG6
VHF operation fRF = 360MHz Low gain mode
17.5
20.5
23.5
dB
CG7
UHF operation fRF = 360MHz Low gain mode
21.0
24.0
27.0
dB
CG8
UHF operation fRF = 800MHz Low gain mode
21.0
24.0
27.0
dB
NF1
VHF operation fRF = 55MHz
High gain mode
12
15
dB
NF2
VHF operation fRF = 360MHz High gain mode
12
15
dB
NF3
UHF operation fRF = 360MHz High gain mode
10
13
dB
NF4
UHF operation fRF = 800MHz High gain mode
11
14
dB
NF5
VHF operation fRF = 55MHz
Low gain mode
13
16
dB
NF6
VHF operation fRF = 360MHz Low gain mode
13
16
dB
NF7
UHF operation fRF = 360MHz Low gain mode
11
14
dB
NF8
UHF operation fRF = 800MHz Low gain mode
12
15
dB
CM1
VHF operation fD = 55MHz
fUD = ±12MHz (30% AM) High gain mode
99
103
dBµ
CM2
VHF operation fD = 360MHz
fUD = ±12MHz (30% AM) High gain mode
99
103
dBµ
CM3
UHF operation fD = 360MHz
fUD = ±12MHz (30% AM) High gain mode
97
101
dBµ
CM4
UHF operation fD = 800MHz
fUD = ±12MHz (30% AM) High gain mode
94
98
dBµ
CM5
VHF operation fD = 55MHz
fUD = ±12MHz (30% AM) Low gain mode
100
104
dBµ
CM6
VHF operation fD = 360MHz
fUD = ±12MHz (30% AM) Low gain mode
100
104
dBµ
CM7
UHF operation fD = 360MHz
fUD = ±12MHz (30% AM) Low gain mode
98
102
dBµ
CM8
UHF operation fD = 800MHz
fUD = ±12MHz (30% AM) Low gain mode
94
98
dBµ
8
11
dBm
Pomax 50Ω load, saturation output
–7–
CXA3627ER
Item
Symbol
Measurement conditions
Min.
Typ.
Max.
Unit
∆fsw1
VHF operation fOSC = 100MHz
∆f from 3s to 3min after switch ON
±200
kHz
∆fsw2
VHF operation fOSC = 405MHz
∆f from 3s to 3min after switch ON
±650
kHz
∆fsw3
UHF operation fOSC = 405MHz
∆f from 3s to 3min after switch ON
±350
kHz
∆fsw4
UHF operation fOSC = 845MHz
∆f from 3s to 3min after switch ON
±400
kHz
∆fst1
VHF operation fOSC = 100MHz
∆f when VCC 5V changes ±5%
±100
kHz
Supply voltage drift ∆fst2
(PLL not
operating) ∗4
∆fst3
VHF operation fOSC = 405MHz
∆f when VCC 5V changes ±5%
±350
kHz
UHF operation fOSC = 405MHz
∆f when VCC 5V changes ±5%
±100
kHz
∆fst4
UHF operation fOSC = 845MHz
∆f when VCC 5V changes ±5%
±100
kHz
C/N1
VHF operation 10kHz offset CP = 1
Phase comparison frequency = 31.25kHz
80
dBc/Hz
C/N2
UHF operation 10kHz offset CP = 1
Phase comparison frequency = 31.25kHz
80
dBc/Hz
Switch ON drift
(PLL not
operating) ∗4
Oscillator phase
noise
∗1 Value measured with untuned input.
∗2 NF meter direct-reading value (DSB measurement).
∗3 Value with a desired reception signal input level of –30dBm, an interference signal of 100kHz/30% AM,
and an interference signal level where S/I = 46dB measured with a spectrum analyzer.
∗4 Value when the PLL is not operating.
–8–
CXA3627ER
PLL Block
Item
Symbol
Min.
Typ.
Max.
Unit
LUT1
VHF operation CP = 1
fOSC 100MHz →
← fOSC 405MHz
50
ms
LUT2
UHF operation CP = 1
fOSC 405MHz →
← fOSC 845MHz
50
ms
REFL
Phase comparison frequency
= 31.25kHz
CP = 1
Lock-up time
Reference leak
Measurement conditions
dBc
50
CL and DA inputs
"H" level input voltage
VIH
3
Vcc
V
"L" level input voltage
VIL
GND
1.5
V
"H" level input current
IIH
VIH = Vcc
0
–0.1
µA
"L" level input current
IIL
VIL = GND
–0.2
–4
µA
AD input
"H" level input voltage
VIH
3
Vcc
V
"L" level input voltage
VIL
GND
1
V
"H" level input current
IIH
VIH = Vcc
100
200
µA
"L" level input current
IIL
VIL = GND
–35
–100
µA
"H" output leak current
ISDALK
VIN = 5.5V
5
µA
"L" output voltage
VSDAL
Sink = –3mA
GND
0.4
V
Output current 1
ICPO1
When CP = 0 is selected
±30
±80
µA
Leak current 1
LeakCP1 When CP = 0 is selected
30
nA
Output current 2
ICPO2
±320
µA
Leak current 2
LeakCP2 When CP = 1 is selected
100
nA
Maximum output voltage
VTH
34
V
Minimum output voltage
VTL
0.8
V
12
MHz
26
pF
SDA output
CPO (charge pump)
When CP = 1 is selected
±120
±50
±200
VT (VC voltage output)
Sink current = 1mA
0.15
REFOSC
Oscillation frequency range
FXTOSC
3
Input capacitance
CXTOSC
22
24
Negative resistance
RNEG
Crystal source impedance
fREF = 4MHz
–1
–3
Output current
IBS
When ON
Saturation voltage
VSAT
When ON Source current =
13mA
Leak current
LeakBS
When OFF IFVCC = 5.5V
kΩ
Band SW
–9–
–13
mA
250
330
mV
0.5
3
µA
CXA3627ER
Item
Symbol
Measurement conditions
Min.
Typ.
Max.
Unit
400
kHz
Bus timing (I2C bus)
SCL clock frequency
fSCL
Start waiting time
tW;STA
tH;STA
tLOW
tHIGH
tS;STA
tH;DAT
tS;DAT
tR
tF
tS;STO
Start hold time
Low hold time
High hold time
Start setup time
Data hold time
Data setup time
Rise time
Fall time
Stop setup time
0
1300
ns
600
ns
1300
ns
600
ns
600
ns
0
900
600
600
– 10 –
ns
ns
300
ns
300
ns
ns
CXA3627ER
Electrical Characteristics Measurement Circuit
+30V
22k
4700p
240
220n
0.056µ
10k
10k
BS2
2.5φ
2.5T
1n
1T363
1T363
10k
0.5p
10k
BS1
0.5p
XTAL
4MHz
56p
7p 56p
100p
7p
2p
3.0φ
5.5T
1k
4.7k
1n
0.5p
2.5φ
2.5T
100p
7p
ADSW
20
19
18
UOSCB2
UOSCE2
UOSCE1
4.7k
1T363
1T362
1n
8p
15p
17
UOSC
B1
21
GND2
25 BS3
22
VT
REFOSC
360
23
CPO
2.2n
24
26 ADSW
VOSC 16
B2
VOSCC2 15
27 IFOUT
VOSCC1 14
28 NC
VOSCB1 13
27
1n
IF OUT
51
SCL
29 SCL
NC 12
30 SDA
UHFIN2 11
31 BS1
UHFIN1 10
51
UHF IN
SDA
1n
GND1
VHFIN
BYP
1
MIXOUT2
BS2
MIXOUT1
BS1
VCC
32 BS2
IFIN2
360
IFIN1
360
2
3
4
5
6
7
8
1n
BS4 9
360
1n
1n
150p
150p
4.5T 4.5T
56p
100
1n
56p
1n
4.7µ
+5V
– 11 –
VHF IN
1n
4.7k
CXA3627ER
Application Circuit
+30V
22k
4700p
240
220n
0.056µ
10k
10k
BS2
2.5φ
2.5T
1n
0.5p
10k
BS1
1T369
3.0φ
5.5T
1n
12p
XTAL
4MHz
0.5p
2.5φ
2.5T
100p
100p
1k
4.7k
100p
100p
22p
8p
8p
1n
IF OUT
1.2µH
19
18
UOSCB2
UOSCE2
UOSCE1
4.7k
1T363
1T362
1n
8p
15p
17
UOSC
B1
20
26 ADSW
VOSC 16
B2
VOSCC2 15
27 IFOUT
VOSCC1 14
28 NC
VOSCB1 13
3k
ADSW
21
GND2
25 BS3
22
VT
REFOSC
FMT
23
CPO
2.2n
24
27
10p
200
NC 12
30 SDA
UHFIN2 11
31 BS1
UHFIN1 10
UHF IN
47p
GND1
VHFIN
BYP
1
MIXOUT2
BS2
MIXOUT1
32 BS2
BVH
VCC
1n
BVL
BS1
29 SCL
200
IFIN2
SDA
47p
IFIN1
SCL
2
3
4
5
6
7
8
1n
BS4 9
BU
1n
3.8φ
14.5T
33p
150p
1n
2k
3.2φ
7.5T
1n
4.5T 4.5T
1n
56p
100
1n
56p
1n
VHF IN
4.7µ
+5V
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 12 –
4.7k
CXA3627ER
Description of Functions
The CXA3627ER is the terrestrial TV broadcasting tuner IC which converts frequencies to IF in order to tune
and detect only the desired reception frequency of VHF and UHF band signals.
In addition to the mixer, local oscillation and IF amplifier circuits required for frequency conversion to IF, this IC
also integrates a PLL circuit for local oscillation frequency control onto a single chip.
The functions of the various circuits are described below.
1. Mixer circuit
This circuit outputs the frequency difference between the signal input to VHFIN or UHFIN and the local
oscillation signal.
2. Local oscillation circuit
A VCO is formed by externally connecting an LC resonance circuit composed of a varicap diode and inductance.
3. IF amplifier circuit
This circuit amplifies the mixer IF output, and consists of an amplifier stage and low impedance output stage.
4. PLL circuit
This PLL circuit fixes the local oscillation frequency to the desired frequency. It consists of a programmable
divider, reference divider, phase comparator, charge pump and reference oscillator. The control format
supports the I2C bus format.
The frequency steps of 31.25, 50 or 62.5kHz can be selected by the I2C bus data-based reference divider
frequency division setting value.
5. Band switch circuit
The CXA3627ER has four sets of built-in PNP transistors for switching between the VL, VH and UHF bands
and for switching the FM trap, etc. These PNP transistors can be controlled by the bus data.
The emitters for these PNP transistors are connected to the power supply pin (VCC), and are ON and output
5V when the bus data is "1 (H)".
Two types of relations of the bus data and the IC internal OSC/MIX circuits operation are available as shown
below. These relations can be selected by grounding or leaving open Pin 8 (BYP).
BYP: Grounding
Band SW data
MIX circuit
OSC circuit
BS1
BS2
BS3
BS4
VHF
UHF
VHF
UHF
∗
∗
∗
0
O
X
O
X
∗
∗
∗
1
X
O
X
O
BYP: Open
Band SW data
MIX circuit
OSC circuit
BS1
BS2
BS3
BS4
VHF
UHF
VHF
UHF
∗
∗
0
∗
O
X
O
X
∗
∗
1
∗
X
O
X
O
∗: Don't care
O: Operating
X: Not operating
– 13 –
CXA3627ER
Description of Analog Block Operation (See the Electrical Characteristics Measurement Circuit.)
VHF oscillator circuit
• This is the differential amplifier-type oscillator circuit. Pins 13 and 16 are base and Pins 14 and 15 are
collector. Pins 13, 15 and Pins 16, 14 have the in-phase input/output relation respectively.
This circuit is oscillated with the positive feedback applied by connecting the output to the input via the
coupling capacitor and the feedback capacitor.
Oscillation frequency is varied by connecting an LC parallel resonance circuit including a varicap and controlling
the voltage applied to the varicap.
VHF mixer circuit
• The mixer circuit employs a double balanced mixer with little local oscillation signal leakage.
The input format is base input type, with Pin 8 grounded either directly or via a capacitor and the RF signal
input to Pin 7.
(Pin 8 can also be used to select VHF/UHF switching mode with the BS3/BS4 data.)
• The RF signal is fed from the oscillator, converted to IF frequency and output from Pins 4 and 5. Pins 4 and
5 are open collectors, so external power feed is necessary. Also, connect single-tuned filters to Pins 4 and 5.
UHF oscillator circuit
• The oscillator circuit is designed so that two collector ground type Colpitts oscillators perform differential
oscillation operation via an LC resonance circuit including a varicap.
• Resonance capacitance is connected between Pins 17 and 18, Pins 18 and 19, and Pins 19 and 20, and an
LC resonance circuit including a varicap is connected between Pins 17 and 20.
UHF mixer circuit
• This circuit employs a double balanced mixer like the VHF mixer circuit.
The input format is base input type, with Pins 10 and 11 as the RF input pins. The input method can be
selected from balanced input consisting of differential input to Pins 10 and 11 or unbalanced input consisting
of grounding Pin 10 via a capacitor and input to Pin 11.
• Pins 4 and 5 are the mixer outputs. Pins 4 and 5 are open collectors, so external power feed is necessary.
Also, connect single-tuned filters to Pins 4 and 5.
IF amplifier circuit
• Pins 1 and 2 are the IF amplifier inputs, and the input impedance is approximately 1.6kΩ.
• The signals frequency converted by the mixer are output from Pins 4 and 5, and Pins 4 and 5 are connected
to Pins 1 and 2 via capacitors. (An adjacent channel trap circuit can be formed by connecting LC parallel
circuits in place of capacitors.)
• The signal amplified by the IF amplifier is output from Pin 27. The output impedance is approximately 10Ω.
– 14 –
CXA3627ER
Description of PLL Block
This IC is controlled by the I2C bus.
The PLL of this IC performs high-speed phase comparison, providing low reference leak and quick lock-up
time characteristics.
During power on, the power-on reset circuit operates to initialize the frequency data to all "0" and the band
data to all "OFF". Power-on reset is performed when VCC ≥ 3.2V at room temperature (Ta = 25°C).
1) Address setting
Up to four addresses can be selected by the hardware bit settings, so that multiple PLL can exist within one
system.
The responding address can be set according to the ADSW pin voltage.
Address
1
1
0
0
0
MA1
MA0
R/W
Hardware bits
ADSW pin voltage
MA1
MA0
0 to 0.1Vcc
0
0
OPEN or
0.2Vcc to 0.3Vcc
0
1
0.4Vcc to 0.6Vcc
1
0
0.9Vcc to Vcc
1
1
2) Frequency data setting
The VCO lock frequency is obtained according to the following formula.
fosc = 2 × fref × (32M + S)
fosc: local oscillator frequency
fref: phase comparison frequency
M: main divider frequency division ratio
S:
swallow counter frequency division ratio
The variable frequency division ranges of M and S are as follows, and are set as binary.
S < M ≤ 1023
0 ≤ S ≤ 31
– 15 –
CXA3627ER
3) Control format
When performing control for this IC, byte 1 contains the address data, bytes 2 and 3 contain the frequency
data, byte 4 contains the control data, and byte 5 contains the band switch data.
These data are latch transferred in the manner of byte 1, byte 2 + byte 3, and byte 4 + byte 5.
When the correct address is received and acknowledged, the data is recognized as frequency data if the
first bit of the next byte is "0", and as control data and band switch data if this bit is "1".
Also, when data transmission is stopped part-way, the previously programmed data is valid. Therefore, once
the control and band switch data have been programmed, 3-byte commands consisting of the address and
frequency data are possible.
Further, even if the I2C bus stop conditions are not met, data can be input by sending the start conditions
and the new address.
The control format is as shown in the table below.
Slave Receiver
MSB
LSB
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Address byte
1
1
0
0
0
MA1
MA0
0
A
Divider byte1
0
M9
M8
M7
M6
M5
M4
M3
A
Divider byte2
M2
M1
M0
S4
S3
S2
S1
S0
A
Control byte
1
CP
GC
CD
X
R1
R0
OS
A
Band SW byte
X
X
X
X
BS4
BS3
BS2
BS1
A
Mode
X: Don't care
A:
MA0, MA1:
M0 to:
S0 to:
CD:
OS:
CP:
GC:
BS1 to BS4:
R0, R1:
Acknowledge bit
address setting
main divider frequency division ratio setting
swallow counter frequency division ratio setting
charge pump OFF (when "1")
varicap output OFF (when "1")
charge pump current switching (200µA when "1", 50µA when "0")
gain switching (IC gain reduced by 2dB when "1")
band switch control (output PNP transistor ON when "1")
reference divider frequency division ratio setting (See the Reference Divider Frequency
Division Ratio Table.)
Reference Divider Frequency Division Ratio Table
R1
R0
Reference Divider
0
1
256
1
1
128
X
0
160
X: Don't care
– 16 –
CXA3627ER
I2C Bus Timing Chart
tW;STA
SDA
tR
tS;STA
tF
tS;STO
SCL
tH;STA
START
tS;STA
tW;STA
tH;STA
tLOW
tHIGH
tLOW
tHIGH
tS;DAT
CLOCK
= Start setup time
= Start waiting time
= Start hold time
= Low clock pulse width
= High clock pulse width
tH;DAT
DATA CHANGE
tS;DAT
tH;DAT
tS;STO
tR
tF
– 17 –
= Data setup time
= Data hold time
= Stop setup time
= Rise time
= Fall time
STOP
CXA3627ER
Example of Representative Characteristics
Band SW output voltage vs. Output current
(BS1, BS2, BS3, BS4)
Circuit current vs. Supply voltage
70
5.4
Vcc = 5V
68
VHF
UHF
66
5.2
64
Output voltage [V]
Icc – Circuit current [mA]
5.3
62
60
58
56
5.1
5.0
4.9
4.8
54
4.7
52
50
4.7
4.8
4.9
5.0
5.1
5.2
5.3
4.6
0
5.4
3
6
15
Conversion gain vs. Reception frequency
(Untuned input)
Noise figure vs. Reception frequency
(Untuned input, in DSB)
20
fIF = 45MHz
High gain mode
30
UHF
VHF (High)
20
VHF (Low)
10
0
0
15
VHF (High)
VHF (Low)
5
0
0
100 200 300 400 500 600 700 800 900
100 200 300 400 500 600 700 800 900
Reception frequency [MHz]
Next adjacent cross modulation vs. Reception frequency
(Untuned input)
120
100
VHF (High)
UHF
300
VHF (Low)
VHF (High)
Vcc + 5%
Vcc – 5%
(Vcc = 5V)
+B drift [kHz]
200
80
70
60
50
30
Oscillation frequency power supply fluctuation
(PLL off)
400
90
40
UHF
10
Reception frequency [MHz]
110
18
fIF = 45MHz
High gain mode
NF – Noise figure [dB]
CG – Conversion gain [dB]
12
Output current [mA]
40
CM – Cross modulation [dBµ]
9
Vcc – Supply voptage [V]
VHF (Low)
100
UHF
0
–100
fUD = fD + 12MHz
fUD = fD – 12MHz
(100kHz, 30% AM)
–200
20
10
0
0
–300
fIF = 45MHz
High gain mode
–400
0
100 200 300 400 500 600 700 800 900
Reception frequency [MHz]
– 18 –
100 200 300 400 500 600 700 800 900
Oscillation frequency [MHz]
CXA3627ER
Oscillator phase noise vs. Reception frequency (untuned input)
130
fIF = 45MHz
High gain mode
C/N – Oscillator phase noise [dBc/Hz]
120
VHF (Low)
VHF (High)
UHF
110
100
VHF (Low)
90
UHF
VHF (High)
80
70
VHF (Low)
VHF (High)
60
UHF
1kHz offset
10kHz offset
100kHz offset
50
40
0
100
200
300
400
500
600
700
800
900
Reception frequency [MHz]
I/O characteristics (untuned input)
PCS beat characteristics (untuned input)
20
20
High gain mode
10
10
0
fIF
0
IF output level [dBm]
–10
–10
–20
–20
–30
–40
–30
–60
fLocal = 495MHz
fP = 449.25MHz
fc = 452.83MHz
(fP –12dB)
fs = 453.75MHz
(fP –1.7dB)
–70
fIF = 45.75MHz
fBeat = fIF ± 950kHz
fBeat
–50
–40
fRF = 45MHz
High gain mode
fRF = 145MHz (VHF)
fRF = 495MHz (UHF)
–50
–60
–60
–50
–40 –30
–20
–10
0
10
20
RF level [dBm]
–80
–40
–30
–20
–10
0
10
RF level (SG Setting level) [dBm]
– 19 –
20
CXA3627ER
Tuning Response Time
VHF (Low) 95MHz → VHF (High) 395MHz
CP = 0
T = 47.2ms
5.0V/div
Offset 10.0V
–75.0000ms
25.0000ms
125.0000ms
20.0ms/div
CP = 1
T = 15.0ms
5.0V/div
Offset 10.0V
–40.0000ms
10.0000ms
10.0ms/div
– 20 –
60.0000ms
CXA3627ER
UHF 413MHz → UHF 847MHz
CP = 0
T = 63.6ms
5.0V/div
Offset 10.0V
–70.0000ms
30.0000ms
130.0000ms
20.0ms/div
CP = 1
T = 20.2ms
5.0V/div
Offset 10.0V
–40.0000ms
10.0000ms
10.0ms/div
– 21 –
60.0000ms
CXA3627ER
VHF (High) 395MHz → VHF (Low) 95MHz
CP = 0
T = 27.0ms
5.0V/div
Offset 10.0V
–110.0000ms
–10.0000ms
90.0000ms
20.0ms/div
CP = 1
T = 7.2ms
5.0V/div
Offset 10.0V
–45.0000ms
5.0000ms
10.0ms/div
– 22 –
55.0000ms
CXA3627ER
UHF 847MHz → UHF 413MHz
CP = 0
T = 35.6ms
5.0V/div
Offset 10.0V
–110.0000ms
–10.0000ms
90.0000ms
20.0ms/div
CP = 1
T = 14.4ms
5.0V/div
Offset 10.0V
–90.0000ms
10.0000ms
20.0ms/div
– 23 –
110.0000ms
CXA3627ER
IF output spectrum
REF = –10.0dBm
10dB/div
VHF (Low)
fRF = 55MHz
fLO = 100MHz
RF input level: –40dBm
CENTER 45.00100MHz
RES BW 1.0kHz
VBW 10Hz
SPAN 50.00kHz
SWP 30.0s
REF = –10.0dBm
10dB/div
VHF (High)
fRF = 350MHz
fLO = 395MHz
RF input level: –40dBm
CENTER 45.00350MHz
RES BW 1.0kHz
VBW 10Hz
SPAN 50.00kHz
SWP 30.0s
REF = –0.0dBm
10dB/div
UHF
fRF = 800MHz
fLO = 845MHz
RF input level: –40dBm
CENTER 45.00188MHz
RES BW 1.0kHz
VBW 10Hz
– 24 –
SPAN 50.00kHz
SWP 30.0s
CXA3627ER
VHF Input Impedance
j50
j25
0
j100
50
50MHz
7
8
1000p
S11
350MHz
–j25
–j100
–j50
UHF Input Impedance
j50
j25
0
j100
50
10
350MHz
11
1000p
S11
–j25
800MHz
–j50
– 25 –
–j100
CXA3627ER
IF Output Impedance
j50
j25
j100
45MHz
38MHz
0
50
–j25
–j100
–j50
– 26 –
CXA3627ER
Package Outline
Unit: mm
32PIN VQFN (PLASTIC)
0.9 ± 0.1
4.8
0.6 ± 0.1
4.4
24
C
0.05 S
0.7
17
25
16
A
B
PIN1 INDEX
9
(0
.1
5)
0.
6
C
x4
S
1.4
0.1 S A-B C
x4
0.03 ± 0.03
(Stand Off)
0.2 ± 0.01
0.1 S A-B C
0.05 M S A-B C
0.23 ± 0.02
0.4
)
45˚
8
1
9
.3
(0
32
Solder Plating
0.13 ± 0.025
+ 0.09
0.14 – 0.03
TERMINAL SECTION
NOTE: 1) The dimensions of the terminal section apply to the
ranges of 0.1mm and 0.25mm from the end of a terminal.
PACKAGE STRUCTURE
SONY CODE
VQFN-32P-03
EIAJ CODE
P-VQFN32-4.4X4.4-0.4
JEDEC CODE
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
LEAD MATERIAL
COPPER ALLOY
PACKAGE MASS
0.05g
LEAD PLATING SPECIFICATIONS
ITEM
LEAD MATERIAL
SPEC.
COPPER ALLOY
SOLDER COMPOSITION
Sn-Bi Bi:1-4wt%
PLATING THICKNESS
5-18µm
– 27 –
Sony Corporation