CXA3185/3186N All Band TV Tuner IC with On-chip PLL Description The CXA3185/3186N is a monolithic TV tuner IC which integrates local oscillator and mixer circuits for VHF band, local oscillator and mixer circuits for UHF band, an IF amplifier and a tuning PLL onto a single chip, enabling further miniaturization of the tuner. Features • Low noise figure • Low power consumption (5 V, 54 mA typ.) • On-chip tuning PLL (3-wire bus format) • Selection of frequency steps 31.25 kHz, 50 kHz and 62.5 kHz • On-chip 4-output band switch Applications • TV tuners • VCR tuners • CATV tuners Structure Bipolar silicon monolithic IC 30 pin SSOP (Plastic) Absolute Maximum Ratings (Ta = 25 °C) • Supply voltage VCC1,VCC2 –0.3 to +5.5 VCC3 –0.3 to +10.0 • Storage temperature Tstg –55 to +150 • Allowable power dissipation PD 880 V V °C mW (when mounted on a substrate) Operating Conditions • Supply voltage VCC1, VCC2 VCC3 • Operating temperature Topr 4.75 to 5.3 4.75 to 9.45 V V –20 to +75 °C Note) Electrostatic discharge strength is weak, and care should be taken in handling this IC. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E97944-TE CXA3185/3186N Block Diagram and Pin Configuration CL 1 DA 2 CE 3 FMT 4 BVL 5 BVH 6 Input Buffer Shift Register Divider 1/512,640,1024 REF OSC Phase Detector Band SW Driver Charge Pump LOCK Det Divider 14/15bit BU 7 USW 30 VCC3 29 REFOSC 28 CPO 27 CPE 26 LOCK 25 IF OUT 24 GND 23 VCC2 22 UOSCB2 21 UOSCE2 20 UOSCE1 19 UOSCB1 18 VOSC2 17 GND 16 VOSC1 Prescaler 1/8 VCC1 8 V.REG Bias IF AMP MIXout1 Buffer 9 MIXout2 10 GND1 11 MS 12 Buffer UHF OSC VHF MIX VHFin 13 Buffer UHFin1 14 UHFin2 15 UHF MIX —2— VHF OSC CXA3185/3186N Pin Description Pin No. Symbol Pin voltage (V) Equivalent circuit 22 Description VCC2 100k 5k 1 1 CL 22 — Clock input. — Data input. VCC2 100k 5k 2 2 DA 22 VCC2 150k 3 CE 1.25 Enable pin. (when open) 3 50k 4 FMT VCC3 30 5 BVL 20k 4 ON : Vcc3 OFF : 0 5 6 6 BVH 7 4 : Output for FM TRAP. 5 : Power supply output for VL band. 6 : Power supply output for VH band. 7 : Power supply output for UHF band. 7 BU The selected band pin goes High. 8 VCC1 Analog circuit power supply. 9 MIXout1 10 9 Mixer outputs. 10 MIXout2 11 GND1 — — —3— Analog circuit GND. CXA3185/3186N Pin No. Symbol Pin voltage (V) Equivalent circuit VCC2 12 MS 13 VHFin 120k 50k 13 14 12 14 UHFin1 15 3k 15 3k UHFin2 18 16 VOSC1 8 16 VCC1 600 8p 50 3k 18 VOSC2 17 GND 19 UOSCB1 3k 15p 19 20 20 21 22 VCC1 UOSCE1 3k 21 UOSCE2 22 UOSCB2 3k —4— Description Frequency step mode 1.5 selection. Five modes can be (when open) selected according to the applied voltage. 2.3 VHF input. (VHF) The input format is unbalanced 0 input. (UHF) 0 (VHF) 2.3 UHF input. (UHF) The input method can be 0 selected from balanced input (VHF) or unbalanced input. 2.3 (UHF) 3.0 (VHF) 3.1 (UHF) External resonance circuit 3.5 connection for VHF oscillator. (VHF) 5.0 (UHF) — GND 3.2 (VHF) 2.9 (UHF) — (VHF) 2.4 (UHF) External resonance circuit — connection for UHF oscillator. (VHF) 2.4 (UHF) 3.2 (VHF) 2.9 (UHF) CXA3185/3186N Pin No. 23 24 Symbol Equivalent circuit VCC2 GND2 — — VCC1 8 25 Pin voltage Description (V) — PLL circuit power supply. — PLL circuit GND. IFOUT 2.3 40 IF output. 25 VCC2 22 5.0 (Lock) 40k 26 26 LOCK 0.2 (UNLock) VCC2 27 22 CPE LOCK detection. High when locked, Low when unlocked. 0.6 NPN transistor connection for varicap diode drive. 2.0 Charge pump output. Connect a loop filter. 4.3 Crystal connection for reference oscillator. — Power supply for external supply. 200 28 500 28 27 CPO 20k 60k 30p 29 REFOSC 30 VCC3 30p 29 —5— CXA3185/3186N Electrical Characteristics Circuit Current Item Circuit current A Symbol AICCV AICCU Circuit current D DICC See the Electrical Characteristics Measurement Circuit. (VCC=5 V, Ta=25 °C) Measurement conditions VCC1 current, Band switch output open during VHF operation VCC1 current, Band switch output open during UHF operation VCC2 current Min. Typ. Max. Unit 30 41 55 mA 31 42 56 mA 7 11 15 mA Measurement conditions VHF operation fRF = 55 MHz VHF operation fRF = 360 MHz UHF operation fRF = 360 MHz UHF operation fRF = 800 MHz VHF operation fRF = 55 MHz VHF operation fRF = 360 MHz UHF operation fRF = 360 MHz UHF operation fRF = 800 MHz VHF operation fD = 55 MHz, fUD = ±12 MHz VHF operation fD = 360 MHz, fUD = ±12 MHz UHF operation fD = 360 MHz, fUD = ±12 MHz UHF operation fD = 800 MHz, fUD = ±12 MHz 50 Ω load saturation output VHF operation fOSC = 100 MHz ∆f from 3 s to 3 min after switch ON VHF operation fOSC = 405 MHz ∆f from 3 s to 3 min after switch ON UHF operation fOSC = 405 MHz ∆f from 3 s to 3 min after switch ON UHF operation fOSC = 845 MHz ∆f from 3 s to 3 min after switch ON VHF operation fOSC = 100 MHz ∆f when VCC 5 V changes ±5 % VHF operation fOSC = 405 MHz ∆f when VCC 5 V changes ±5 % UHF operation fOSC = 405 MHz ∆f when VCC 5 V changes ±5 % UHF operation fOSC = 845 MHz ∆f when VCC 5 V changes ±5 % Min. 21 22 26 27 Typ. 24 25 29 30 12 11 8.5 9.5 Max. 27 28 32 33 15 14 12.5 13.5 Unit dB dB dB dB dB dB dB dB 97 101 dBµ 96 100 dBµ 92 96 dBµ 88 92 dBµ +5 +10 dBm OSC/MIX/IF Amplifier Block Item Symbol Conversion gain ∗1 CG1 CG2 CG3 CG4 Noise figure ∗1, ∗2 NF1 NF2 NF3 NF4 1 % cross CM1 modulation ∗1, ∗3 CM2 CM3 CM4 Maximum output power Switch ON drift ∗4 Pomax ∆fsw1 ∆fsw2 ∆fsw3 ∆fsw4 Supply voltage drift ∆fst1 ∗4 ∆fst2 ∆fst3 ∆fst4 —6— ±300 kHz ±400 kHz ±400 kHz ±500 kHz ±150 kHz ±250 kHz ±200 kHz ±250 kHz CXA3185/3186N ∗1 Measured value for untuned inputs. ∗2 Noise figure is the direct-reading value of NF meter in DSB. ∗3 Desired signal (fD) input level is –30 dBm. Undesired signal (fUD) is 100 kHz, 30 % AM. The measurement value is undesired signal level, it measured with a spectrum analyzer at S/I=46 dBm. ∗4 Value when the PLL is not operating. PLL Block Item Symbol CL and DA pins “H” level input voltage VIH “L” level input voltage VIL “H” level input current IIH “L” level input current IIL CE pins “H” level input voltage VIHE “L” level input voltage VILE “H” level input current IIHE “L” level input current IILE CPO (charge pump) ICPO Output current LeakCP Leak current LOCK VLOCKH “H” output voltage VLOCKL “L” output voltage REFOSC Oscillator FXTOSC frequency range CXTOSC Input capacitance VXTOSC Drive level BVL, BVH, BU (Band SW) IBS1 Output current VSAT1 Saturation voltage LeakBS1 Leak current FMT (Band SW) Output current Saturation voltage Leak current Bus timing Data setup time Data hold time Enable waiting time Enable setup time Enable hold time Measurement conditions Min. Max. Unit 3 VCC GND 0 –1 1.5 –0.1 –2 V V µA µA 100 –30 VCC 1.5 130 –45 V V µA µA ±75 30 µA nA VCC–0.5 0 VCC 0.5 V V 3 12 MHz 20.5 pF mVp-p 100 0.5 –25 200 3 mA mV µA 75 0.03 –7 150 0.1 mA mV µA VIH = VCC VIL = GND 3 GND VIHE=VCC VILE=GND ±35 When locked When unlocked 17.5 200 When ON When ON Sink current = 20 mA When OFF IBS2 When ON VSAT2 When ON Sink current = 5 mA LeakBS2 When OFF tSD tHD tWE tSE tHE Typ. See Timing Chart on Page 15 See Timing Chart on Page 15 See Timing Chart on Page 15 See Timing Chart on Page 15 See Timing Chart on Page 15 —7— 300 600 300 300 600 ±50 19 400 ns ns ns ns ns CXA3185/3186N Electrical Characteristics Measurement Circuit +30V 22k 8200p 1.2k 47k 0.047µ 33p +5V 47k 2SC2785 3.3µ 47k 1n 2.5ø2.5t 0.5p 0.5p 7p LOCK IF OUT 1T363 3.2ø 5.5t 1n 47k 3.0ø 2.5t 1n 47k BVL 51 BVH 0.5p 150p 1T363 51 47k 1T363 47k XTAL 4MHz 56p 47k 56p 1T362 1n 16p CPE LOCK IFOUT 22 21 20 19 18 17 16 VOSC1 CPO 23 GND REFOSC 24 VOSC2 25 8p UOSCB1 26 4p UOSCE2 27 UOSCB2 28 VCC2 29 GND2 30 VCC3 8p UOSCE1 100p 1n 1p CL DA CE FMT BVL BVH BU VCC1 MIX out1 MIX out2 GND1 MS VHF in UHFin1 UHFin2 CXA3185/3186N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 2k 1n 4.5t 1n 1n 1n 4.5t CLOCK DATA ENABLE 56p FMT BVL BVH BU 100 56p 1n VHF IN 3.3µ 1n +5V —8— UHF IN 47k CXA3185/3186N Description of Functions The CXA3185/3186N is a terrestrial wave broadcast tuner IC which converts frequencies to IF in order to tune and detect only the desired reception frequency of VHF, CATV and UHF band signals. In addition to the mixer, local oscillator and IF amplifier circuits required for frequency conversion to IF, this IC also integrates a PLL circuit for local oscillator frequency control onto a single chip. The functions of the various circuits are described below. 1. Mixer circuit This circuit outputs the frequency difference between the signal input to VHFIN or UHFIN and the local oscillation signal. 2. Local oscillator circuit A VCO is formed by externally connecting an LC resonance circuit composed of a varicap diode and inductance. 3. IF amplifier circuit This circuit amplifies the mixer IF output, and consists of an amplifier stage and low impedance output stage. 4. PLL circuit This PLL circuit fixes the local oscillator frequency to the desired frequency. It consists of a prescaler, main divider, reference divider, phase comparator, charge pump and reference oscillator. The control format supports the 3-wire bus format. The following four modes can be selected according to the combination of the frequency division values of the main and reference dividers. Mode A-0 A-1 A-2 A-3/4 Main divider 15 bit 14 bit 15 bit 15 bit —9— Reference divider 1024 fixed 512 fixed 640 fixed 512 fixed CXA3185/3186N Description of Analog Block Operation (See the Electrical Characteristics Measurement Circuit.) VHF oscillator circuit • This circuit is a differential amplifier type oscillator circuit. Pin 18 is the output and Pin 16 is the input. Oscillation is performed by connecting an LC resonance circuit including a varicap to Pin 18 via coupled capacitance, inputting to Pin 16 with feedback capacitance, and applying positive feedback. • The amplifier between Pins 16 and 18 has an extremely high gain. Therefore, care should be taken to avoid creating parasitic capacitance, resistance or other feedback loops as this may produce abnormal oscillation. VHF mixer circuit • The mixer circuit employs a double balance mixer with little local oscillation signal leakage. The input format is base input type, with Pin 12 grounded and the RF signal input to Pin 13. • The RF signal is inserted from the oscillator, converted to IF frequency and output from Pins 9 and 10. • Pins 9 and 10 are open collectors, so power must be supplied externally. The electric potential of Pins 9 and 10 at this time must be DC 4.0 V or more. UHF oscillator circuit • This oscillator circuit is designed so that two collector ground type Colpitts oscillators perform differential oscillation operation via an LC resonance circuit including a varicap. Connect resonance capacitance which consists of colpitts oscillator between Pins 19 and 20, Pins 20 and 21, and Pins 21 and 22. Then an LC resonance circuit including a varicap diode is connected between Pins 19 and 22. UHF mixer circuit • This circuit employs a double balance mixer like the VHF mixer circuit. The input format is base input type, with Pins 14 and 15 as the RF input pins. The input method can be selected from balanced input consisting of differential input to Pins 14 and 15 or unbalanced input consisting of grounding Pin 14 via a capacitor and input to Pin 15. • Pins 9 and 10 are the mixer outputs. • Pins 9 and 10 are open collectors, so power must be supplied externally. The electric potential of Pins 9 and 10 at this time must be DC 4.0 V or more. IF amplifier circuit • The signals frequency converted by the mixer are output from Pins 9 and 10, and at the same time are AC coupled inside the IC and input to the IF amplifier. • Single-tuned filters are connected to Pins 9 and 10 in order to improve the interference characteristics of the IF amplifier. • The signal amplified by the IF amplifier is output from Pin 25. The output impedance is approximately 75 Ω. —10— CXA3185/3186N Description of PLL Block The PLL on this IC supports the 3-wire bus control format. The serial data is input to the DA, CL and CE pins. The data is loaded to the shift register at the clock rise, and latched at the enable fall. Symbol CE CL DA LOCK 3-wire bus control Enable input Clock input Data input Lock signal output 1) Mode Setting Method The modes for each frequency step are set according to the MS pin voltage. Mode MS pin voltage A-0 A-1 A-2 A-3 A-4 0 to 0.15VCC OPEN 0.45VCC to 0.55VCC 0.65VCC to 0.75VCC 0.85VCC to VCC Main divider 15 bit 14 bit 15 bit 15 bit 15 bit Reference divider 1024 512 640 512 512 Reference frequency∗ Frequency step∗ 3.90625 kHz 7.8125 kHz 6.25 kHz 7.8125 kHz 7.8125 kHz 31.25 kHz 62.5 kHz 50 kHz 62.5 kHz 62.5 kHz Control word length Total 19 bits Total 18 bits Total 19 bits Total 19 bits Total 27 bits ∗ Frequency step is for when X’tal OSC = 4 MHz. 2) Programming • The VCO lock frequency is obtained according to the following formula. fosc = fref × 8 × (32 M + S) fosc : local oscillator frequency fref : reference frequency 8 : prescaler fixed frequency division ratio M : main divider frequency division ratio S : swallow counter frequency division ratio The variable frequency division ranges of M and S are as follows, and are set as binary. 32 ≤ M ≤ 1023 (32 ≤ M ≤ 511 for A-1 mode) 0 ≤ S ≤ 31 • The PLL control data is comprised of the above frequency data and the band switch control data. —11— CXA3185/3186N 2-1) The CXA3185N control format is as follows. 2-1-1 : A-0/A-2/A-3 Modes (19-bit data format) Front bit ←MSB BU FMT BVH BVL M9 M8 M7 M6 M5 2-1-2 : A-1 Mode (18-bit data format) Front bit ←MSB BU FMT BVH BVL M8 M7 2-1-3 : A-4 Mode (27-bit data format) Front bit ←MSB BU FMT BVH BVL M9 M8 M7 X CP T1 CD X R1 R0 M6 M6 X M5 M5 M4 M4 M4 M3 M3 M3 M2 M2 M2 M1 M1 M1 M0 M0 M0 S4 S4 S4 S3 S3 S3 S2 LSB→ S1 S0 S2 LSB→ S1 S0 S2 LSB→ S1 S0 ∗) X: Don’t care S0 to : M0 to : BVL : BVH : FMT : BU : CP : T1 : CD : R0, R1: swallow counter frequency division ratio setting main divider frequency division ratio setting VL band switch control VH band switch control FM trap switch control UHF band switch control charge pump current switching test mode selection charge pump OFF reference divider frequency division ratio setting (output PNP Tr ON when “1”) (output PNP Tr ON when “1”) (output PNP Tr ON when “1”) (output PNP Tr ON when “1”) (200 µA when “1”, 50 µA when “0”) (when “1”) (when “1”) (See the table below.) Reference Divider Frequency Division Ratio Table R1 0 1 X R0 1 1 0 Reference divider 1024 512 640 ∗) X: Don’t care —12— CXA3185/3186N 2-2) The CXA3186N control format is as follows. The BU and FMT data order is switched for the CXA3185N. In this case the control format is as follows. 2-2-1 : A-0/A-2/A-3 Modes (19-bit data format) Front bit ←MSB FMT BU BVH BVL M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 S4 S3 S2 S1 LSB→ S0 2-2-2 : A-1 Mode (18-bit data format) Front bit ←MSB FMT BU BVH BVL M8 M7 M6 M5 M4 M3 M2 M1 M0 S4 S3 S2 S1 LSB→ S0 2-2-3 : A-4 Mode (27-bit data format) Front bit ←MSB FMT BU BVH BVL M9 M8 M7 X CP T1 CD X R1 R0 M6 X M5 M4 M3 M2 M1 M0 S4 S3 S2 S1 LSB→ S0 ∗) X: Don’t care S0 to : M0 to : BVL : BVH : FMT : BU : CP : T1 : CD : R0, R1: swallow counter frequency division ratio setting main divider frequency division ratio setting VL band switch control VH band switch control FM trap switch control UHF band switch control charge pump current switching test mode selection charge pump OFF reference divider frequency division ratio setting (output PNP Tr ON when “1”) (output PNP Tr ON when “1”) (output PNP Tr ON when “1”) (output PNP Tr ON when “1”) (200 µA when “1”, 50 µA when “0”) (when “1”) (when “1”) (See the table below.) Reference Divider Frequency Division Ratio Table R1 R0 Reference divider 0 1 1024 1 1 512 X 0 640 ∗) X: Don't care —13— CXA3185/3186N 3) 3-wire Bus Data Format A-1 Mode (18-bit data format) Band switch data BU /FMT FMT /BU Frequency data BVH BVL M8 M7 M6 M5 M4 M3 M2 M1 M0 S4 S3 S2 S1 S0 DATA 1 4 5 18 CLOCK ENABLE A-0/A-2/A-3 Modes (19-bit data format) Band switch data BU /FMT FMT /BU Frequency data BVH BVL M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 S4 S3 S2 S1 S0 DATA 1 4 5 19 CLOCK ENABLE A-4 Mode (27-bit data format) Band switch data BU /FMT FMT /BU Frequency data BVH BVL M9 M8 S3 S2 Test data S1 S0 X 19 20 CP T1 CD X R1 R0 X DATA 1 4 5 CLOCK ENABLE —14— 27 CXA3185/3186N 4) Bus Timing Chart tSD DATA 3V 1.5V 3V 1.5V CLOCK ENABLE tHD 3V 1.5V tWE tSE tHE tSD = Data setup time tHD = Data hold time tSE = Enable setup time tHE = Enable hold time tWE = Enable waiting time —15— CXA3185/3186N Circuit current vs. Supply voltage 1 Circuit current vs. Supply voltage 2 15 45 DICC - Circuit current [mA] AICC - Circuit current [mA] UHF VHF 40 35 4.7 4.8 4.9 5.0 5.2 5.1 5.3 10 5 5.4 4.7 4.8 VCC1 - Supply voltage [V] Band SW output voltage vs. Output current (BU, BVH, BVL) 9.2 9.0 4.9 5.0 5.1 5.2 5.3 5.4 VCC2 - Supply voltage [V] Band SW output voltage vs. Output current (FMT) 9.2 9.0 VCC3=9V VCC3=9V 8.8 Output voltage [V] Output voltage [V] 8.8 8.6 5.0 VCC3=5V 4.8 VCC3=5V 4.6 0 5 10 15 20 4.4 25 Output current [mA] I/O characteristics (Untuned input) 0 –20 fRF=100MHz (VHF) fRF=450MHz (UHF) fIF is both f=45MHz –40 –60 –60 –50 –40 –30 0 1 2 3 4 Output current [mA] 20 IF output level [dBm] 5.0 4.8 4.6 4.4 8.6 –20 –10 0 10 RF input level [dBm] —16— 5 6 CXA3185/3186N 30 UHF VHF (Low) VHF (High) 25 Noise figure vs. Reception frequency (Untuned input, in DSB) 20 fIF=45MHz NF - Noise figure [dB] CG - Conversion gain [dB] Conversion gain vs. Reception frequency (Untuned input) 40 fIF=45MHz 35 20 15 10 15 VHF (Low) VHF (High) 10 UHF 5 5 0 0 0 100 200 300 400 500 600 700 800 900 0 100 200 300 400 500 600 700 800 900 Reception frequency [MHz] Next adjacent cross modulation vs. Reception frequency (Untuned input) 120 Oscillation frequency power supply fluctuation (PLL off) 400 VCC+5% VCC–5% (VCC=5V) 300 100 200 80 +B drift [kHz] CM - Cross modulation [dBµ] Reception frequency [MHz] fIF=45MHz fUD=fD+12MHz fUD=fD–12MHz (100kHz, 30% AM) 60 40 VHF (High) VHF (Low) 100 UHF 0 –100 –200 20 0 –300 0 –400 100 200 300 400 500 600 700 800 900 0 Reception frequency [MHz] Oscillation frequency [MHz] PCS beat characteristics +20 +10 fIF 0 IF output level [dBm] –10 –20 –30 –40 fLocal=129MHz fP=83.25MHz fC=86.83MHz, (fP–12dB) fS=87.75MHz, (fP–1.7dB) fIF=45.75MHz fBeat=fIF±920kHz –50 fBeat –60 –70 –80 –30 –20 –10 100 200 300 400 500 600 700 800 900 0 +10 SG output level [dBm] (fP level) —17— +20 CXA3185/3186N Tuning Response Time VHF (Low) 95MHz → VHF (High) 395MHz 30 T=70ms Varicap voltage [V] 20 10 0 5.0V/div offset 10.0V –90,0000ms 10,0000ms 20.0ms/div 110,000ms UHF 413MHz → UHF 847MHz 30 T=70ms Varicap voltage [V] 20 10 0 5.0V/div offset 10.0V –90,0000ms 10,0000ms 20.0ms/div —18— 110,000ms CXA3185/3186N IF output spectrum RL=0dBm 10dB/div VHF (Low) fRF=55MHz fLO=100MHz IF output [dBm] RF input level : –40dBm CENTER 45.0MHz RES BW 1.0kHz VBW 10Hz IF output spectrum SPAN 100.0kHz SWP 30.0s RL=0dBm 10dB/div VHF (High) fRF=350MHz fLO=395MHz IF output [dBm] RF input level : –40dBm CENTER 45.0MHz RES BW 1.0kHz VBW 10Hz —19— SPAN 100.0kHz SWP 30.0s CXA3185/3186N IF output spectrum RL=0dBm 10dB/div UHF (Low) fRF=800MHz fLO=845MHz IF output [dBm] RF input level : –40dBm CENTER 45.0MHz RES BW 1.0kHz VBW 10Hz —20— SPAN 100.0kHz SWP 30.0s CXA3185/3186N VHF Input Impedance j50 50MHz 50 VHFin 0 j100 BYP j25 12 13 1000p S11 350MHz –j25 –j100 –j50 UHF Input Impedance j50 UHFin2 0 UHFin1 j100 j25 14 15 50 1000p S11 350MHz 800MHz –j25 –j50 —21— –j100 CXA3185/3186N IF Output Impedance j50 j25 0 j100 50 –j25 45MHz –j100 –j50 —22— CXA3185/3186N Package Outline Unit : mm 30PIN SSOP (PLASTIC) + 0.2 1.25 – 0.1 ∗9.7 ± 0.1 1 + 0.1 0.22 – 0.05 7.6 ± 0.2 16 ∗5.6 ± 0.1 30 0.10 A 15 + 0.05 0.15 – 0.02 0.65 0.13 M 0.5 ± 0.2 0.1 ± 0.1 0° to 10° NOTE: Dimension “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE SSOP-30P-L01 LEAD TREATMENT SOLDER/PALLADIUM PLATING EIAJ CODE SSOP030-P-0056 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.1g JEDEC CODE NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). —23—