CXA3250AN All Band TV Tuner IC with On-chip PLL For the availability of this product, please contact the sales office. Description The CXA3250AN is a monolithic TV tuner IC which integrates local oscillator and mixer circuits for VHF band, local oscillator and mixer circuits for UHF band, an IF amplifier and a tuning PLL onto a single chip, enabling further miniaturization of the tuner. Features • Superior cross modulation • Balanced UHF oscillator (4 pins) with excellent oscillation stability • Supports both I2C and 3-wire bus modes • Automatic identification of 18, 19 or 27-bit control (during 3-wire bus mode) • On-chip A/D converter (during I2C bus mode) • On-chip high voltage drive transistor for charge pump • Reference frequency selectable from 31.25, 50 or 62.5 kHz (when using a 4 MHz crystal) • Low-phase noise synthesizer • On-chip 4-output band switch (supports output voltages from 5 to 9 V) 30 pin SSOP (Plastic) Absolute Maximum Ratings (Ta=25 °C) • Supply voltage VCC1, VCC2 –0.3 to +5.5 V VCC3 –0.3 to +10.0 V • Storage temperature Tstg –55 to +150 °C • Allowable power dissipation 580 mW PD (when mounted on a printed circuit board) Operating Conditions • Supply voltage VCC1, VCC2 4.75 to 5.30 VCC3 4.75 to 9.45 • Operating temperature Topr –25 to +75 V V °C Applications • TV tuners • VCR tuners • CATV tuners Structure Bipolar silicon monolithic IC This IC has the pins whose electrostatic discharge strength is weak as the operating frequency is high and the high-frequency process is used for this IC. Take care of handling the IC. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E99866-TE CXA3250AN Block Diagram and Pin Configuration 30 VCC3 CL 1 DA 2 ADSW /CE 3 BS3 4 Shift Register Divider 1/64, 80, 128 REF OSC 29 REFOSC ADC BS1 5 BS2 6 BS4 BUS Interface Phase Detector Band SW Driver Programable Divider 14/15bit 7 VSW VCC1 8 LOCK 26 /ADC 23 VCC2 Buffer MIXout1 9 22 UOSCB2 MIXout2 10 GND1 11 Buffer VHFin 13 LOCK Det 27 VT 24 GND2 Bias IF AMP BYP/MS 12 28 CPO 25 IFOUT Mode Select V.REG Charge Pump UHF OSC VHF MIX 21 UOSCE2 20 UOSCE1 19 UOSCB1 18 VOSC2 Buffer UHFin1 14 UHFin2 15 VHF OSC 17 GND 16 VOSC1 VHF UHF MIX —2— CXA3250AN Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Symbol CL DA CE/ADSW BS3 BS1 BS2 BS4 VCC1 MIXOUT1 MIXOU2 GND1 BYP/MS VHFIN UHFIN1 UHFIN2 VOSC1 GND VOSC2 UOSCB1 UOSCE1 UOSCE2 UOSCB2 VCC2 GND2 IFOUT LOCK/ADC VT CPO REFOSC VCC3 Description CLOCK/SCL (I2C bus) DATA/SDA (I2C bus) Enable/address selection (I2C bus) Band switch output 3 Band switch output 1 Band switch output 2 Band switch output 4 Analog circuit VCC MIX output MIX output Analog circuit GND VHF input GND and control bus switching VHF input UHF input UHF input VHF oscillator (base input) GND VHF oscillator (collector output) UHF oscillator (base pin) UHF oscillator (emitter pin) UHF oscillator (emitter pin) UHF oscillator (base pin) PLL circuit VCC PLL circuit GND IF output LOCK signal output/ADC input (I2C bus) VC drive voltage output (open collector) Charge pump output (loop filter connection) Crystal connection Band switch power supply —3— CXA3250AN Pin Description and Equivalent Circuit Pin No. Symbol Pin voltage [V] Equivalent circuit Description 23 1 CL — Clock input. 40k 1 23 2 DA — 2 Data input. 40k 2.5p 20 I2C bus setting : Address selection. Bits 1 and 2 of the address byte are controlled. 3-wire bus setting : Enable input. 23 150k 3 ADSW/CE 1.25 (when open) 3 50k 5p 30 4 BS3 4 7 7 BS4 Band switch outputs. The pin corresponding to the selected band goes High. ON : 4.8 OFF : 0.0 30 5 BS1 5 6 6 BS2 8 VCC1 12k 25k — — —4— Analog circuit power supply. CXA3250AN Pin No. Symbol Pin voltage [V] 9 MIXOUT1 — 10 MIXOUT2 — 11 GND1 — Equivalent circuit 9 12 13 14 15 16 BYP/MS VHFin UHFin1 UHFin2 VOSC1 18 VOSC2 17 GND 3.8 during VHF reception 3.8 during UHF reception 2.6 during VHF reception 0.1 during UHF reception 2.6 during UHF reception 0.1 during VHF reception 2.6 during UHF reception 0.1 during VHF reception 2.1 during VHF reception 2.3 during UHF reception 4.2 during VHF reception 5.0 during UHF reception — Description 10 Mixer output. These pins output the signal with open collector, and they must be connected to the power supply via the load. — Analog circuit GND. 8 23 15p 24k Pin 12 : VHF input grounding and control bus switching. 76k Pin 13 : VHF input. Input format is the unbalanced input. 13 3k 3k 12 8 UHF inputs. Input the signal to Pins 14 and 15 symmetrically or ground either of Pin 14 or 15 with the capacitor and input the signal to the rest. 14 15 3k 3k 8 400 18 50 16 3k 3k — —5— External resonance circuit connection for VHF oscillator. GND for separating the analog and PLL systems. CXA3250AN Pin No. Symbol 19 UOSCB1 20 UOSCE1 21 UOSCE2 22 UOSCB2 23 24 VCC2 GND2 Pin voltage [V] 2.1 during UHF reception 2.3 during VHF reception 1.4 during UHF reception 1.8 during VHF reception 1.4 during UHF reception 1.8 during VHF reception 2.1 during UHF reception 2.3 during VHF reception — — Equivalent circuit Description 8 22 21 20 19 3k External resonance circuit connection for UHF oscillator. 3k — — PLL circuit power supply. PLL circuit GND. 8 25 IFOUT 2.7 IF output. 25 23 26 LOCK/ADC — 250 26 5k 500k —6— I2C bus setting : 5-level A/D converter input. 3-wire bus setting : Lock detection. Low when locked, High when unlocked. CXA3250AN Pin No. 27 Symbol VT Pin voltage [V] — Equivalent circuit Description Varicap drive voltage output. This pin outputs the signal with open collector, and this must be connected to the tuning power supply via the load. 23 28 27 70 28 CPO Charge pump output. Connects the loop filter. 2.0 60k 30p 29 29 REFOSC 30 VCC3 Crystal connection for reference oscillator. 4.3 — 30p — —7— Power supply for external supply. CXA3250AN Electrical Characteristics Circuit Current Item Symbol Circuit current A AICCV AICCU Circuit current D DICC (VCC=5 V, Ta=25 °C) Measurement conditions VCC1 current, band switch output open during VHF operation VCC1 current, band switch output open during UHF operation VCC2 current Min. Typ. Max. Unit 38 52 70 mA 39 53 71 mA 10 16 22 mA Measurement conditions VHF operation fRF=55 MHz VHF operation fRF=360 MHz UHF operation fRF=360 MHz UHF operation fRF=800 MHz VHF operation fRF=55 MHz VHF operation fRF=360 MHz UHF operation fRF=360 MHz UHF operation fRF=800 MHz VHF operation fD=55 MHz, fUD=±12 MHz VHF operation fD=360 MHz, fUD=±12 MHz UHF operation fD=360 MHz, fUD=±12 MHz UHF operation fD=800 MHz, fUD=±12 MHz Min. 18 19 22.5 24 Typ. 21 22 25.5 27 12 11 10 11 Max. 24 25 28.5 30 15 14 13 14 Unit dB dB dB dB dB dB dB dB 100 104 dBµ 99 103 dBµ 96 100 dBµ 90 94 dBµ +8 +11 dBm OSC/MIX/IF Amplifier Block Item Conversion gain Noise figure ∗1, ∗2 1 % cross modulation ∗1, ∗3 Symbol CG1 CG2 CG3 CG4 NF1 NF2 NF3 NF4 CM1 CM2 CM3 CM4 Maximum output Pomax power Switch ON drift ∗4 ∆ fsw1 ∆ fsw2 ∆ fsw3 ∆ fsw4 50 Ω load saturation output VHF operation fOSC=100 MHz ∆ f from 3 s to 3 min after switch ON VHF operation fOSC=405 MHz ∆ f from 3 s to 3 min after switch ON UHF operation fOSC=405 MHz ∆ f from 3 s to 3 min after switch ON UHF operation fOSC=845 MHz ∆ f from 3 s to 3 min after switch ON —8— ±300 kHz ±600 kHz ±350 kHz ±350 kHz CXA3250AN Item Supply voltage drift Symbol ∗4 ∆ fst1 ∆ fst2 ∆ fst3 ∆ fst4 Oscillator phase noise Reference leak Lock-up time C/N V C/N U REFL LUT 1 LUT 2 Measurement conditions VHF operation fOSC=100 MHz ∆ f when VCC 5 V changes ±5 % VHF operation fOSC=405 MHz ∆f when VCC 5 V changes ±5 % UHF operation fOSC=405 MHz ∆ f when VCC 5 V changes ±5 % UHF operation fOSC=845 MHz ∆f when VCC 5 V changes ±5 % 10 kHz offset 10 kHz offset Phase comparison frequency of 62.5 kHz, CP : 1 VHF operation fOSC=95 MHz ⇔ fOSC=395 MHz CP : 1 UHF operation fOSC=413 MHz ⇔ fOSC=847 MHz CP : 1 Min. Typ. Max. Unit ±200 kHz ±250 kHz ±150 kHz ±150 kHz 82 78 dBc/Hz 55 dB 24 70 ms 36 70 ∗1 Value measured with untuned input. ∗2 NF meter direct-reading value (DSB measurement). ∗3 Value with a desired reception signal input level of –30 dBm, an interference signal of 100 kHz/30 % AM, and an interference signal level where S/I=46 dB measured with a spectrum analyzer. ∗4 Value when the PLL is not operating. —9— CXA3250AN PLL Block Item CL, DA and CE pins “H” level input voltage “L” level input voltage “H” level input current “L” level input current CE input “H” level input voltage “L” level input voltage “H” level input current “L” level input current SDA output “H” output leak current “L” output voltage CPO (charge pump) Output current 1 Leak current 1 Output current 2 Leak current 2 VT (VC voltage output) Maximum output voltage Minimum output voltage LOCK “H” output voltage “L” output voltage REFOSC Oscillation frequency range Input capacitance Negative resistance Band SW Output current Saturation voltage Leak current Bus timing (I2C bus) SCL clock frequency Start waiting time Start hold time “L” hold time “H” hold time Start setup time Data hold time Data setup time Symbol Measurement conditions Min. Typ. Max. Unit VIH 3 VCC VIL IIH IIL GND 0 –0.3 1.5 –0.1 –4 V V µA µA –100 35 VCC 1.5 –200 100 V V µA µA 5 0.4 µA V ±75 30 ±300 100 µA nA µA nA 33 0.8 V V VCC–0.5 0 VCC 0.5 V V 3 22 24 –2.0 12 26 –1.0 MHz pF kΩ 120 0.5 –25 240 3 mA mV µA 400 kHz ns ns ns ns ns ns ns VIH=VCC VIL=GND VIH VIL IIH IIL 3 GND VIH=VCC VIL=GND ISDALK VSDAL Vin=5.5 V Iout=–3 mA ICPO1 LeakCP1 ICPO2 LeakCP2 Byte4/bit6=0 Byte4/bit6=0 Byte4/bit6=1 Byte4/bit6=1 GND ±35 ±50 ±140 ±200 VTH VTL VLOCKH VLOCKL 0.5 When locked When unlocked FXTOSC CXTOSC RNEG Crystal source impedance IBS VSAT LeakBS When ON When ON Source current=20 mA When OFF fSCL tWSTA tHSTA tLOW tHIGH tSSTA tHDAT tSDAT 0 1300 600 1300 600 600 0 600 —10— 900 CXA3250AN PLL Block Item Rise time Fall time Stop setup time Bus timing (3-wire bus) Data setup time Data hold time Enable waiting time Enable setup time Enable hold time Symbol tR tF tSSTO Measurement conditions tSD tHD tWE tSE tHE —11— Min. Typ. Max. 300 300 600 Unit ns ns ns 300 600 300 300 600 ns ns ns ns ns CXA3250AN Electrical Characteristics Measurement Circuit (I2C bus control) +30V 22k 8200p 1.2k 6.8k 0.047µ 100p 33p +5V 2.2µ 47k 1n 47k 2.6φ 2.5t ADC in IF OUT 1n 47k 51 BVL 3.2φ 2.5t 1n 47k 51 BVH 0.75p 0.5p 0.5p 1T363 3.2φ 5.5t 150p 1T363 47k 1T363 7p XTAL 4MHz 47k 47k 1T362 56p 1n REFOSC CPO VT LOCK/ADC IFOUT GND2 23 22 21 20 19 18 17 16 VOSC1 24 GND 25 VOSC2 26 20 16p 6p UOSCE1 27 2p UOSCE2 28 UOSCB2 29 VCC2 30 VCC3 6p UOSCB1 100p 1n 1p 56p CL DA CE/ADSW BS3 BS1 BS2 BS4 VCC1 MIX out1 MIX out2 GND1 BYP/MS VHF in UHF in1 UHF in2 CXA3250AN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 2k 1n 4.5t SCL 1n 1n 4.5t SDA ADSW 56p 56p FMT BVL BVH BU 1n 100 1n 2.2µ +5V —12— VHF IN UHF IN 47k CXA3250AN Electrical Characteristics Measurement Circuit (3-wire bus control) +30V 22k 8200p 1.2k 6.8k 0.047µ 100p 33p +5V 2.2µ 47k 1n 47k 2.6φ 2.5t LOCK IF OUT 1n 47k 51 BVL 3.2φ 2.5t 1n 47k 51 BVH 0.75p 0.5p 0.5p 1T363 3.2φ 5.5t 150p 1T363 47k 1T363 7p XTAL 4MHz 47k 47k 1T362 56p 1n REFOSC CPO VT LOCK/ADC IFOUT GND2 23 22 21 20 19 18 17 16 VOSC1 24 GND 25 VOSC2 26 20 16p 6p UOSCE1 27 2p UOSCE2 28 UOSCB2 29 VCC2 30 VCC3 6p UOSCB1 100p 1n 1p 56p CL DA CE/ADSW BS3 BS1 BS2 BS4 VCC1 MIX out1 MIX out2 GND1 BYP/MS VHF in UHF in1 UHF in2 CXA3250AN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 2k 1n 4.5t SCL SDA 1n 1n 1n 4.5t CE 56p 56p FMT BVL BVH BU 1n 100 1n 2.2µ +5V —13— VHF IN UHF IN 47k CXA3250AN Application Circuit (I2C bus control) +30V +5V 22k 100 39k SWD 10k 4.7n 1n 82n 2.2n 10k 2p 1.2k 3.2φ 1n 5.5t SWD 47k 150p 1n 3.2φ 2.5t 0.5p 47k 1.2k 10k 10k 2.2φ 1.5t BVL BVH 330p ADC IN IF OUT 1T363 0.5p 1T363 10k 15p XTAL 4MHz 3.3µ 1n 100p 10k 2p 100p 1T362 20p 1n 20 REFOSC CPO VT LOCK/ADC IFOUT GND2 23 22 21 20 19 18 17 16 VOSC1 24 GND 25 VOSC2 26 6p UOSCE1 27 5p UOSCE2 28 UOSCB2 29 VCC2 30 VCC3 16p UOSCB1 100p CL DA CE/ADSW BS4 BS3 BS2 BS1 VCC1 MIX out1 MIX out2 GND1 BYP/MS VHF in UHF in1 UHF in2 CXA3250AN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 2k 1n 4.5t CL DA 1n 1n 4.5t ADSW 56p 56p FMT BVL BVH BU 100 3.3µ 1n VHF IN UHF IN 1n +5V Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. —14— CXA3250AN Application Circuit (3-wire bus control) +30V +5V 22k 100 39k SWD 10k 4.7n 1n 82n 2.2n 10k 2p 1.2k 3.2φ 1n 5.5t SWD 47k 150p 1n 3.2φ 2.5t 0.5p 47k 1.2k 10k 10k 2.2φ 1.5t BVL BVH 330p LOCK IF OUT 10 1T363 0.5p 1T363 10k 15p XTAL 4MHz 3.3µ 1n 100p 10k 2p 100p 1T362 20p 1n 20 REFOSC CPO VT LOCK/ADC IFOUT GND2 23 22 21 20 19 18 17 16 VOSC1 24 GND 25 VOSC2 26 6p UOSCE1 27 5p UOSCE2 28 UOSCB2 29 VCC2 30 VCC3 16p UOSCB1 100p CL DA CE/ADSW BS4 BS3 BS2 BS1 VCC1 MIX out1 MIX out2 GND1 BYP/MS VHF in UHF in1 UHF in2 CXA3250AN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 2k 1n 4.5t CL DA 1n 1n 1n 4.5t CE 56p 56p FMT BVL BVH BU 100 3.3µ 1n VHF IN UHF IN 1n +5V Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. —15— CXA3250AN Description of Functions The CXA3250AN is a ground wave broadcast tuner IC which converts frequencies to IF in order to tune and detect only the desired reception frequency of VHF, CATV and UHF band signals. In addition to the mixer, local oscillation and IF amplifier circuits required for frequency conversion to IF, this IC also integrates a PLL circuit for local oscillation frequency control onto a single chip. The functions of the various circuits are described below. 1. Mixer circuit This circuit outputs the frequency difference between the signal input to VHFIN or UHFIN and the local oscillation signal. 2. Local oscillation circuit A VCO is formed by externally connecting an LC resonance circuit composed of a varicap diode and inductance. 3. IF amplifier circuit This circuit amplifies the mixer IF output, and consists of an amplifier stage and low impedance output stage. 4. PLL circuit This PLL circuit fixes the local oscillation frequency to the desired frequency. It consists of a programmable divider, reference divider, phase comparator, charge pump and reference oscillator. The control format supports both the I2C bus and 3-wire bus formats. During I2C bus control, the frequency steps of 31.25, 50 or 62.5 kHz can be selected by the data-based reference divider frequency division setting value. During 3-wire bus control, these frequency steps can be selected by the combination of the communication word length (18 or 19 bits) and the voltage applied to the BYP/MS pin. 5. Band switch circuit The CXA3250AN has four sets of built-in PNP transistors for switching between the VL, VH and UHF bands and for switching the FM trap, etc. These PNP transistors can be controlled by the bus data. The emitters for these PNP transistors are connected to an independent power supply pin (VCC3) from the oscillator, mixer and PLL circuits, and support either 5 V or 9 V as the RF amplifier power supply. —16— CXA3250AN Description of Analog Block Operation (See the Electrical Characteristics Measurement Circuit.) VHF oscillator circuit • This circuit is a differential amplifier type oscillator circuit. Pin 18 is the output and Pin 16 is the input. Oscillation is performed by connecting an LC resonance circuit including a varicap to Pin 18 via coupled capacitance, inputting to Pin 16 with feedback capacitance, and applying positive feedback. • The amplifier between Pins 16 and 18 has an extremely high gain. Therefore, care should be taken to avoid creating parasitic capacitance, resistance or other feedback loops as this may produce abnormal oscillation. VHF mixer circuit • The mixer circuit employs a double balanced mixer with little local oscillation signal leakage. The input format is base input type, with Pin 12 grounded via a capacitor and the RF signal input to Pin 13. (Pin 12 can also be used to switch the PLL mode according to the applied DC voltage value.) • The RF signal is fed from the oscillator, converted to IF frequency and output from Pins 9 and 10. UHF oscillator circuit • This oscillator circuit is designed so that two collector ground type Colpitts oscillators perform differential oscillation operation via an LC resonance circuit including a varicap. • Resonance capacitance is connected between Pins 19 and 20, Pins 20 and 21, and Pins 21 and 22, and an LC resonance circuit including a varicap is connected between Pins 19 and 22. UHF mixer circuit • This circuit employs a double balanced mixer like the VHF mixer circuit. The input format is base input type, with Pins 14 and 15 as the RF input pins. The input method can be selected from balanced input consisting of differential input to Pins 14 and 15 or unbalanced input consisting of grounding Pin 14 via a capacitor and input to Pin 15. • Pins 9 and 10 are the mixer outputs. IF amplifier circuit • The signals frequency converted by the mixer are output from Pins 9 and 10, and at the same time are AC coupled inside the IC and input to the IF amplifier. • Single-tuned filters are connected to Pins 9 and 10 in order to improve the interference characteristics of the IF amplifier. • The signal amplified by the IF amplifier is output from Pin 25. The output impedance is approximately 75 Ω. —17— CXA3250AN Description of PLL Block This IC supports both I2C bus and 3-wire bus control. The I2C bus conforms to the standard I2C bus format, and bidirectional bus control is possible consisting of a write mode in which various data are received and a read mode in which various data are sent. The 3-wire bus is equipped with an 18- or 19-bit auto identify function, and the frequency step can be switched according to the voltage applied to the BYP/MS pin. The PLL of this IC does not have a fixed frequency division circuit and performs high-speed phase comparison, providing low reference leak and quick lock-up time characteristics. During power-on (VCC2), the power-on reset circuit operates to initialize the frequency data to all “0” and the band data to all “OFF”. Power-on reset is performed when Vcc2=2.5 V at room temperature (Ta=25 °C). Pin Function Table Symbol CL DA ADSW/CE LOCK/ADC I2C bus SCL input SDA I/O Address selection ADC input 3-wire bus CLOCK input DATA input ENABLE input LOCK output 1.) PLL Mode Setting Method The selected control bus is set according to the BYP/MS pin (Pin 12) voltage. BYP/MS pin GND OPEN VCC Control bus I2C bus 3-wire bus 3-wire bus During 3-wire bus control, the transferred bit length (18, 19 or 27 bits) is automatically identified. During 18- or 19-bit transfer, the frequency steps in the table below are set according to the combination of the BYP/MS pin voltage and the bit length. This IC does not have a fixed frequency division circuit, so the phase comparison frequency becomes the frequency step. BYP/MS pin voltage OPEN OPEN OPEN or VCC 27 Selectable from 64, 80 or 128 Phase comparison frequency 62.5 kHz 31.25 kHz 62.5 kHz/ 50.0 kHz/ 31.25 kHz VCC VCC 18 19 80 80 50.0 kHz 50.0 kHz Transfer bit length 18 19 Reference divider 64 128 Frequency step∗ 62.5 kHz 31.25 kHz 62.5 kHz/ 50.0 kHz/ 31.25 kHz 50.0 kHz 50.0 kHz ∗ Phase comparison frequency and frequency step are for when the crystal oscillation=4 MHz. —18— CXA3250AN 2.) Programming The VCO lock frequency is obtained according to the following formula. fosc=fref × (32 M + S) fosc : local oscillator frequency fref : phase comparison frequency M : main divider frequency division ratio S : swallow counter frequency division ratio The variable frequency division ranges of M and S are as follows, and are set as binary. S < M ≤ 1023 (S < M ≤ 511 during 18-bit transfer) 0 ≤ S ≤ 31 3.) I2C Bus Control This IC conforms to the standard I2C bus format, and bidirectional bus control is possible consisting of a write mode in which various data are received and a read mode in which various data are sent. Write and read modes are recognized according to the setting of the final bit (R/W bit) of the address byte. Write mode is set when the R/W bit is “0” and read mode is set when the R/W bit is “1”. —19— CXA3250AN 3-1) Address settings Up to four addresses can be selected by the hardware bit settings, so that multiple PLL can exist within one system. The responding address can be set according to the ADSW/CE pin voltage. Address 1 1 0 0 0 MA1 MA0 R/W Hardware bits CE pin voltage 0 to 0.1 VCC OPEN or 0.2 VCC to 0.3 VCC 0.4 VCC to 0.6 VCC 0.9 VCC to VCC MA1 0 MA0 0 0 1 1 1 0 1 3-2) Write mode Write mode is used to receive various data. In this mode, byte 1 contains the address data, bytes 2 and 3 contain the frequency data, byte 4 contains the control data, and byte 5 contains the band switch data. These data are latch transferred in the manner of byte 1, byte 2 + byte 3, and byte 4 + byte 5. When the correct address is received and acknowledged, the data is recognized as frequency data if the first bit of the next byte is “0”, and as control data and band switch data if this bit is “1”. Also, when data transmission is stopped part-way, the previously programmed data is valid. Therefore, once the control and band switch data have been programmed, 3-byte commands consisting of the address and frequency data are possible. Further, even if the I 2C bus stop conditions are not met, data can be input by sending the start conditions and the new address. —20— CXA3250AN The control format is as shown in the table below. Write-mode : Slave Receiver MODE Address byte Divider byte 1 Divider byte 2 Control byte Band SW byte MSB bit7 1 0 M2 1 X bit6 1 M9 M1 CP X bit5 0 M8 M0 0 X bit4 0 M7 S4 CD X bit3 0 M6 S3 X BS4 bit2 MA1 M5 S2 R1 BS3 X : Don’t care A : MA0, MA1 : M0 to : S0 to : CD : OS : CP : BS1 to BS4 : R0, R1 : Acknowledge bit address setting main divider frequency division ratio setting swallow counter frequency division ratio setting charge pump OFF (when “1”) varicap output OFF (when “1”) charge pump current switching (200 µA when “1”, 50 µA when “0”) band switch control (output PNP transistor ON when “1”) reference divider frequency division ratio setting. See the Reference Divider Frequency Division Ratio Table. Reference Divider Frequency Division Ratio Table R1 0 1 X R0 1 1 0 Reference divider 128 64 80 X : Don’t care —21— bit1 MA0 M4 S1 R0 BS2 LSB bit0 0 M3 S0 OS BS1 A A A A A CXA3250AN 3-3) Read mode In read mode, the phase comparator locked/unlocked status and 5-level A/D converter input pin voltage status are transmitted and output to the master. The read data format is as shown in the table below. Read mode : Slave Transmitter MODE Address byte Status byte A MA0, MA1 FL A0 to A1 : : : : bit7 1 X bit6 1 FL bit5 0 1 bit4 0 1 bit3 0 1 Acknowledge bit address setting lock detection signal (1: locked, 0: unlocked) A/D converter (See the table below.) 5-level A/D Converter Output Table Voltage applied to LOCK/ADC pin 0.6 VCC2 to VCC2 0.45 VCC2 to 0.6 VCC2 0.3 VCC2 to 0.45 VCC2 0.15 VCC2 to 0.3 VCC2 0 to 0.15 VCC2 A1 1 0 0 0 0 A1 0 1 1 0 0 —22— A0 0 1 0 1 0 bit2 MA1 A2 bit1 MA0 A1 bit0 0 A0 A A CXA3250AN 4.) 3-Wire Bus Control The following transfer bit length formats are automatically identified during 3-wire bus control. 18 bits : Band data (4 bits) + frequency data (14 bits) 19 bits : Band data (4 bits) + frequency data (15 bits) 27 bits : Band data (4 bits) + frequency data (15 bits) + test data (8 bits) 4-1) 18-bit data transfer Data is loaded at the rising edge of the clock signal while the enable signal is high, and is latched at the falling edge of the enable signal. The clocks during the enable period are counted, and when 18 bits have been loaded, the programmable divider “M9” data is set to “0” and the reference divider frequency division ratio is automatically set to “1/80” when the BYP/MS pin voltage is VCC or to “1/64” when the BYP/MS pin is DC open. 18-bit data format Invalid data Band switch data Frequency data BS4 BS3 BS2 BS1 M8 M7 M6 M5 M4 M3 M2 M1 Invalid data M0 S4 S3 S2 S1 S0 DATA 1 4 5 18 CLOCK ENABLE Time Latch 4-2) 19-bit data transfer Data is loaded at the rising edge of the clock signal while the enable signal is high, and is latched at the falling edge of the enable signal. The clocks during the enable period are counted, and when 19 bits have been loaded, the reference divider frequency division ratio is automatically set to “1/80” when the BYP/MS pin voltage is VCC or to “1/128” when the BYP/MS pin is DC open. 19-bit data format Invalid data Band switch data Frequency data BS4 BS3 BS2 BS1 M9 M8 M7 M6 M5 M4 M3 M2 M1 Invalid data M0 S4 S3 S2 S1 S0 DATA 1 4 5 19 CLOCK ENABLE Time Latch —23— CXA3250AN 4-3) 27-bit data transfer The 3-wire bus also automatically supports the 27-bit format in which various control data are transferred in addition to the band and frequency data. Data is loaded at the rising edge of the clock signal while the enable signal is high, and is latched at the falling edge of the enable signal. The clocks during the enable period are counted, and 27 bits of data as counted from the rising edge of the enable signal are loaded as valid data. 27-bit data format Invalid data Band switch data Frequency data BS4 BS3 BS2 BS1 M9 M8 S3 S2 Test data S1 S0 X 19 20 CP CD X Invalid data R1 R0 X DATA 1 4 5 27 CLOCK ENABLE Time M0 to : S0 to : CD : OS : CP : BS1 to BS4 : R0, R1 : Latch main divider frequency division ratio setting swallow counter frequency division ratio setting charge pump OFF (when “1”) varicap output OFF (when “1”) charge pump current switching (200 µA when “1”, 50 µA when “0”) band switch control (output PNP transistor ON when “1”) Reference divider frequency division ratio setting. Reference Divider Frequency Division Ratio Table R1 0 1 X R0 1 1 0 Reference divider 128 64 80 X : Don’t care —24— CXA3250AN I2C Bus Timing Chart tWSTA SDA tR tSSTA tF tSSTO SCL tHSTA tLOW START tHIGH tSDAT CLOCK tHDAT DATACHANGE tSSTA=Start setup time tWSTA=Start waiting time tHSTA=Start hold time tLOW=LOW clock pulse width tHIGH=HIGH clock pulse width STOP tSDAT=Data setup time tHDAT=Data hold time tSSTO=Stop setup time tR =Rise time tF =Fall time 3-Wire Bus Timing Chart tSD DATA 3V 1.5V 3V 1.5V CLOCK ENABLE tHD 3V 1.5V tWE tSE tHE tSD=Data setup time tHD=Data hold time tSE=Enable setup time tHE=Enable hold time tWE=Enable waiting time —25— CXA3250AN Example of Representative Characteristics Circuit current vs. Supply voltage 1 Circuit current vs. Supply voltage 2 60 20 58 UHF VHF 54 DICC-Circuit current [mA] AICC-Circuit current [mA] 56 52 50 48 46 15 44 42 40 4.7 4.8 4.9 5 5.1 5.2 5.3 10 4.6 5.4 4.8 VCC1-Supply voltage [V] Band SW output voltage vs. Output current (BS1, BS2, BS3, BS4) 9.2 VCC3=9V 9.0 8.8 8.6 VCC3=5V 8.8 8.6 VCC3=5V 5.0 4.8 4.8 4.6 4.6 4.4 4.4 0 5 10 15 20 25 Output current [mA] I/O characteristics (Untuned input) 10 0 –10 –20 fRF=145MHz (VHF) fRF=495MHz (UHF) fIF is both f=45MHz –30 –40 –50 –60 –60 –50 –40 –30 –20 –10 0 1 2 3 4 Output current [mA] 20 IF output level [dBm] 5.4 Band SW output voltage vs. Output current VCC3=9V 5.0 5.2 9.2 Output voltage [V] Output voltage [V] 9.0 5 VCC2-Supply voltage [V] 0 10 20 RF level [dBm] —26— 5 6 CXA3250AN Noise figure vs. Reception frequency (Untuned input, in DSB) 20 fIF=45MHz Conversion gain vs. Reception frequency (Untuned input) 40 30 UHF VHF (Low) VHF (High) 20 15 NF-Noise figure [dB] CG-Conversion gain [dB] fIF=45MHz 10 VHF (Low) VHF (High) UHF 10 5 0 0 0 100 200 300 400 500 600 700 800 0 900 100 200 Reception frequency [MHz] 500 600 700 800 900 Oscillation frequency power supply fluctuation (PLL off) 400 120 VCC–5% VCC+5% (VCC=5V) 300 100 200 VHF (Low) VHF (High) 80 +B drift [kHz] CM-Cross modulation [dBµ] 400 Reception frequency [MHz] Next adjacent cross modulation vs. Reception frequency (Untuned input) 60 fIF=45MHz fUD=fD+12MHz fUD=fD–12MHz (100kHz, 30%AM) 40 100 UHF 0 –100 –200 20 –300 –400 0 0 100 200 300 400 500 600 700 800 900 PCS beat characteristics +20 +10 0 fIF –10 –20 –30 fBeat –40 VHF (Low) fLocal=95MHz fP=49.25MHz fC=52.83MHz (fP–12dB) fS=53.75MHz (fP–1.7dB) –50 –60 –70 –80 –40 fIF=45.75MHz fBeat=fIF±920kHz –30 –20 –10 0 +10 0 100 200 300 400 500 600 Oscillation frequency [MHz] Reception frequency [MHz] IF output level [dBm] 300 +20 SG output level [dBm] (fP level) —27— 700 800 900 CXA3250AN Tuning Response Time 1 VHF (Low) 95MHz → VHF (High) 395MHz (CP=1) T=27.2msec 5.0V/div offset 10.0V –40,0000ms 10,0000ms 10.0ms/div 60,0000ms real time VHF (Low) 95MHz → VHF (High) 395MHz (CP=0) T=75.6msec 5.0V/div offset 10.0V –130,000ms 20,0000ms 30.0ms/div —28— 170,000ms real time CXA3250AN Tuning Response Time 2 UHF 413MHz → UHF 847MHz (CP=1) T=34.2msec 5.0V/div offset 10.0V –40,0000ms 10,0000ms 10.0ms/div 60,0000ms real time UHF 413MHz → UHF 847MHz (CP=0) T=86.0msec 5.0V/div offset 10.0V 10.0V –70,0000ms 30,0000ms 20.0ms/div 130,000ms real time —29— CXA3250AN Tuning Response Time 3 VHF (High) 395MHz → VHF (Low) 95MHz (CP=1) T=12.6msec 5.0V/div offset 10.0V –40,0000ms 10,0000ms 10.0ms/div 60,0000ms real time VHF (High) 395MHz → VHF (Low) 95MHz (CP=0) T=39.2msec 5.0V/div offset 10.0V –100,000ms 0,00000s 20.0ms/div —30— 100,000ms real time CXA3250AN Tuning Response Time 4 UHF 847MHz → UHF 413MHz (CP=1) T=15.0msec 5.0V/div offset 10.0V –40,0000ms 10,0000ms 20.0ms/div 600,000ms real time UHF 847MHz → UHF 413MHz (CP=0) T=50.0msec 5.0V/div offset 10.0V –100,000ms 0,00000s 20.0ms/div —31— 100,000ms real time CXA3250AN IF output spectrum 10dB/div VHF (Low) fRF=55MHz fL.0=100MHz RF input level : –40dBm CENTER 45.0MHz #RES BW 1.0kHz SPAN 100.0kHz SWP 30.0 sec #VBW 10Hz IF output spectrum 10dB/div VHF (High) fRF=350MHz fL.0=395MHz RF input level : –40dBm CENTER 45.0MHz #RES BW 1.0kHz #VBW 10Hz —32— SPAN 100.0kHz SWP 30.0 sec CXA3250AN IF output spectrum 10dB/div UHF fRF=800MHz fL.0=845MHz RF input level : –40dBm CENTER 45.0 270MHz #RES BW 1.0kHz #VBW 10Hz —33— SPAN 100.0kHz SWP 30.0 sec CXA3250AN VHF Input Impedance j50 j25 50MHz VHFin 50 BYP/MS 0 j100 12 13 1000p S11 350MHz –j100 –j25 –j50 UHF Input Impedance j50 j25 UHFin2 50 UHFin1 0 j100 14 15 1000p S11 350MHz 800MHz –j25 –j50 —34— –j100 CXA3250AN IF Output Impedance j50 j25 0 j100 45MHz 50 38MHz –j100 –j25 –j50 —35— CXA3250AN Package Outline Unit : mm 30PIN SSOP (PLASTIC) + 0.2 1.25 – 0.1 ∗9.7 ± 0.1 1 + 0.1 0.22 – 0.05 7.6 ± 0.2 16 ∗5.6 ± 0.1 30 0.10 A 15 + 0.05 0.15 – 0.02 0.65 0.13 M 0.5 ± 0.2 0.1 ± 0.1 0° to 10° NOTE: Dimension “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER/PALLADIUM PLATING SONY CODE SSOP-30P-L01 LEAD TREATMENT EIAJ CODE SSOP030-P-0056 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.1g JEDEC CODE NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). —36—