CXB1567Q Limiting Amplifier for Optical Fiber Communication Receiver For the availability of this product, please contact the sales office. Description The CXB1567Q achieves the 2R optical-fiber communication receiver functions (Reshaping and Regenerating) on a single chip. This IC is also equipped with the signal interruption alarm output function, which is used to discriminate the existence of data input. 48 pin QFP (Plastic) Features • Auto-offset canceller circuit • Signal interruption alarm outputs • Single 5V power supply Applications • SONET/SDH: 622.08Mb/s • Fiber channel: 531.25Mb/s Absolute Maximum Ratings • Power supply VCC – VEE • Storage temperature Tstg • Input voltage difference: | VD – VD | Vdif • Input voltage Vi • Output current (Continuous) IO (Surge current) Recommended Operating Conditions • Supply voltage VCC – VEE • Operating temperature Ta • Termination resistor (Q/Q) RT1 • Termination resistor (SD/SD) RT2 • Termination voltage VCC – VTT –0.3 to +7.0 –65 to +150 V °C 0.0 to +2.5 –0.3 to VCC V V 0 to 50 0 to 100 mA mA 5.0 ± 0.5 –40 to +85 V °C 45 to 55 Ω 45 to 55 1.8 to 2.2 Ω V Structure Bipolar silicon monolithic IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E94709A63-ST CXB1567Q N.C. N.C. SD SD VEED VEED N.C. Q Q VCCDA N.C. VEE Block Diagram and Pin Configuration 36 35 34 33 32 31 30 29 28 27 26 25 24 N.C. N.C. 38 23 N.C. Output Buffer Block VEE 37 VEED 39 22 VEED VCCD 40 VCCD 42 20 VEED 19 VEED Limiting Amplifier Block Alarm Block VEED 41 Peak Hold1 Peak Hold2 21 VEED UP 43 DOWN 44 VCCA 45 R3 R1 R1 N.C. 47 17 VEED 16 CAP1 15 CAP1 R3 VEEA 46 18 VEED 14 N.C. R2 13 VEE N.C. 48 1 2 3 4 5 6 7 8 9 10 11 12 VEE N.C. VCCA VEEA CAP3 CAP2 VEEA D N.C. D VEEA N.C. R2 –2– CXB1567Q Pin Description Pin No. Typical pin Symbol voltage (V) DC AC Description Equivalent circuit –5V 1 VEE 2 N.C. 3 VCCA 0V Positive power supply pin for analog block. 4 VEEA –5V Negative power supply pin for analog block. Negative power supply pin. No connection. 6 5 VCCA CAP3 –1.8V 80 80 10p 10p 5 40µA 6 CAP2 –1.8V 7 VEEA –5V 8 D –1.3V 9 N.C. 10 D 11 VEEA 12 N.C. 13 VEE 14 N.C. 15 CAP1 –1.8V 16 CAP1 –1.8V 40µA VEEA Capacitance connection pins for alarm block peak hold circuit. Connect each pin to VCC in 2000pF. CAP2 pin → Peak hold capacitance connection pin for the limiting amplifier signal CAP3 pin → Peak hold capacitance connection pin for the alarm level setting block Negative power supply pin for analog block. –0.9V to –1.7V Limiting amplifier input pins Ensure that these inputs are AC-coupled. VCCA 100 –1.3V 8 10 17 to 22 VEED 23, 24 N.C. 25 VEE –5V 100 1K 7.5k 130p 200 7.5k 200 16 Negative power supply pin for analog block. 15 No connection. Negative power supply pin. –5V 1K VEEA No connection. Capacitance connection pins to determine the cut-off frequency for feedback block. Negative power supply pin for digital block. –5V No connection. –5V Negative power supply pin. –3– CXB1567Q Pin No. Typical pin Symbol voltage (V) DC 26 N.C. 27 VCCDA 28 Q Equivalent circuit Description AC No connection. Positive power supply pin for output buffer. 0V –0.9V to –1.7V VCCDA 28 29 Q 30 N.C. 31, 32 VEED 33 29 –0.9V to –1.7V VEED No connection. Negative power supply pin for digital block. –5V VCCDA –0.9V to –1.7V SD 33 34 Data signal output pins. Terminate these pins in 50Ω at VTT = –2V. 34 –0.9V to –1.7V SD Alarm signal output pins. Terminate these pins in 50Ω at VTT = –2V. VEED No connection. 35, 36 N.C. 37 VEE 38 N.C. 39 VEED –5V Negative power supply pin for digital block. 40 VCCD 0V Positive power supply pin for digital block. 41 VEED –5V Negative power supply pin for digital block. 42 VCCD 0V Positive power supply pin for digital block. Negative power supply pin. –5V No connection. –4– CXB1567Q Pin No. Typical pin Symbol voltage (V) DC AC Equivalent circuit Description VCCA 43 UP 1k –4.7V 100 100 5k 43 5k 44 44 DOWN –5V VEEA Resistor connection pins for alarm level setting. UP pin → When the resistance connected to this pin is increased, the alarm level becomes higher. DOWN pin → Normally connect this pin to VEE. 45 VCCA 0V Positive power supply pin for analog block. 46 VEEA –5V Negative power supply pin for analog block. 47, 48 N.C. No connection. –5– CXB1567Q Electrical Characteristics • DC characteristics (VCC = VCCA = 0V, VEED= VEEA= VEE = –5V±10%, Ta = –40°C to +85°C, RT = 50Ω, VTT = –2V) Item Symbol Conditions Min. Typ. Max. Supply current IEE –93 –59 Q/Q High output voltage VOH –1.03 –0.95 –0.88 Q/Q Low output voltage VOL –1.81 –1.70 –1.62 –1.25 –0.95 –0.70 –1.95 –1.76 –1.57 SD/SD High output voltage VOHS SD/SD Low output voltage VOLS Input offset voltage VOFF D/D input resistance Rin Ta = 0 to 85°C mA 70 1.0 0.75 Unit V µV 1.25 kΩ • AC characteristics (VCC = VCCA = 0V, VEED= VEEA= VEE = –5V±10%, Ta = –40°C to +85°C, RT = 50Ω, VTT = –2V) Item Symbol Conditions Maximum input data rate B Maximum input voltage VMAX Limiting amplifier gain GL Q/Q rise time TTLH Q/Q fall time TTHL Identification maximum voltage amplitude of alarm level VMIN Hysteresis width Hys Alarm response assert time TAS Electrically tested Low → High ∗1 (SD) Alarm response deassert time TDAS High → Low ∗2 (SD) Min. Typ. Max. Unit 622.08 Mbps Single-ended input voltage at D 1000 mVpp IC internal amplitude 400mVpp 66 dB 20% to 80% 240 450 240 450 20 4 –6– mVpp 6 8 0 100 2.5 100 ∗1 CAP2, CAP3 pin capacitance = 2000pF, REX = 400Ω, Vin = 20mVpp (single ended) ∗2 CAP2, CAP3 pin capacitance = 2000pF, REX = 400Ω, Vin = 60mVpp (single ended) ps dB µs CXB1567Q DC Electrical Characteristics Measurement Circuit VTT V 36 35 VTT –2V 51 34 51 V 32 33 V 31 –2V 51 30 29 51 28 V 27 26 25 24 38 23 Output Buffer Block 37 39 22 40 20 Alarm Block 41 P/H 1 P/H 2 21 19 Limiting Amplifier Block 42 43 REX 44 45 46 17 16 C2 15 47 14 48 13 1 2 3 5 4 C3 A 18 6 8 7 C3 9 10 11 12 C1 VEE V –5V VD –7– C1 CXB1567Q AC Electrical Characteristics Measurement Circuit Z0 = 50 Z0 = 50 Oscilloscope 50Ω Input Z0 = 50 Z0 = 50 36 35 33 34 32 31 30 29 28 27 26 25 24 38 23 Output Buffer Block 37 39 22 40 20 Alarm Block 41 P/H 1 P/H 2 21 19 Limiting Amplifier Block 42 43 REX 44 45 46 16 0.047µF 15 14 48 13 2 3 4 2000pF 5 6 8 7 2000pF 9 1000pF 10 11 1000pF VCC –3V 17 47 1 VEE 18 RD +2V VD –8– RD 12 CXB1567Q Application Circuit VTT 51 36 35 51 33 34 –2.0V 51 32 31 30 51 28 29 27 26 25 24 38 23 Output Buffer Block 37 39 22 40 20 Alarm Block 41 P/H 1 P/H 2 21 19 Limiting Amplifier Block 42 43 273 44 45 46 18 17 16 0.047µF 15 47 14 48 13 1 2 3 4 2000pF 5 6 7 2000pF 9 8 10 11 1000pF 1000pF 50 50 12 VEE –5.0V VD Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. –9– CXB1567Q Notes on Operation 1. Limiting amplifier block The limiting amplifier block is equipped with the auto-offset canceller circuit. When external capacitors C1 and C2 are connected as shown in Fig. 1, the DC bias is set automatically in this block. External capacitor C1 and IC internal resistor R1 determine the low input cut-off frequency f2, as shown in Fig. 2. Similarly, external capacitor C2 and internal resistor R2 determine the high cut-off frequency f1 for DC bias feedback. Since peaking characteristics may occur in the low frequency area of the amplifier gain characteristics depending on the f1/f2 combination, set the C1 and C2 values so as to avoid the occurrence of peaking characteristics. The typical values of R1,R2, C1 and C2 are as indicated below. When a single-ended input is used, provide AC grounding by connecting Pin 10 to a capacitor which has the same capacitance as capacitor C1. RD is the resistor for impedance matching. The same level of output impedance as for the signal source should be applied to Pin 10. R1 (internal) : 1kΩ R2 (internal) : 7.5kΩ f2: 160kHz f1: 450Hz C1 (external) : 1000pF C2 (external) : 0.047µF 8 D C1 To IC interior RD 10 C1 R1 R1 15 R2 C2 R2 16 Fig. 1 Gain Feedback frequency responce f1 f2 Frequency Fig. 2 – 10 – Amplifier frequency responce CXB1567Q 2. Alarm block As shown in Fig. 3, the alarm block requires external resistor REX1 for alarm level setting and peak hold capacitor C3. When the resistance value provided for resistor REX1 is increased, the alarm setting level rises. When the resistance value provided for REX2 is increased, the alarm setting level lowers. However, the voltage of Pin 43 should always be higher than that of Pin 44. Normally, short-circuit Pin 44 to VEE (REX2 = 0). See Fig. 5 for the alarm setting level. In the relationship between the alarm setting level and hysteresis width, the hysteresis width is designed to maintain a constant gain (design target value: 6dB) as shown in Fig. 4. External capacitors C3 are used for input signal and alarm level peak hold capacitance. The C3 capacitance value should be set so as to obtain desired assert time and deassert time settings for the alarm signal. The deassert time becomes smaller by connecting resistor R10 between VEE and Pin 5 and resistor R11 between VEE and Pin 6. The REX1 and C3 typical values are indicated below. (A capacitance of approximately 10pF is built in Pins 5 and 6 respectively.) REX1: C3: 273Ω (VDAS = 3mVpp) 2000pF VCCA R7 R8 From Limiting amplifier 1k Peak hold SD SD 100 100 R8 R7, R8, and R9 values are typical values. Peak hold 10p R9 5k R9 10p 5k VccA IC interior 43 VccA 6 44 5 IC exterior REX1 VEE C3 R10 REX2 VEE VEE Vcc C3 Vcc R11 VEE SD output Fig. 3 VDAS → deassert level VAS → assert level 20 VAS, VDAS (mVpp) High level 24 Low level VDAS 0 VAS 16 12 VDAS 8 VAS Hysteresis width Input amplitude 4 0 20 log ( VAS ) = 6.0 dB VDAS 0 200 400 600 REX1 (Ω) Fig. 4 Fig. 5 – 11 – 800 1000 1200 CXB1567Q Example of Representative Characteristics Bit error rate vs. Data input level for each data rate 10–6 VEE = –5.0V, Ta = 27°C, pattern : PRBS223–1 10–7 Bit error rate 10–8 1062.5Mbps 10–9 622.08Mbps 265.5Mbps 10–10 10–11 2 3 4 5 Data input level [mVp-p] Output RMS jitter vs. Data input level 50 VEE = –5.0V Ta = 27°C D = 622.08Mbps pattern : PRBS223–1 Output RMS jitter [ps] 40 30 20 10 0 1 10 100 Data input level [mVp-p] – 12 – 1000 CXB1567Q VEE = –5.0V Ta = 27°C D = 265.5Mbps pattern = PRBS223–1 Y Axis = 300mV/div X Axis = 1300ps/div Q VDIN = 2.0Vp-p Q 26.1040ns 32.6040ns 39.1040ns Q VDIN = 500mVpp Q 26.1040ns 32.6040ns 39.1040ns Q VDIN = 2.5mVpp Q 26.1040ns 32.6040ns – 13 – 39.1040ns CXB1567Q VEE = –5.0V Ta = 27°C D = 622.08Mbps pattern = PRBS223–1 Y Axis = 300mV/div X Axis = 500ps/div Q VDIN = 2.0Vp-p Q 23.7300ns 26.2300ns 28.7300ns Q VDIN = 500mVpp Q 23.6600ns 26.1600ns 28.6600ns Q VDIN = 3.0mVpp Q 23.7500ns 26.2500ns – 14 – 28.7500ns CXB1567Q VEE = –5.0V Ta = 27°C D = 1062.5Mbps pattern = PRBS223–1 Y Axis = 300mV/div X Axis = 300ps/div Q VDIN = 2.0Vp-p Q 26.4900ns 27.9900ns 29.4900ns Q VDIN = 500mVpp Q 26.4900ns 27.9900ns 29.4900ns Q VDIN = 10mVpp Q 16.3740ns 17.8740ns – 15 – 19.3740ns CXB1567Q Package Outline Unit: mm 48PIN QFP (PLASTIC) 15.3 ± 0.4 + 0.1 0.15 – 0.05 + 0.4 12.0 – 0.1 36 25 0.15 24 48 13 13.5 37 12 0.8 + 0.15 0.3 – 0.1 ± 0.12 M 0.9 ± 0.2 1 + 0.2 0.1 – 0.1 + 0.35 2.2 – 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE QFP-48P-L04 LEAD TREATMENT SOLDER / PALLADIUM PLATING EIAJ CODE ∗QFP048-P-1212-B LEAD MATERIAL COPPER / 42 ALLOY PACKAGE WEIGHT 0.7g JEDEC CODE – 16 –