CXB1565R 622Mbps Clock & Data Recovery with High Sensitivity Limitting Amplifier For the availability of this product, please contact the sales office. Description The CXB1565R achieves 3R optical-fiber communication receiver functions (Reshaping and Regenerating and Retiming) on a single chip. This IC also equipped with the signal interruption alarm output, which is used to discriminate the existence of data input. 64 pin LQFP (Plastic) Features • Auto-offset canceler circuit • Signal interruption alarm output • No reference clock required • Single 5V power supply Applications • SONET/SDH: 622.08Mbps • ATM: 622.08Mbps Absolute Maximum Ratings • Supply voltage • Storage temperature • Input voltage difference: | VD – VDN | • TTL input voltage • Output current (Continuous) (Surge) Recommended Operating Conditions • Supply voltage • Termination voltage (for RCK/RDATA) • Termination voltage (for SDE) • Termination resistance (for RCK/RDATA) • Termination resistance (for SDE) • Operating temperature VCC – VEE Tstg Vdif VinT IO –0.3 to +7.0 –65 to +150 0 to 2.5 –0.5 to 5.5 0 to 50 0 to 100 V °C V V mA mA VCC – VEE VCC – VT1 VT2 RT1 RT2 Ta 4.5 to 5.5 1.8 to 2.2 VEE 46 to 56 460 to 560 –40 to +85 V V V Ω Ω °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E97323-PS CXB1565R NC VEEP1 VEEP1 NC NC NC NC VEEP2 LPFB LPFA VCCP VCCP NC CAP1B CAP1 VEER1 Block Diagram and Pin Configuration 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 NC NC 49 31 VEER2 REXT 50 LKDT 51 Up VEEG 52 charge pump VCO Down 30 VEER2 phase/ frequency detector 29 DN 28 D VEEG 53 1 0 VCCG 54 Mux. 27 VCCR1 D-FF EXCK 55 26 VCCR2 D CK Reset NC 56 25 DOWN CKSEL 57 24 HYS SQLCH 58 23 VEER3 SDC 59 peak hold SDE 60 22 CAP2 peak hold 21 CAP3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VEEG VCCG VCCG VEEE2 RCKN RCK VCCE2 VCCE2 NC 17 VEEG NC 64 VEEE1 18 NC RDATAN NC 63 RDATA 19 NC VCCE1 NC 62 VCCE1 20 NC NC SDEN 61 –2– NC CXB1565R Pin Description Typical pin voltage (V) Pin No. Symbol DC AC 1, 16 to 20 2, 3 Equivalent circuit Description No connect NC VCCE1 Positive supply for RDATA/RDATAN output circuits. 5 VCCE1 4 3.3 to 4.1 RDATA 4 5 5 3.3 to 4.1 RDATAN Retimed data outputs. VEEE1 6 VEEE1 0 Ground for RDATA/RDATAN output circuits. 7, 8 52, 53 VEEG 0 Ground for digital circuits. 9, 10 54 VCCG 5 Positive supply for digital circuits. 11 VEEE2 0 Ground for RCK/RCKN outputs circuits. 12 VCCE2 3.3 to 4.1 RCKN 12 13 14, 15 VCCE2 13 3.3 to 4.1 RCK VEEE2 Positive supply for RCK/RCKN output circuits. 5 21 22 10p 21 CAP3 Recovered clock outputs. VCCR2 3.2 Connect a peak hold capacitor for signal detector. Typically 470pF. 22 CAP2 3.2 5µA 5µA VEER3 –3– CXB1565R Typical pin voltage (V) Pin No. Symbol DC AC 23 VEER3 Equivalent circuit Description 0 Ground for signal detector. VCCR2 Connect to VEER3 through a external resistor determine signal detect hysteresis width (∆P). When connect to VEER3 directly. ∆P ≈ 6dB (Typ.) When 8.2kΩ is inserted. ∆P ≈ 3dB (Typ.) Bias Generator 24 HYS 0.3 24 VEER3 VCCR2 25 DOWN 4.4 Connect to VCCR2 through a external resistor to decrease signal detect level (SDL). When open, SDL sets to 20mVp-p. (single-ended) 25 VEER3 26 VCCR2 5 Positive supply for signal detector. 27 VCCR1 0 Positive supply for post amplifier. 28 D VCCR1 Serial data stream inputs. 29 DN 34 28 29 3.7 34 CAP1 35 CAP1B 3.7 30, 31 VEER2 32, 36 NC 35 VEER2 VEER1 0 Connect a external capacitor, which determines low cut-off frequency for feedback block. Typically 0.022µF. Ground for post amplifier. No connect 33 VEER1 0 Ground for post amplifier. Both VEER1 and VEER2 must be grounded. 37, 38 VCCP 5 Positive supply for PLL circuits. –4– CXB1565R Typical pin voltage (V) Pin No. Symbol DC AC Equivalent circuit Description VCCP 39 LPFA 39 40 40 Connect a external loop filter capacitor. Typically 0.33µF. LPFB VEEP1 VEEP2 41 VEEP2 Ground for PLL circuits. 0 42 to 45 48, 49 NC 56 46, 47 VEEP1 No connect Ground for PLL circuits. Both VEEP1 and VEEP2 must be grounded. 0 VCCP 50 REXT Bias Generator 0.6 50 Connect to VEEP1 through a external resistor to determine VCO frequency. Typically 2.4kΩ. VEEP2 VCCG 51 LKDT 0.2 to 4.8 51 VEEG –5– Lock detector (TTL). Driven low, while synchronization is lost. If SQLCH is asserted(low),fixed high even when lock is lost. CXB1565R Typical pin voltage (V) Pin No. Symbol DC AC Equivalent circuit Description VCCG 55 EXCK External clock input (ECL). For testing only. Normally, left open. 55 3 VEEG VCCG 57 CKSEL 5 Clock selector (TTL). When low, EXCK is active instead of VCO output. Normally, left open. 57 VEEG VCCG 58 SQLCH 5 TTL input. When Low, RCK and RDATA fix Low, in case of data loss. When high, RCK outputs VCO free-run frequency, in case of data loss. 58 VEEG VCCG 59 SDC 0.2 to 4.8 Signal detect output (TTL). Driven low, while input serial data is lost. 59 VEEG VCCG 60 SDE 60 Signal detect outputs (ECL). SDE is driven low, while input serial data is lost. 61 61 SDEN VEEG No connect 62 to 64 NC –6– CXB1565R Electrical Characteristics • DC characteristics Item (VCC = +5V ± 10%, VEE = GND, Ta = –40°C to +85°C) Symbol Conditions Min. Typ. Max. Unit 95 130 mA Supply current ICC TTL input High voltage VIHT 2 5.5 V TTL input Low voltage VILT 0 0.8 V 51Ω to VCC – 2V VCC – 1.1 VCC – 0.83 V 51Ω to VCC – 2V VCC – 1.86 VCC – 1.55 V RDATA/RCK output High voltage RDATA/RCK output Low voltage VOH1∗1 VOL1∗1 All outputs open 510Ω to VEE VCC – 1.1 VCC – 0.83 V SDE output Low voltage VOH2∗1 VOL2∗1 510Ω to VEE VCC – 1.86 VCC – 1.55 V TTL output High voltage VOHT IOH = –0.4mA 2.6 TTL output Low voltage VOLT IOL = 2.1mA Maximum input voltage amplitude Vmax 1600 D/DB input resistance Rin 1125 SDE output High voltage V 0.5 V mV 1500 1875 Ω ∗1 Ta = 0°C to +85°C • AC characteristics Item (VCC = +5V ± 10%, VEE = GND, Ta = –40°C to +85°C) Symbol Conditions Min. Typ. Max. Unit Post amplifier gain GL Except for output buffer 40 dB Signal detect hysteresis width ∆P HYS = VEER3, Rd ≥ 2kΩ 3 7.5 dB Signal detect response assert time Tas 0 100 µs Signal detect response deassert time Tdas CAP2, CAP3 = 470ps DOWN = OPEN D = 200mVp-p, Single ended 2.3 100 µs RCK/RCKN output jitter RJ ∗1 PLL band width fc∗2 ∗1 500 kHz Jitter peaking ∗1 0.1 dB Jitter Tolerance f = 10Hz, ∗1 ∗3 30Hz, ∗1 ∗3 300Hz, ∗1 ∗3 25kHz, ∗1 ∗3 250kHz, ∗1 ∗3 degrees rms 3.6 PLL capture range 15 15 1.5 1.5 0.15 UI 622.01 622.08 622.15 Mbps PLL pull in time Tp ∗1 10 RCK/RCKN output rise/fall time TRC/TFC 51Ω to VCC – 2V, 20% to 80% 250 350 ps RDATA/RDATAN output rise/fall time TRD/TFC 51Ω to VCC – 2V, 20% to 80% 350 500 ps ms ∗1 D = 50mVp-p (single-ended), 223 – 1 PRBS, under the AC Electrical characteristics measurement circuit. ∗2 fc: frequency which attenuates the input sinusoidal jitter by 3dB. ∗3 Bit error rate threshould: 1E – 10 –7– CXB1565R 0.022µF DC Electrical Characteristics Measurement Circuit 0.33µF 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 32 50 31 2.4kΩ 51 52 Up charge pump Down VCO 30 phase/ frequency detector 29 28 53 1 0 54 Mux. 27 D-FF 55 26 D CK Reset 56 25 57 24 58 23 59 22 470pF peak hold 21 61 20 62 19 63 18 64 17 5 4 3 6 7 8 9 10 11 13 12 2V 2V 14 15 470pF 16 51Ω 2 51Ω 1 51Ω 510Ω 51Ω 510Ω peak hold 60 Vcc 5V VEE –8– CXB1565R AC Electrical Characteristics Measurement Circuit 0.1µF 33µF 5V 0.022µF 0.33µF 48 47 46 45 43 44 42 40 41 39 38 37 36 35 34 33 49 32 50 31 2.4kΩ 51 30 Up 52 charge pump VCO Down phase/ frequency detector 470pF 50Ω 29 28 1 0 54 Mux. 27 D-FF 55 26 D CK Reset 56 470pF 25 57 24 58 23 22 59 peak hold 510Ω 60 peak hold 470pF 21 470pF 61 20 62 19 63 18 64 17 4 5 6 7 9 8 10 11 12 13 Z = 50Ω 3 Z = 50Ω 2 Z = 50Ω 1 Z = 50Ω 510Ω 14 15 16 Oscilloscope 50Ω 50Ω 50Ω 1MΩ 1MΩ 1MΩ 1MΩ Z = 50Ω 0.1µF Oscilloscope Clock Data Bit Error Rate Counter –9– Clock Jitter Source Data Pulse Pattern Generator 50Ω 0.1µF 53 0.1µF CXB1565R Application Circuit 0.33µF 48 47 46 45 43 44 42 40 41 39 0.1µF 38 Analog 0.022µF Supply 2 37 36 35 34 33 49 32 50 31 2.4kΩ 51 Up 52 charge pump Down VCO 30 phase/ frequency detector 130Ω 130Ω 470pF 29 470pF 28 53 1 0 54 Mux. 27 D-FF 55 91Ω 26 D CK Reset 56 91Ω Analog 25 Supply1 57 24 58 23 59 22 0.1µF 470pF peak hold 60 peak hold 470pF 21 61 20 62 19 63 18 64 17 1 2 5 4 3 6 7 8 9 10 11 13 14 15 16 Digital Supply 0.1µF 40µH 5V 12 33µF Digital Supply Analog Supply 1 Analog Supply 2 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 10 – CXB1565R Notes on Operation 1. Limiting amplifier block The limiting amplifier block is equipped with the auto-offset canceler circuit. When external capacitors C1 and C2 are connected as shown in Fig. 1, the DC bias is set automatically in this block. External capacitor C1 and IC internal resistor R1 determine the low input cut-off frequency f2 as shown in Fig. 2. Similarly, external capacitor C2 and IC internal resistor R2 determine the high cut-off frequency f1 for DC bias feedback. Since peaking characteristics may occur in the low frequency area of the amplifier gain characteristics depending on the f1/f2 combination, set the C1 and C2 so as to avoid the occurrence of peaking characteristics. The target values of R1 and R2 and the typical values of C1 and C2 are as indicated below. When a single-ended input is used, provide AC grounding by connecting Pin 29 to a capacitor which has the same capacitance as capacitor C1. R1 (internal): 1.5kΩ R2 (internal): 10kΩ f2: 225kHz f1: 723Hz C1 (external): 470pF D C2 (external): 0.022µF 28 C1 To IC interior 29 C1 R1 R1 R2 34 C2 35 R2 Fig. 1 Gain Feedback frequency response f1 f2 Frequency Fig. 2 – 11 – Amplifier frequency response CXB1565R 2. Alarm block This block provides a signal interruption alarm output used for open fibre control (OFC). Signal detect threshold level and hysteresis width are both user adjustable. Signal detect threshold default level is 20mVp-p (single-ended). An external resister Rd between DOWN and VCCR decrease it. Typical characteristics of Rd vs. threshold level is shown in fig. 7, 8. Hysteresis width can be also decreased by an external resister RH. Typical characteristics of RH vs. ∆P is shown in fig. 9. Timing chart of signal detect function is shown in fig. 5. SD response assert/deassert time are decided by peak hold capacitor CR and CS.Their typical value is 470pF each. VDAS → Deassert level VAS → Assert level SD output High level Rd 26 Rh 25 Cs 24 23 Cs : 470pF CR : 470pF CR 22 Low level VAS VDAS Small 21 Large 3dB 3dB Alarm setting input level Hysteresis Input electrical signal amplitude Fig. 4 Fig. 3 Hysteresis width Data input (D) Alarm setting level Alarm output (SDEN) Alarm output (SDE, SDC) Assert time Deassert time Fig. 5. Timing Chart – 12 – CXB1565R 3. Clock and Data recovery block Clock recovery is reallized by fully integrated phase locked loop (PLL), which needs no external reference clock. PLL accepts scrambled NRZ data with 50% mark density. Two external components Re and Cp are required. Their recommended values are shown in fig. 6. Cp 47 46 41 40 39 50 Re Re : 2.4kΩ Cp : 0.33µF Fig. 6 Re is a resistor which decides VCO center frequency. To reduce the temperature dependence of the VCO oscillation frequency, Re should have a small temperature coefficient. In addition, Re should place as near as IC terminal to obtain good jitter performance. Cp is a loop filter capacitance. Since loop damping factor ξ is function of √Cp, Cp is also important to have a small temperature coefficient. Damping factor ξ is given as 20,000 × √Cp (@ρ = 1/2) ∗3 Recommended Cp value gives a ξ of 10, and jitter peaking of under 0.1dB is specified. ∗3 ρ: data transition density 4. Others Pay attention to handling this IC because its electrostatic discharge strength is week. – 13 – CXB1565R Assert/Deassert level [mVp-p, single-ended] 30 25 20 15 10 Vassert Vdeassert 5 0 0 5 10 Rd [kΩ] 15 20 30 25 20 15 10 Vassert Vdeassert 5 0 0 5 10 Rd [kΩ] 15 VCC = 5V, Ta = 27°C 622.08Mbps, 223 – 1PRBS Rh = 8.2kΩ VCC = 5V, Ta = 27°C 622.08Mbps, 223 – 1PRBS Rh = 0Ω Fig. 8. Rd vs. Assert/Deassert level (RH = 8.2kΩ) Fig. 7. Rd vs. Assert/Deassert level 30 Vssert/Deassert level [mVp-p, single-ended] Assert/Deassert level [mVp-p, single-ended] Example of Representative Characteristics 25 20 15 10 Vassert Vdeassert 5 0 0 5000 10000 15000 Rh [Ω] VCC = 5V, Ta = 27°C 622.08Mbps, 223 – 1PRBS Rd = ∞ Fig. 9. Rh vs. Assert/Deassert level – 14 – 20000 20 400mV/div CXB1565R 500ps/div VCC = 5V, Ta = 27°C 622.08Mbps, 223 – 1PRBS 50mVp-p single-ended 100mV/div Fig. 10. RCK/RDATA output waveform 14.6ps (RMS) 50ps/div VCC = 5V, Ta = 27°C 622.08Mbps, 223 – 1PRBS 50mVp-p single-ended Fig. 11. RCK output histgram 0 100 OC-12 mask Amplitude [UI] Amplitude [dB] –5 –10 –15 10 1 OC-12 template –20 –25 0.1 101 102 103 105 104 Modulation Frequency [Hz] 106 107 101 102 105 106 104 103 Modulation Frequency [Hz] VCC = 5V, Ta = 27°C 622.08Mbps, 223 – 1PRBS 50mVp-p, single-ended Threshold = 1E – 10 VCC = 5V, Ta = 27°C 622.08Mbps, 223 – 1PRBS 50mVp-p, single-ended Fig. 12. Jitter transfer function Fig. 13. Jitter tolerance – 15 – 107 CXB1565R Package Outline Unit: mm 64PIN LQFP (PLASTIC) 12.0 ± 0.2 ∗ 10.0 ± 0.1 48 33 32 64 17 (0.22) 0.5 ± 0.2 (11.0) 49 A 1 0.5 ± 0.08 + 0.08 0.18 – 0.03 16 + 0.2 1.5 – 0.1 + 0.05 0.127 – 0.02 0.1 0° to 10° 0.5 ± 0.2 0.1 ± 0.1 NOTE: Dimension “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE LQFP-64P-L01 LEAD TREATMENT SOLDER/PALLADIUM PLATING EIAJ CODE LQFP064-P-1010 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.3g JEDEC CODE – 16 –