UT8ER1M32 - Aeroflex Microelectronic Solutions

Standard Products
UT8ER1M32 32Megabit SRAM MCM
UT8ER2M32 64Megabit SRAM MCM
UT8ER4M32 128Megabit SRAM MCM
Data Sheet
June 2015
The most important thing we build is trust
INTRODUCTION
The UT8ER1M32, UT8ER2M32, and UT8ER4M32 are high
performance CMOS static RAM multichip modules (MCMs)
organized as two, four or eight individual 524,288 words x 32
bits dice respectively. Easy memory expansion is provided by
active LOW chip enables (En), an active LOW output enable
(G), and three-state drivers. This device has a power-down
feature that reduces power consumption by more than 90% when
deselected. Autonomous (master) and demanded (slave)
scrubbing continues while deselected.
FEATURES
 20ns Read, 10ns Write maximum access times available
 Functionally compatible with traditional 1M, 2M and 4M
x 32 SRAM devices
 CMOS compatible input and output levels, three-state
bidirectional data bus
- I/O Voltages 2.3V to 3.6V, 1.7V to 2.0Vcore
 Available densities:
- UT8ER1M32: 33, 554, 432 bits
- UT8ER2M32: 67, 108, 864 bits
- UT8ER4M32: 134, 217, 728 bits
 Operational environment:
- Total-dose: 100 krad(Si)
Writing to the device is accomplished by driving one of the chip
enable (En) inputs LOW and the write enable (W) input LOW.
Data on the 32 I/O pins (DQ0 through DQ31) is then written into
the location specified on the address pins (A0 through A18).
Reading from the device is accomplished by driving one of the
chip enables (En) and output enable (G) LOW while driving
write enable (W) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins. Note: Only on En pin may be active at any time.
- SEL Immune: <110 MeV-cm2/mg
- SEU error rate = 8.1 x10-16 errors/bit-day assuming
geosynchronous orbit, Adam’s 90% worst environment,
and 6600ns default Scrub Rate Period (=97% SRAM
availability)
The 32 input/output pins (DQ0 through DQ31) are placed in a
high impedance state when the device is deselected (En HIGH),
the outputs are disabled (G HIGH), or during a write operation
(En LOW, W LOW).
 Packaging option:
- 132-lead side-brazed dual cavity ceramic quad flatpack
 Standard Microelectronics Drawing:
- UT8ER1M32: 5962-10202
- QML Q, Q+ and Vcompliant
- UT8ER2M32: 5962-10203
- QML Q, Q+, and Vcompliant
- UT8ER4M32: 5962-10204
- QML Q and Q+ compliant
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32M /64M/ 128M
2-, 4-, 8- Die
SRAM MCM Module
(0.90” Square, 132-Lead Side-Brazed Dual Cavity
Ceramic Quad Flatpack)
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
VSS
VSS
DQ16
DQ17
DQ18
DQ19
VDD2
VSS
DQ20
DQ21
DQ22
DQ23
VDD1
VSS
NC
VDD2
NC
VDD2
NC
VSS
VDD1
DQ24
DQ25
DQ26
DQ27
VSS
VDD2
DQ28
DQ29
DQ30
DQ31
VSS
VSS
VSS
A11
A12
A13
VSS
NC
NC
NC
VSS
BUSY# (NC)
VDD1
E7# (NC)
E5# (NC)
E3# (NC)
E1#
VDD1
G#
VSS
E2#
E4# (NC)
E6# (NC)
E8# (NC)
VDD1
SCRUB#
MBE
VDD2
NC
NC
VSS
A14
A15
A16
VSS
VSS
VSS
DQ0
DQ1
DQ2
DQ3
VDD2
VSS
DQ4
DQ5
DQ6
DQ7
VDD1
VSS
NC
VDD2
NC
VDD2
NC
VSS
VDD1
DQ8
DQ9
DQ10
DQ11
VSS
VDD2
DQ12
DQ13
DQ14
DQ15
VSS
VSS
132
131
130
129
128
127
126
125
124
1123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
VSS
VSS
A0
A1
A2
A3
VDD1
VSS
A4
A5
A17
NC
VDD1
NC
NC
VSS
NC
VDD1
NC
NC
VDD1
NC
A18
W#
A6
VSS
VDD1
A7
A8
A9
A10
VSS
VSS
June 2015
Notes:
1. NC = Pins are not connected on die.
2. (NC) = Depending on device option, pin may be either signal as named or NC (see Table 1).
Figure 2. Pin Diagram
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Table 1. Device Option: Signal and Pin Description
Pkg
Pin
#
UT8ER1M32M
(Master)
Signal Name
UT8ER1M32S
(Slave)
Signal Name
UT8ER2M32M
(Master)
Signal Name
UT8ER2M32S
(Slave)
Signal Name
UT8ER4M32M
(Master)
Signal Name
UT8ER4M32S
(Slave)
Signal Name
Device
Pin
Description
1
VSS
VSS
VSS
VSS
VSS
VSS
PWR
2
VSS
VSS
VSS
VSS
VSS
VSS
PWR
3
DQ0
DQ0
DQ0
DQ0
DQ0
DQ0
DATA I/O
4
DQ1
DQ1
DQ1
DQ1
DQ1
DQ1
DATA I/O
5
DQ2
DQ2
DQ2
DQ2
DQ2
DQ2
DATA I/O
6
DQ3
DQ3
DQ3
DQ3
DQ3
DQ3
DATA I/O
7
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
PWR
8
VSS
VSS
VSS
VSS
VSS
VSS
PWR
9
DQ4
DQ4
DQ4
DQ4
DQ4
DQ4
DATA I/O
10
DQ5
DQ5
DQ5
DQ5
DQ5
DQ5
DATA I/O
11
DQ6
DQ6
DQ6
DQ6
DQ6
DQ6
DATA I/O
12
DQ7
DQ7
DQ7
DQ7
DQ7
DQ7
DATA I/O
13
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
PWR
14
VSS
VSS
VSS
VSS
VSS
VSS
PWR
15
NC
NC
NC
NC
NC
NC
NC
16
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
PWR
17
NC
NC
NC
NC
NC
NC
NC
18
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
PWR
19
NC
NC
NC
NC
NC
NC
NC
20
VSS
VSS
VSS
VSS
VSS
VSS
PWR
21
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
PWR
22
DQ8
DQ8
DQ8
DQ8
DQ8
DQ8
DATA I/O
23
DQ9
DQ9
DQ9
DQ9
DQ9
DQ9
DATA I/O
24
DQ10
DQ10
DQ10
DQ10
DQ10
DQ10
DATA I/O
25
DQ11
DQ11
DQ11
DQ11
DQ11
DQ11
DATA I/O
26
VSS
VSS
VSS
VSS
VSS
VSS
PWR
27
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
PWR
28
DQ12
DQ12
DQ12
DQ12
DQ12
DQ12
DATA I/O
29
DQ13
DQ13
DQ13
DQ13
DQ13
DQ13
DATA I/O
30
DQ14
DQ14
DQ14
DQ14
DQ14
DQ14
DATA I/O
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Table 1. Device Option: Signal and Pin Description
Pkg
Pin
#
UT8ER1M32M
(Master)
Signal Name
UT8ER1M32S
(Slave)
Signal Name
UT8ER2M32M
(Master)
Signal Name
UT8ER2M32S
(Slave)
Signal Name
UT8ER4M32M
(Master)
Signal Name
UT8ER4M32S
(Slave)
Signal Name
Device
Pin
Description
31
DQ15
DQ15
DQ15
DQ15
DQ15
DQ15
DATA I/O
32
VSS
VSS
VSS
VSS
VSS
VSS
PWR
33
VSS
VSS
VSS
VSS
VSS
VSS
PWR
34
VSS
VSS
VSS
VSS
VSS
VSS
PWR
35
A11
A11
A11
A11
A11
A11
ADDRESS
INPUT
36
A12
A12
A12
A12
A12
A12
ADDRESS
INPUT
37
A13
A13
A13
A13
A13
A13
ADDRESS
INPUT
38
VSS
VSS
VSS
VSS
VSS
VSS
PWR
39
NC
NC
NC
NC
NC
NC
NC
40
NC
NC
NC
NC
NC
NC
NC
41
NC
NC
NC
NC
NC
NC
NC
42
VSS
VSS
VSS
VSS
VSS
VSS
PWR
43
BUSY#
NC
BUSY#
NC
BUSY#
NC
OUTPUT1
44
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
PWR
45
NC
NC
NC
NC
E7#
E7#
CONTROL
INPUT2
46
NC
NC
NC
NC
E5#
E5#
CONTROL
INPUT2
47
NC
NC
E3#
E3#
E3#
E3#
CONTROL
INPUT2
48
E1#
E1#
E1#
E1#
E1#
E1#
CONTROL
INPUT
49
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
PWR
50
G#
G#
G#
G#
G#
G#
CONTROL
INPUT
51
VSS
VSS
VSS
VSS
VSS
VSS
PWR
52
E2#
E2#
E2#
E2#
E2#
E2#
CONTROL
INPUT
53
NC
NC
E4#
E4#
E4#
E4#
CONTROL
INPUT2
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Table 1. Device Option: Signal and Pin Description
Pkg
Pin
#
UT8ER1M32M
(Master)
Signal Name
UT8ER1M32S
(Slave)
Signal Name
UT8ER2M32M
(Master)
Signal Name
UT8ER2M32S
(Slave)
Signal Name
UT8ER4M32M
(Master)
Signal Name
UT8ER4M32S
(Slave)
Signal Name
Device
Pin
Description
54
NC
NC
NC
NC
E6#
E6#
CONTROL
INPUT2
55
NC
NC
NC
NC
E8#
E8#
CONTROL
INPUT2
56
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
PWR
57
SCRUB#
SCRUB#
SCRUB#
SCRUB#
SCRUB#
SCRUB#
CONTROL
I/O3
58
MBE
MBE
MBE
MBE
MBE
MBE
DATA I/O
59
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
PWR
60
NC
NC
NC
NC
NC
NC
NC
61
NC
NC
NC
NC
NC
NC
NC
62
VSS
VSS
VSS
VSS
VSS
VSS
PWR
63
A14
A14
A14
A14
A14
A14
ADDRESS
INPUT
64
A15
A15
A15
A15
A15
A15
ADDRESS
INPUT
65
A16
A16
A16
A16
A16
A16
ADDRESS
INPUT
66
VSS
VSS
VSS
VSS
VSS
VSS
PWR
67
VSS
VSS
VSS
VSS
VSS
VSS
PWR
68
VSS
VSS
VSS
VSS
VSS
VSS
PWR
69
DQ31
DQ31
DQ31
DQ31
DQ31
DQ31
DATA I/O
70
DQ30
DQ30
DQ30
DQ30
DQ30
DQ30
DATA I/O
71
DQ29
DQ29
DQ29
DQ29
DQ29
DQ29
DATA I/O
72
DQ28
DQ28
DQ28
DQ28
DQ28
DQ28
DATA I/O
73
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
PWR
74
VSS
VSS
VSS
VSS
VSS
VSS
PWR
75
DQ27
DQ27
DQ27
DQ27
DQ27
DQ27
DATA I/O
76
DQ26
DQ26
DQ26
DQ26
DQ26
DQ26
DATA I/O
77
DQ25
DQ25
DQ25
DQ25
DQ25
DQ25
DATA I/O
78
DQ24
DQ24
DQ24
DQ24
DQ24
DQ24
DATA I/O
79
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
PWR
80
VSS
VSS
VSS
VSS
VSS
VSS
PWR
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Table 1. Device Option: Signal and Pin Description
Pkg
Pin
#
UT8ER1M32M
(Master)
Signal Name
UT8ER1M32S
(Slave)
Signal Name
UT8ER2M32M
(Master)
Signal Name
UT8ER2M32S
(Slave)
Signal Name
UT8ER4M32M
(Master)
Signal Name
UT8ER4M32S
(Slave)
Signal Name
Device
Pin
Description
81
NC
NC
NC
NC
NC
NC
NC
82
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
PWR
83
NC
NC
NC
NC
NC
NC
NC
84
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
PWR
85
NC
NC
NC
NC
NC
NC
NC
86
VSS
VSS
VSS
VSS
VSS
VSS
PWR
87
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
PWR
88
DQ23
DQ23
DQ23
DQ23
DQ23
DQ23
DATA I/O
89
DQ22
DQ22
DQ22
DQ22
DQ22
DQ22
DATA I/O
90
DQ21
DQ21
DQ21
DQ21
DQ21
DQ21
DATA I/O
91
DQ20
DQ20
DQ20
DQ20
DQ20
DQ20
DATA I/O
92
VSS
VSS
VSS
VSS
VSS
VSS
PWR
93
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
PWR
94
DQ19
DQ19
DQ19
DQ19
DQ19
DQ19
DATA I/O
95
DQ18
DQ18
DQ18
DQ18
DQ18
DQ18
DATA I/O
96
DQ17
DQ17
DQ17
DQ17
DQ17
DQ17
DATA I/O
97
DQ16
DQ16
DQ16
DQ16
DQ16
DQ16
DATA I/O
98
VSS
VSS
VSS
VSS
VSS
VSS
PWR
99
VSS
VSS
VSS
VSS
VSS
VSS
PWR
100
VSS
VSS
VSS
VSS
VSS
VSS
PWR
101
VSS
VSS
VSS
VSS
VSS
VSS
PWR
102
A10
A10
A10
A10
A10
A10
ADDRESS
INPUT
103
A9
A9
A9
A9
A9
A9
ADDRESS
INPUT
104
A8
A8
A8
A8
A8
A8
ADDRESS
INPUT
105
A7
A7
A7
A7
A7
A7
ADDRESS
INPUT
106
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
PWR
107
VSS
VSS
VSS
VSS
VSS
VSS
PWR
108
A6
A6
A6
A6
A6
A6
ADDRESS
INPUT
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Table 1. Device Option: Signal and Pin Description
Pkg
Pin
#
UT8ER1M32M
(Master)
Signal Name
UT8ER1M32S
(Slave)
Signal Name
UT8ER2M32M
(Master)
Signal Name
UT8ER2M32S
(Slave)
Signal Name
UT8ER4M32M
(Master)
Signal Name
UT8ER4M32S
(Slave)
Signal Name
Device
Pin
Description
109
W#
W#
W#
W#
W#
W#
CONTROL
INPUT
110
A18
A18
A18
A18
A18
A18
ADDRESS
INPUT
111
NC
NC
NC
NC
NC
NC
NC
112
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
PWR
113
NC
NC
NC
NC
NC
NC
NC
114
NC
NC
NC
NC
NC
NC
NC
115
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
PWR
116
NC
NC
NC
NC
NC
NC
NC
117
VSS
VSS
VSS
VSS
VSS
VSS
PWR
118
NC
NC
NC
NC
NC
NC
NC
119
NC
NC
NC
NC
NC
NC
NC
120
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
PWR
121
NC
NC
NC
NC
NC
NC
NC
122
A17
A17
A17
A17
A17
A17
ADDRESS
INPUT
123
A5
A5
A5
A5
A5
A5
ADDRESS
INPUT
124
A4
A4
A4
A4
A4
A4
ADDRESS
INPUT
125
VSS
VSS
VSS
VSS
VSS
VSS
PWR
126
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
PWR
127
A3
A3
A3
A3
A3
A3
ADDRESS
INPUT
128
A2
A2
A2
A2
A2
A2
ADDRESS
INPUT
129
A1
A1
A1
A1
A1
A1
ADDRESS
INPUT
130
A0
A0
A0
A0
A0
A0
ADDRESS
INPUT
131
VSS
VSS
VSS
VSS
VSS
VSS
PWR
132
VSS
VSS
VSS
VSS
VSS
VSS
PWR
Notes:
NC Pins are not connected on the die
1. BUSY# pin is an output for master devices only, and is a NC for slave devices.
2. Control input when shown as En#, otherwise pin is NC.
3. SCRUB# is an output for master devices, but an input for slave devices.
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MASTER or SLAVE OPTIONS
Table 3. EDAC Control Pin Operation Truth Table
To reduce the bit error rates, the SRAM devices employ an
embedded EDAC (error detection and correction) with user
programmable auto scrubbing options. The SRAM devices can
automatically correct single bit word errors in event of an upset.
During a read operation, if a multiple bit error occurs in a word,
the SRAMs assert the MBE output to notify the host.
All SRAM devices are offered in two options: Master
(UT8ER1M32M, UT8ER2M32M and UT8ER4M32M) or
Slave (UT8ER1M32S, UT8ER2M32S and UT8ER4M32S).
The masters are a full function device which features user
defined autonomous EDAC scrubbing options. The slave device
employs a scrub on demand feature.
The master and slave device pins SCRUB and BUSY are
physically different. The SCRUB pin is an output on the master
device, but an input on the slave device. The master SCRUB pin
asserts low when a scrub cycle initiates, and can be used to
demand scrub cycles from multiple slave units when connected
to the SCRUB input of slave(s). The BUSY pin is an output for
the master device and can be used to generate wait states by the
memory controller. The BUSY pin is a no connect (NC) for slave
devices.
MBE
SCRUB
BUSY
I/O Mode
Mode
H
H
H
Read
Uncorrectable
Multiple Bit Error
L
H
H
Read
Valid Data Out
X
H
H
X
Device Ready
X
H
L
X
Device Ready /
Scrub Request
Pending
X
L
X
Not
Accessible
Device Busy
Notes:
1. “X” is defined as a “don’t care” condition
2. BUSY signal is a "NC" for slave devices and are an "X" don’t care.
READ CYCLE
A combination of W greater than VIH (min) with a single En and
G less than VIL (max) defines a read cycle. Read access time is
measured from the latter of device enable, output enable, or valid
address to valid data output.
DEVICE OPERATION
The SRAMs have control inputs called Chip Enable (En), Write
Enable (W), and Output Enable (G); 19 address inputs, A(18:0);
and 32 bidirectional data lines, DQ(31:0). The En (chip enable)
controls selection between active and standby modes. Asserting
En enables the device, causes IDD to rise to its active value, and
decodes the 19 address inputs. Only one chip enable may be
active at any time. W controls read and write operations. During
a read cycle, G must be asserted to enable the outputs.
SRAM Read Cycle 1, the Address Access in Figure 3a, is
initiated by a change in address inputs after a single En is
asserted, G is asserted, W is deasserted and all are stable. Valid
data appears on data outputs DQ(31:0) after the specified tAVQV
is satisfied. Outputs remain active throughout the entire cycle.
As long as device enable and output enable are active, the
minimum time between valid address changes is specified by
the read cycle time (tAVAV).
Table 2. SRAM Device Control Operation Truth Table
SRAM Read Cycle 2, the Chip Enable-controlled Access in
Figure 3b is initiated by a single En going active while G remains
asserted, W remains deasserted, and the addresses remain stable
for the entire cycle. After the specified tETQV is satisfied, the
32-bit word addressed by A(18:0) is accessed and appears at the
data outputs DQ(31:0).
G
W
En
I/O Mode
Mode
X
X
H
DQ(31:0)
3-State
Standby
L
H
L
DQ(31:0)
Data Out
Word Read
H
H
L
DQ(31:0)
All 3-State
Word
Read2
X
L
L
DQ(31:0)
All 3-State
Word Write
SRAM Read Cycle 3, the Output Enable-controlled Access in
Figure 3c, is initiated by G going active while a single En is
asserted, W is deasserted, and the addresses are stable. Read
access time is tGLQV unless tAVQV or tETQV (reference Figure
3b) have not been satisfied.
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
36-00-01-009
Version 1.0.0
SRAM EDAC Status Indications during a Read Cycle, if MBE
is Low, the data is valid. If MBE is High, the data is corrupted
(reference Table 3).
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The effective error rate is a function of the intrinsic error rate
and the environment. Therefore, users are given the ability to
control the scrub rate (ref. figure 7a) appropriate for the
applicable environment. NOTE: the scrub rate will have an
inverse relationship to the total throughput of the memory.
WRITE CYCLE
A combination of W and a single En less than VIL(max) defines
a write cycle. The state of G is a “don’t care” for a write cycle.
The outputs are placed in the high-impedance state when either
G is greater than VIH(min) or when W is less than VIL(max).
A master mode scrub cycle will occur at the user defined Scrub
Rate Period. A scrub cycle is defined as the verification and
correction (if necessary) of data for a single word address
location. Address locations are scrubbed sequentially every
Scrub Rate Period (tSCRT). Scrub cycles will occur at every
Scrub Rate Period regardless of the status of control pins. All
inputs should remain stable while the SCRUB signal is active
to avoid data corruption. Control pin function will be returned
upon deassertion of BUSY pin. The Slave mode scrub cycle
occurs anytime the SCRUB pin is asserted. The scrub cycle is
defined the same as the master mode and will occur regardless
of control pin status. Control pin function will be returned upon
SCRUB deassertion.
Write Cycle 1, the Write Enable-controlled Access in Figure 4a,
is defined by a write terminated by W going high with a single
En still active. The write pulse width is defined by tWLWH when
the write is initiated by W and by tETWH when the write is
initiated by En. To avoid bus contention tWLQZ must be satisfied
before data is applied to the 32 bidirectional pins DQ(31:0)
unless the outputs have been previously placed in high
impedance state by deasserting G.
Write Cycle 2, the Chip Enable-controlled Access in Figure 4b,
is defined by a write terminated by a single En. The write pulse
width is defined by tWLEF when the write is initiated by W and
by tETEF when the write is initiated by En going active. For the
W initiated write, unless the outputs have been previously placed
in the high-impedance state by G, the user must wait tWLQZ
before applying data to the 32 bidirectional pins DQ(31:0) to
avoid bus contention.
Data is corrected during not only the internal scrub, but again
during a user requested read cycle. If the data presented contains two or more errors after tAVAV is satisfied, the MBE signal
will be asserted. (Note: Reading un-initialized memory
locations may result in un-intended MBE assertions.)
Table 4. Operational Environment1
CONTROL REGISTER WRITE/READ CYCLES
Configuration options can be selected by writing to the control
register. The configuration tables (Tables 5 and 6) details the
programming options. Scrub rate period and BUSY to SCRUB
configurations are applicable to master devices using E1 chip
enable only. EDAC bypass and Read/Write control register is
applicable to all valid chip enables En. The control register is
accessed by applying a series of values to the address bus as
shown in Figures 7a and 7b. After the series the contents of the
control register can be either read or written depending on the
value of the corresponding read/write control register address
pin (A(9) for odd die and A(2) for even die). NOTE: MBE must
be driven high by the user for both a write or a read of the control
register.
100k
rads(Si)
Heavy Ion
Error Rate2
8.1x10-16
Errors/Bit-Day
Notes:
1. The SRAM is immune to latchup to particles <110MeV-cm2/mg.
2. 90% worst case particle environment, Geosynchronous orbit, 100 mils of
Aluminum and default EDAC scrub rate.
SUPPLY SEQUENCING
No supply voltage sequencing is required between VDD1 and
VDD2.
POWER-UP REQUIREMENTS
During power-up of the SRAM devices, the power supply
voltages will transverse through voltage ranges where the device
is not guaranteed to operate before reaching final levels. Since
some circuits on the device may operate at lower voltage levels
than others, the device may power-up in an unknown state. To
eliminate this with most power-up situations, the device
employs an on-chip power-on-reset (POR) circuit. The POR,
however, requires time to complete the operation. Therefore, it
is recommended that all device activity be delayed by a
minimum of 100ms, after both VDD1 and VDD2 supplies have
reached stable minimum operating voltage.
MEMORY SCRUBBING/CYCLE STEALING
The SRAMs use architectural improvements and embedded
error detection and correction to maintain unsurpassed levels of
error protection. This is accomplished by what Aeroflex refers
to as Cycle Stealing. To minimize the system design impact on
the speed of operation, the edge relationship between BUSY and
SCRUB is programmable via the sequence described in figures
7a and 7b. The BUSY output is intended to give notification to
the memory controller that a scrub cycle is impending. Since the
memory cannot be accessed during an internal scrub cycle, the
BUSY to SCRUB delay can be adjusted so the user may
complete accesses prior to internal scrubbing.
36-00-01-009
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ABSOLUTE MAXIMUM RATINGS1
(Referenced to VSS)
SYMBOL
PARAMETER
LIMITS
VDD1
DC supply voltage (Core)
-0.3 to 2.1V
VDD2
DC supply voltage (I/O)
-0.3 to 3.8V
VI/O
Voltage on any pin
-0.3 to 3.8V
TSTG
Storage temperature
-65 to +150°C
PD2:
Maximum package power dissipation
permitted @ Tc = +105oC
UT8ER1M32
UT8ER2M32
UT8ER4M32
TJ
ΘJC3:
UT8ER1M32
UT8ER2M32
UT8ER4M32
II
Maximum junction temperature
3.3W
2W
1.3W
+150°C
Thermal resistance, junction-to-case2
6oC/W
10oC/W
15oC/W
±10 mA
DC input current
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Per MIL-STD-883, Method 1012, Section 3.4.1, PD = (125oC - 105oC)
3. ΘJC varies with density due to stacked die configuration.
ΘJC
RECOMMENDED OPERATING CONDITIONS
SYMBOL
36-00-01-009
Version 1.0.0
PARAMETER
LIMITS
VDD1
DC supply voltage (Core)
1.7 to 2.0V
VDD2
DC supply voltage (I/O)
2.3 to 3.6V
TC
Case temperature range
-55 to +105°C
VIN
DC input voltage
0V to VDD2
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DC ELECTRICAL CHARACTERISTICS (Pre and Post-Radiation)*
(VDD1 = 1.7V to 2.0V, VDD2 = 2.3V to 3.6V; Unless otherwise noted, Tc is per the temperature range ordered)
SYMBOL
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
0.8
V
VOL11
Low-level output voltage IOL = 8mA, 3.0V<VDD2 < 3.6V
0.4
V
VOL21
Low-level output voltage IOL = 6mA, 2.3V<VDD2 < 2.7V
0.2*VDD2
VOH1
High-level output
voltage
IOH = -4mA,3.0V< VDD2 < 3.6V
0.8*VDD2
V
VOH2
High-level output
voltage
IOL = -2mA, 2.3V<VDD2 < 2.7V
0.8*VDD2
V
Input leakage current
VIN = VDD2 and VSS
-2
2
μA
IOZ3
Three-state output
leakage current
VO = VDD2 and VSS
VDD2 = VDD2 (max), G = VDD2
(max)
-2
2
μA
IOS4, 5
Short-circuit output
current
VDD2 = VDD2 (max), VO = VDD2
VDD2 = VDD2 (max), VO = VSS
-100
+100
mA
VDD1 Supply current
read operation
@ 1MHz, EDAC enabled
@ default Scrub Rate
Period (see table 5).
Inputs: VIL = VSS + 0.2V,
VIH = VDD2 -0.2V, IOUT = 0
VDD1 = VDD1 (max),
VDD2 = VDD2 (max)
VDD1 = 2.0V
14
mA
VDD1 = 1.9V
10
mA
VDD1 Supply current
read operation
@ fmax, EDAC enabled
@ default Scrub Rate
Period (see table 5).
Inputs: VIL = VSS + 0.2V,
VIH = VDD2 -0.2V, IOUT = 0
VDD1 = VDD1 (max),
VDD2 = VDD2 (max)
VDD1 = 2.0V
VDD1 = 1.9V
UT8ER4M32
230
215
mA
mA
VDD1 = 2.0V
VDD1 = 1.9V
UT8ER1M32
UT8ER2M32
225
210
mA
mA
IDD2(OP16,8)
VDD2 Supply current
read operation
@ 1MHz, EDAC enabled
@ default Scrub Rate
Period (see table 5).
Inputs : VIL = VSS + 0.2V,
VIH = VDD2 -0.2V, IOUT = 0
VDD1 = VDD1 (max), VDD2 = VDD2
(max)
2
mA
IDD2(OP26,8,9)
VDD2 Supply current
read operation
@ fmax, EDAC enabled
@ default Scrub Rate
Period (see table 5).
Inputs : VIL = VSS + 0.2V,
VIH = VDD2 -0.2V, IOUT = 0
VDD1 = VDD1 (max), VDD2 = VDD2
(max)
5
mA
IIN
IDD1(OP16,8)
IDD1(OP26,8,9)
36-00-01-009
Version 1.0.0
CONDITION
MIN
MAX
2.2
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UNIT
V
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SYMBOL
IDD1(SB)7,10
IDD2(SB)10
IDD1(SB)7,9,10
IDD2(SB)9,10
PARAMETER
Supply current standby
@ 0Hz, EDAC disabled
(per die)
Supply current standby
@ 0Hz, EDAC disabled
(per die)
Supply current standby
A(16:0) @ fmax, EDAC
disabled
(per die)
Supply current standby
A(16:0) @ fmax, EDAC
disabled
(per die)
CONDITION
MIN
CMOS inputs, IOUT = 0
En = VDD2 -0.2
MAX
UNIT
-55oC and
25oC
15
mA
105oC
35
mA
3
mA
-55oC and
25oC
15
mA
105oC
35
mA
3
mA
VDD1 = VDD1 (max), VDD2 = VDD2
(max)
CMOS inputs, IOUT = 0
En = VDD2 -0.2
VDD1 = VDD1 (max), VDD2 = VDD2
(max)
CMOS inputs , IOUT = 0
En = VDD2 - 0.2
VDD1 = VDD1 (max), VDD2 = VDD2
(max)
CMOS inputs, IOUT = 0
En = VDD2 - 0.2
VDD1 = VDD1 (max), VDD2 = VDD2
(max)
CAPACITANCE
SYMBOL
PARAMETER
CONDITION
UT8ER1M32
MIN
MAX
UT8ER2M32
MIN
MAX
UT8ER4M32
MIN
UNIT
MAX
CIN2
Input capacitance
ƒ = 1MHz @ 0V
18
29
50
pF
CEn2
Input capacitance
Device Enables
ƒ = 1MHz @ 0V
10
10
10
pF
CIO2
Bidirectional I/O
capacitance
ƒ = 1MHz @ 0V
15
27
50
pF
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. The SCRUB and BUSY pins for UT8ER1M32M, UT8ER2M32M and UT8ER4M32M (master) are tested functionally for VOL specification.
2. Measured only for initial qualification and after process or design changes that could affect this parameter.
3. The SCRUB and BUSY pins for UT8ER1M32M, UT8ER2M32M and UT8ER4M32M (master) are guaranteed by design, but neither tested nor characterized.
4. Supplied as a design limit but not guaranteed or tested.
5. Not more than one output may be shorted at a time for maximum duration of one second.
6. EDAC enabled. Default Scrub Rate Period applicable to master device only.
7. Post radiation limits are the 105oC temperature limit when specified.
8. Operating current limit does not include standby current.
9. fmax = 50MHz.
10. VIH = VDD2 (max), VIL = 0V.
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AC CHARACTERISTICS READ CYCLE (Pre and Post-Radiation)*
(VDD1 = 1.7V to 2.0V, VDD2 = 2.3V to 3.6V); Unless otherwise noted, Tc is per the temperature range ordered
SYMBOL
PARAMETER
tAVAV11
Read cycle time
tAVQV1
Address to data valid from
address change
tAXQX2
Output hold time
tGLQX1,2
G-controlled output enable time
UT8ER1M32
MIN
MAX
20
UT8ER2M32
MIN
MAX
22
20
UT8ER4M32
MIN
MAX
25
22
25
UNIT
FIGURE
ns
3a
ns
3c
1.5
1.5
1.5
ns
3a
1
1
1
ns
3c
10
ns
3c
8
ns
3c
ns
3b
25
ns
3b
9
ns
3b
25
ns
3a
tGLQV
G-controlled output data valid
tGHQZ12
G-controlled output three-state
time
1
tETQX2
E-controlled output enable time
4
tETQV
E-controlled access time
tEFQZ2
E-controlled output three-state
time2
tAVMV
Address to error flag valid
tAXMX2
Address to error flag hold time
from address change
1.5
1.5
1.5
ns
3a
tGLMX2
G-controlled error flag enable
time
0
0
0
ns
3c
tGLMV
G-controlled error flag valid
ns
3c
tETMX2
E-controlled error flag enable
time
ns
3b
tETMV
E-controlled error flag time
25
ns
3b
tGHMZ2
G-controlled error flag three-state
time
9
ns
3b
10
10
8
1
4
20
2
1
4
22
9
2
22
9
2
22
8
8
4
4
22
1
8
8
4
22
9
1
9
1
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. Guaranteed by characterization, but not tested.
2. Three-state is defined as a change from steady-state output voltage.
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tAVAV1
A(18:0)
DQ(31:0)
Previous Valid Data
Valid Data
MBE
Valid Data
tAVQV1, tAVMV
Assumptions:
1. En and G < VIL (max) and W > VIH (min)
2. SCRUB > VOH (min)
3. Reading uninitialized addresses may cause
MBE to be asserted.
tAXQX, tAXMX
Figure 3a. SRAM Read Cycle 1: Address Access
A(18:0)
En
tETQV, tETMV
tETQX, tETMX
tEFQZ
DQ(31:0)
DATA VALID
MBE
DATA VALID
Assumptions:
1. G < VIL (max) and W > VIH (min)
2. SCRUB > VOH (min)
3. Reading uninitialized addresses may cause
MBE to be asserted.
Figure 3b. SRAM Read Cycle 2: Chip Enable Access
tAVQV1
tAVMV
A(18:0)
tGLQV
G
tGHQZ1
tGLQX1
DQ(31:0)
DATA VALID
tGLMX
MBE
DATA VALID
Assumptions:
1. En < VIL (max), W > VIH (min)
tGLMV
tGHMZ
2. SCRUB > VOH (min)
3. Reading uninitialized addresses may cause
MBE to be asserted.
36-00-01-009
Version 1.0.0
Figure 3c. SRAM Read Cycle 3: Output Enable Access
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AC CHARACTERISTICS WRITE CYCLE (Pre and Post-Radiation)*
(VDD1 = 1.7V to 2.0V, VDD2 = 2.3V to 3.6V); Unless otherwise noted, Tc is per the temperature range ordered
SYMBOL
PARAMETER
UT8ER1M32
MIN
MAX
UT8ER2M32
MIN
MAX
UT8ER4M32
MIN
UNIT
FIGURE
MAX
tAVAV21
Write cycle time
10
10
10
ns
4a/4b
tETWH
Device enable to end of write
10
10
10
ns
4a
tAVET
Address setup time for write
(En- controlled)
0
0
0
ns
4b
tAVWL
Address setup time for write
(W - controlled)
0
0
0
ns
4a
tWLWH1
Write pulse width
8
8
8
ns
4a
tWHAX
Address hold time for write
(W - controlled)
0
0
0
ns
4a
tEFAX
Address hold time for device
enable (En- controlled)
0
0
0
ns
4b
ns
4a/4b
tWLQZ2
W - controlled three-state time
tWHQX2
W - controlled output enable time
0
0
0
ns
4a
tETEF
Device enable pulse width
(En - controlled)
10
10
10
ns
4b
tDVWH
Data setup time
5
5
6
ns
4a
tWHDX
Data hold time
0
0
0
ns
4a
tWLEF1
Device enable controlled write
pulse width
8
8
8
ns
4b
tDVEF
Data setup time
5
5
6
ns
4a/4b
tEFDX
Data hold time
0
0
0
ns
4b
tAVWH
Address valid to end of write
10
10
10
ns
4a
Write disable time
2
2
3
ns
4a
tWHWL1
9
9
9
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. Tested with G high.
2. Three-state is defined as a change from steady-state output voltage.
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A(18:0)
tAVAV2
En
tAVWH
tETWH, tWLEF
tWHWL
W
tAVWL
tWLWH
tWHAX
Q(31:0)
tWHQX
tWLQZ
D(31:0)
APPLIED DATA
tDVWH, tDVEF
Assumptions:
1. G < VIL (max). (If G > VIH (min) then Q(31:0) and MBE will be in threestate for the entire cycle.)
tWHDX
2. SCRUB > VOH (min)
Figure 4a. SRAM Write Cycle 1: W - Controlled Access
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tAVAV2
A(18:0)
tAVET
tETEF
tEFAX
En
tWLEF
W
APPLIED DATA
D(31:0)
tDVEF
Q(31:0)
tEFDX
Assumptions & Notes:
1. G < VIL (max). (If G > VIH (min) then Q(31:0) and MBE will be in three-state for the entire cycle.)
2. Busy > VOH (min)
Figure 4b. SRAM Write Cycle 2: Enable - Controlled Access
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A9 A8
A7 A6
A5
A4
A3 A2
A1 A0
Scrub Rate Period (Default = 7h)
BUSY to SCRUB (Default = Ah)
EDAC Bypass (Default = 0h)
Read / Write Control Register
Note:
1. See Table 5 for Control Register Definitions
Figure 5. (Odd Die Numbers (E1, E3, E5, E7 Chip Enables) EDAC Control Register
Table 5: (Odd Die Numbers (E1, E3, E5, E7 Chip Enables) EDAC Programming Configuration Table
ADDR BIT
A (3-0)
PARAMETER
Scrub Rate Period
1,2,3
VALUE
FUNCTION
3-15
As Scrub Rate Period changes from 0 - 15, then the interval
between Scrub cycles will change as follows:
3 = 600 ns
8 = 13.0 us
12 = 205 us
Note:
0-2
4 = 1000 ns
reserved 5 = 1800 ns
6 = 3400 ns
7 = 6600 ns
A (7-4)
9 = 25.8 us
13 = 409.8 us4
10 = 51.4 us
14 = 819.4 us4
11 = 102.6 us
15 = 1.64 ms4
BUSY to SCRUB1,3,5
0-15
If BUSY to SCRUB changes from 0 - 15, then the interval
tBLSL between SCRUB and BUSY will change as follows:
0 = 0 ns
6 = 300 ns
11 = 550 ns
1 = 50 ns
7 = 350 ns
12 = 600 ns
2 = 100 ns
8 = 400 ns
13 = 650 ns
3 = 150 ns
9 = 450 ns
14 = 700 ns
4 = 200 ns
10 = 500 ns
15 = 750 ns
5 = 250ns
A (8)
Bypass EDAC Bit6,7
0, 1
If 0, then normal EDAC operation will occur.
If 1, then EDAC will be bypassed and no memory scrubbing
will occur.
A (9)
Read / Write Control Register
0, 1
0 = A8 to A0 will be written to the control register.
1 = Control register will be asserted to the data bus DQ[8:0]
respectively.
Notes:
1. Values based on minimum specifications. For guaranteed ranges of Scrub Rate Period (tSCRT) and BUSY to SCRUB (tBLSL), reference the Master Mode
AC Characteristic.
2. Default Scrub Rate Period is 6600 ns.
3. Scrub Rate Period and BUSY to SCRUB applicable to the master devices die #1 (E1 chip enable) only.
4. Period below test capability.
5. The default for tBLSL is 500 ns.
6. The default state for A8 is 0.
7. The EDAC bypass option is provided for memory accesses when error correction is not desired (i.e. device and system testing).
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A9 A8
A7 A6
A5
A4
A3 A2
A1 A0
Read / Write Control Register
EDAC Bypass (Default = 0h)
Note:
X = Not applicable for even die.
1. See Table 6 for Control Register Definitions
Figure 6. Even Die Numbers (E2, E4, E6, E8 Chip Enables) EDAC Control Register
Table 6: Even Die Numbers (E2, E4, E6, E8 Chip Enables) EDAC Programming Configuration Table
ADDR BIT
PARAMETER
1,2
A (2)
Bypass EDAC Bit
A (1)
Read / Write Control Register
VALUE
FUNCTION
0, 1
If 0, then normal EDAC operation will occur.
If 1, then EDAC will be bypassed and no memory scrubbing
will occur.
0, 1
0 = A2 will be written to the control register
1 = Control register will be asserted to the data bus DQ18
Notes:
1. The default state for A2 is 0.
2. The EDAC bypass option is provided for memory accesses when error correction is not desired (i.e. device and system testing).
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EDAC CONTROL REGISTER AC CHARACTERISTICS (Pre and Post-Radiation)*
(VDD1 = 1.7V to 2.0V, VDD2 = 2.3V to 3.6V); Unless otherwise noted, Tc is per the temperature range ordered
SYMBOL
PARAMETER
UT8ER1M32
UT8ER2M32
UT8ER4M32
MIN
UNIT
FIGURE
MAX
tAVAV3
Address valid to address valid for control register cycle
200
ns
7a
tAVCL
Address valid to control low
400
ns
7a
tAVEX
Address valid to enable de-assertion
200
ns
7a
tAVQV3
Address to data valid control register read
ns
7a
tMLQX1
MBE control EDAC disable time
3
ns
7a
tCHAV
MBE high to address valid
0
ns
7a
tCLAX
MBE low to address invalid
0
ns
7a
tGHQZ31
Output tri-state time
2
ns
7a
tMLGL2
MBE low to output enable
85
ns
7a
400
9
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition A up to the maximum TID level procured.
1. Three-state is defined as a change from steady-state output.
2. Guaranteed by design neither tested or characterized.
En
Valid En, Device Enabled
tGHQZ3
G
tCLAX
tCHAV
tMLGL
MBE1
tAVEX
ADDR (18:0)2
70000h
7FF00h
3A500h
55A00h
10500h
00XYZh
Note 3
tMLQX
DQ (8:0)
tAVCL
tAVAV3
Control Reg.
Read
tAVQV3
Note:
1. MBE is driven high by the user.
2. Device must see a transition to address 70000h coincident with or subsequent to MBE assertion.
3. Lower 10 bits of the last address are used to read or configure the control register (ref Control Register Write/Read Cycles page 9 and Table 5).
Assumptions:
1. SCRUB > VOH before the start of the configuration cycle. Ignore SCRUB during configuration cycle.
Figure 7a. Odd Die Numbers (E1, E3, E5, E7 Chip Enables) EDAC Control Register Cycle
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En
Valid En, Device Enabled
tGHQZ3
G
tCLAX
tCHAV
tMLGL
MBE1
tAVEX
ADDR (18:0)
DQ18
2
20820h
3F827h
25805h
1A822h
00805h
00XYZh
Note 3
tMLQX
tAVCL
tAVAV3
Control Reg.
Read
t
AVQV3
Note:
1. MBE is driven high by the user.
2. Device must see a transition to address 20820h coincident with or subsequent to MBD assertion.
3. Bits A2 and A1 are used to read or configure the control register (ref Control Register Write/Read Cycles page 9 and Table 6).
Assumptions:
1. SCRUB > VOH before the start of the configuration cycle. Ignore SCRUB during configuration cycle.
Figure 7b. Even Die Numbers (E2, E4, E6, E8 Chip Enables) EDAC Control Register Cycle
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MASTER MODE AC CHARACTERISTICS (Pre and Post-Radiation)*
VDD1 = 1.7V to 2.0V, VDD2 = 2.3V to 3.6V); Unless otherwise noted, Tc is per the temperature range ordered
SYMBOL
PARAMETER
MIN
MAX
UNIT
FIGURE
tBLSL1
User Programmable - BUSY low to SCRUB
50*n
(90*n)+1
ns
7b
tSLSH1
SCRUB low to SCRUB high
200
350
ns
7b
tSHBH
SCRUB high to BUSY high
50
85
ns
7b
tSCRT2
Scrub Rate Period
2n*50+200
2n*90+350
ns
7b
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition A up to the maximum TID level procured.
1. See Table 5 for User Programmable information. The value "n" is decimal equivalent of hexidecimal value 0x0 through 0xF programmed into control register
address bits A4-A7 by user. Default value "n" = 10.
2. See Table 5 for User Programmable information. The value "n" is decimal equivalent of hexidecimal value 0x3 through 0xF programmed into control register
address bits A0-A3. Default value is "n" = 7.
tSLSH1
SCRUB
BUSY
tBLSL
tSHBH
Assumptions:
1. The conditions pertain to both a Read or Write.
Figure 7c. Master Mode Scrub Cycle
SLAVE MODE AC CHARACTERISTICS (Pre and Post-Radiation)*
VDD1 = 1.7V to 1.9V, VDD2 = 2.3V to 3.6V)Unless otherwise noted, Tc is per the temperature range ordered
SYMBOL
PARAMETER
MIN
MAX
UNIT
FIGURE
tSLSH2
SCRUB low to SCRUB high (slave)
200
ns
7c
tSHSL1
SCRUB high to SCRUB low (slave)
400
ns
7c
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019,
Condition A up to the maximum TID level procured.
1. Guaranteed by design, neither tested nor characterized.
tSLSH2
SCRUB
tSHSL
Assumptions:
1. The conditions pertain to both a Read or Write.
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VDD
VDD
RTERM
100ohm
CL = 40pF
DUT
Test
Point
Zo = 50ohm
RTERM
100ohm
VDD2
VSS
90%
90%
10%
< 2ns
10%
CMOS Input Pulses
< 2ns
Notes:
1. Measurement of data output occurs at the low to high or high to low transition mid-point (i.e., CMOS input = VDD2/2)
Figure 8. AC Test Loads and Input Waveforms
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PACKAGING
Figure 9. 132-Lead Side-Brazed Dual Cavity Ceramic Quad Flatpack
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ORDERING INFORMATION
32Mbit (1Mx32) SRAM MCM
64Mbit (2Mx32) SRAM MCM
128Mbit (4Mx32) SRAM MCM
UT ******** - * * * *
Lead Finish: (Note 1)
(C) = Gold
Screening: (Notes 2, 3)
(F) = HiRel Flow
(P) = Prototype Flow
(Temperature Range: -55°C to +105°C)
(Temperature Range: 25oC only)
Package Type:
(X) = 132-lead ceramic quad flatpack, side-brazed, dual cavity
Access Time: (Note 4)
(21) = 32Mbit device, 20ns read / 10ns write access times
(22) = 64Mbit device, 22ns read / 10ns write access times
(25) = 128Mbit device, 25ns read / 10ns write access times
Device Type:
(8ER1M32M) = 32Mbit (1Mx32) SRAM MCM Master Device
(8ER1M32S) = 32Mbit (1Mx32) SRAM MCM Slave Device
(8ER2M32M) =64Mbit (2Mx32) SRAM MCM Master Device
(8ER2M32S) = 64Mbit (2Mx32) SRAM MCM Slave Device
(8ER4M32M) = 128Mbit (4Mx32) SRAM MCM Master Device
(8ER4M32S) = 128Mbit (4Mx32) SRAM MCM Slave Device
Notes:
1. Lead finish is "C" (Gold) only.
2. Prototype Flow per Aeroflex Manufacturing Flows Document. Devices are tested at 25oC only. Lead finish is GOLD "C" only.
Radiation is neither tested nor guaranteed.
3. HiRel flow per Aeroflex Manufacturing Flows Document. Radiation is neither tested nor guaranteed.
4. Device option (21) is applicable to 32Mbit device t ypes only. Option (22) is applicable to 64Mbit device types only. Option (25)
is applicable to 128Mbit device types only.
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32Mbit (1Mx32) SRAM MCM:SMD
64Mbit (2Mx32) SRAM MCM:SMD
128Mbit (4Mx32) SRAM MCM:SMD
5962 * *****
** * * *
Lead Finish: (Note 1)
(C) = Gold
Case Outline:
(X) = 132-lead ceramic quad flatpack, side-brazed, dual cavity
Class Designator:
(Q) = QML Class Q
(V) = QML Class V (10202 and 10203 device options only)
Device Type (Note 2)
(01) = Master Device (-55°C to +105°C)
(02) = Slave Device (-55°C to +105°C)
(03) = Master Device Assembled with Aeroflex Q+ Flow (-55oC to +105oC)
(04) = Slave Device Assembled with Aeroflex Q+ Flow (-55oC to +105oC)
Drawing Number:
10202 = 32Mbit (1Mx32) SRAM MCM
10203 = 64Mbit (2Mx32) SRAM MCM
10204 = 128Mbit (4Mx32) SRAM MCM
Total Dose: (Note 3)
(R ) = 100krad(Si)
Federal Stock Class Designator: No options
Notes:
1.Lead finish is "C" (Gold) only.
2.Aeroflex’s Q+assembly flow, as defined in section 4.2.2.d of the SMD, provides QML-Q product through the SMD that is manufactured with Aeroflex’s standard QML-V flow.
3.TID tolerance guarantee of 1E5 is tested in accordance with MIL-STD-883 Test Method 1019 (condition A and section 3.11.2) resulting in an effective dose rate of 1 rad(Si)/sec.
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This product is controlled for export under the U.S. Department of Commerce (DoC). A license may be
required prior to the export of this product from the United States.
Cobham Semiconductor Solutions
4350 Centennial Blvd
Colorado Springs, CO 80907
E: [email protected]
T: 800 645 8862
Advanced Datasheets - Product is in Development
Preliminary Datasheet - Prototypes are Shipping
Datasheet - Shipping QML & Reduced Hi - Rel
Aeroflex Colorado Springs Inc., DBA Cobham Semiconductor Solutions, reserves the right to make changes to any products and services described
herein at any time without notice. Consult Aeroflex or an authorized sales representative to verify that the information in this data sheet is current
before using this product. Aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service
described herein, except as expressly agreed to in writing by Aeroflex; nor does the purchase, lease, or use of a product or service from Aeroflex
convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of Aeroflex or of third parties.
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Aeroflex Colorado Springs Application Note
AN-MEM-002
Low Power SRAM Read Operations
Table 1: Cross Reference of Applicable Products
Manufacturer
Part Number
SMD #
Device Type
Internal PIC
Number:*
4M Asynchronous SRAM
UT8R128K32
5962-03236
01 & 02
WC03
4M Asynchronous SRAM
UT8R512K8
5962-03235
01 & 02
WC01
16M Asynchronous SRAM
UT8CR512K32
5962-04227
01 & 02
MQ08
16M Asynchronous SRAM
UT8ER512K32
5962-06261
05 & 06
WC04/05
4M Asynchronous SRAM
UT8Q512E
5962-99607
05 & 06
WJ02
4M Asynchronous SRAM
UT9Q512E
5962-00536
05 & 06
WJ01
16M Asynchronous SRAM
UT8Q512K32E
5962-01533
02 & 03
QS04
16M Asynchronous SRAM
UT9Q512K32E
5962-01511
02 & 03
QS03
32M Asynchronous SRAM
UT8ER1M32
5962-10202
01 - 04
QS16/17
64M Asynchronous SRAM
UT8ER2M32
5962-10203
01 - 04
QS09/10
128M Asynchronous SRAM
UT8ER4M32
5962-10204
01 - 04
QS11/12
40M Asynchronous SRAM
UT8R1M39
5962-10205
01 & 02
QS13
80M Asynchronous SRAM
UT8R2M39
5962-10206
01 & 02
QS14
160M Asynchronous SRAM
UT8R4M39
5962-10207
01 & 02
QS15
Product Name:
* PIC = Aeroflex’s internal Product Identification Code
1.0 Overview
The purpose of this application note is to discuss the Aeroflex SRAMs low power read architecture and to inform users of the
affects associated with the low power read operations.
2.0 Low Power Read Architecture
The aforementioned Aeroflex designed SRAMs all employ an architecture which reduces power consumption during read
accesses. The architecture internally senses data only when new data is requested. A request for new data occurs anytime the
chip enable device pin is asserted, or any of the device address inputs transition states while the chip enable is asserted. A trigger is generated and sent to the sensing circuit anytime a request for new data is observed. Since several triggers could occur
simultaneously, these triggers are wire-ORed to result in a single sense amplifier activity for the read request. This design
method results in less power consumption than designs that continually sense data. Aeroflex’s low power SRAMs listed above
activate the sensing circuit for approximately 5ns whenever and access is requested, thereby, significantly reducing active
power.
Creation Date: 8/19/11
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AN-MEM-002
2.1 The SRAM Read Cycles.
The data sheets for all the devices noted in Table #1 discuss three methods for performing a read operation. The two most common methods for reading data are an Address Access and a Chip Enabled-Controlled Access. The third access discussed is the
Output Enable-Controlled Access. The sequence at which control lines and address inputs are toggled determines which cycle
is considered relevant. As discussed in section 2.0, an assertion of chip enable or any address transition while chip enable is
asserted, initiates a read cycle. If the device chip enable is asserted prior to any address input transitions, then the read access
is considered an Address Access. By keeping the device enabled and repeatedly switching address locations, the user retrieves
all data of interest. A Chip Enable-Controlled Access occurs when the address signals are stable prior to asserting the chip
enable. The Output Enabled-Controlled Access requires that either an Address Access or Chip Enable-Controlled Access has
already been performed and the data is waiting for the Output Enable pin to assert, driving data to the device I/O pins.
The subsequent read cycle verbiage and diagrams are based on the Aeroflex UT8R512K8 data sheet. The number of control,
input, and I/O pins will vary across the products listed in Table 1. The basic design family functionality for read operations is
common among all the devices.
2.1.0 Address Access Read Cycle
The Address Access is initiated by a change in address inputs while the chip is enabled with G asserted and W deasserted. Valid
data appears on data outputs DQ(7:0) after the specified tAVQV is satisfied. Outputs remain active throughout the entire cycle.
As long as chip enable and output enable are active, the address inputs may change at a rate equal to the minimum read cycle
time (tAVAV).
tAVAV
A(18:0)
DQ(7:0)
Previous Valid Data
Valid Data
tAVQV
Assumptions:
1. E1 and G < VIL (max) and E2 and W > VIH (min)
tAXQX
Note: No time references are relevant with respect to Chip Enable(s). Chip Enable(s) is assumed to be asserted.
SRAM Read Cycle 1: Address Access
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AN-MEM-002
2.1.1 Chip Enable-Controlled Read Cycle
The Chip Enable-controlled Access is initiated by E1 and E2 going active while G remains asserted, W remains deasserted, and
the addresses remain stable for the entire cycle. After the specified tETQV is satisfied, the eight-bit word addressed by A(18:0)
is accessed and appears at the data outputs DQ(7:0).
A(18:0)
E1 low or
E2 high
tETQV
tETQX
DQ(7:0)
tEFQZ
DATA VALID
Assumptions:
1. G < VIL (max) and W > VIH (min)
Note: No specification is given for address set-up time with respect to chip enable assertion. The read cycle description states that
addresses are to remain stable for the entire cycle. Address set-up time relative to chip enable is assumed to be 0ns minimum.
SRAM Read Cycle 2: Chip Enable Access
2.1.1 Output Enabled-Controlled Read Cycle
The Output Enable-controlled Access is initiated by G going active while E1 and E2 are asserted, W is deasserted, and the
addresses are stable. Read access time is tGLQV unless tAVQV or tETQV have not been satisfied.
tAVQV
A(18:0)
G
tGHQZ
tGLQX
DATA VALID
DQ(7:0)
tGLQV
Assumptions:
1. E1 < VIL (max) , E2 > and W > VIH (min)
SRAM Read Cycle 3: Output Enable Access
3.0 Low Power Read Architecture Timing Consideration
The low power read architecture employed by Aeroflex designed SRAMs results in significant power reduction, especially in
applications with longer than minimum read cycle times. However, this type of architecture is responsive to excessive input
signal skew when device addressing and chip enable assertion occur simultaneously. Signal skew of greater than 4-5ns
between all of the read triggering activities is sufficient to start another read cycle.
Creation Date: 8/19/11
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AN-MEM-002
3.1 Simultaneous Control and Address Switching
Simultaneous switching of controls and address pins, alone, is not a problem; excessive skew between them is the concern.
Consider the application where several SRAM devices are connected to the same memory bus. The address bus is commonly
connected to all the devices, but the chip enable pin is singularly connected to each individual SRAM. This configuration
results in a loading difference between the address inputs and the chip enable. This lightly loaded chip enable propagates to the
memory more quickly than the heavily loaded address lines. The oscilloscope capture of Figure #1 is the actual timing of an
application which had intermittent data errors due to address transitions lagging chip enable.
Address Signal (Ax)
Chip Enable (/E)

Timing shown from VIL (yellow trace /CS) and VIH (pink for address signal) as delta X =
6ns. Even at actual internal gate switching point (~ VDD/2), the skew is still around 6ns.
Figure #1 SRAM Signal Capture
The signal transitions in the scope plot of Figure #1 appear to be fairly coincidental. A closer look however, reveals the chip
enable signal actually starts and reaches VIL approximately 6ns before the address signal reaches VIH. Even at one half VDD
(closer to actual logical gate switching of the inputs), the delta in signal times is still approximately 6ns.
Simultaneous switching of controls and address inputs is not recommended for a couple of reasons. The first is the previously
described signal skew sensitivity between controls and/or address inputs. The second reason is that activating all the controls
and address inputs simultaneously results in peak instantaneous current consumption. This condition causes maximum strain
to the power decoupling. Chip Enable activates address decoding circuits, address switching introduces input buffer switching
current, and output enable assertion turns on all the device output drivers. Peforming all three simultaneously results in worst
case transient current demand by the memory.
3.1.0 Technical Overview of Skew Sensitivity
Recall from section 2.0 that any activity requesting new data causes a read trigger. The triggers are wire-ORed together. In
order to meet the faster access times demanded by today’s applications, the ORed trigger only exists during the first 4-5ns of
the read cycle. Since the slowest of the address transitions occurs more than 5ns after the initiation of the read activity, a second read activity is initiated. The sensing circuit does not have time to normalize before the second read activity has started.
For this reason a Chip Enable-Controlled read cycle requires that address inputs remain stable for the entire cycle. Infrequent
and random sensing errors can result if the bit columns are continually pulled to one state then quickly requested to sense the
opposite state. Another effect of the low power read architecture that differs from previous generation designs (those that continually sense for data) is that the bit line will not be sensed again until another read triggering event occurs. If another read
trigger event (chip enable assertion and/or address change) does no occur for a particular address, the incorrect data remains at
the outputs.
Creation Date: 8/19/11
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AN-MEM-002
4.0 Summary and Conclusion
The Aeroflex SRAMs in Table #1 all employ a low power consumption read architecture. Power is conserved by sensing data
only when new data is requested. A request occurs anytime chip enable is asserted or any address input signal transitions while
chip enable is asserted. The data sheets for the SRAMs listed in Table #1 do not explicitly define the case of simultaneous
switching of address and control signals during read operations. Data sheet read cycle descriptions indicate that control inputs
are established prior to address changes, and address inputs are stable prior to control assertions. Simultaneous switching of
addresses and controls is tolerable, when the skew between all input signals is < 4ns. For designs that must employ the simultaneous activation of address and control signals, two important issues should be considered by the designer. The first is the
input signal skew sensitivity of the low power read architecture discussed by this application note. The second is the instantaneous current consumption that results from simultaneous access methods. Aeroflex recommends the use of only one read
access method at a time. If multiple read accesses (simultaneous chip enable assertion and address switching) cannot be
avoided, then Aeroflex recommends that the chip enable signal be delayed until all addresses have completed transitions.
Creation Date: 8/19/11
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