CXB1575AQ 155Mbps Clock & Data Recovery with High Sensitivity Limiting Amplifier For the availability of this product, please contact the sales office. Description The CXB1575AQ achieves 3R optical-fiber communication receiver functions (Reshaping and Regenerating and Retiming) on a single chip. This IC also equipped with the signal interruption alarm output, which is used to discriminate the existence of data input. 40 pin QFP (Plastic) Features • Auto-offset canceler circuit • Signal interruption alarm output • No reference clock required • Single 3.3V power supply Applications • SONET/SDH: 155.52Mbps • ATM: 155.52Mbps Absolute Maximum Ratings • Supply voltage • Storage temperature • Input voltage difference: | VD–VDN | • TTL input voltage • Output current (Continuous) (Surge) Recommended Operating Conditions • Supply voltage • Termination voltage (for RCK/RDATA) • Termination voltage (for SDE) • Termination resistance (for RCK/RDATA) • Termination resistance (for SDE) • Operating temperature VCC – VEE Tstg Vdif VinT IO –0.3 to +5.0 –65 to +150 0 to 2.5 –0.5 to 5.5 0 to 50 0 to 100 VCC – VEE 3.069 to 3.465 VCC – VT1 1.8 to 2.2 VT2 VEE RT1 46 to 56 RT2 460 to 560 Ta –40 to +85 V °C V V mA mA V V V Ω Ω °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E97Y13-PS CXB1575AQ NC VEEP2 LPFB LPFA VCCP CAP1B CAP1 VEER1 30 29 28 27 26 25 24 23 22 21 VEEP1 VEEP1 Block Diagram and Pad Configuration 20 VEER2 REXT 31 LKDT 32 19 DN Up phase/ charge frequency pump Down detector VCO VEEG 33 18 D 17 VCCR 1 Mux. 0 VCCG 34 16 DOWN D EXCK 35 15 HYS D-FF CK Reset CKSEL 36 14 VEER3 13 CAP2 SQLCH 37 peak hold SDC 38 peak hold 12 CAP3 11 NC SDE 39 –2– RDATAN RDATA VEEE1 VEEG 6 7 8 9 10 VCCE2 5 RCK 4 RCKN 3 VEEE2 2 VCCG 1 VCCE1 SDEN 40 CXB1575AQ Pin Description Typical pin voltage (V) Pin No. Symbol DC AC 1 2 VCCE1 Equivalent circuit Description Positive supply for RDATA/RDATAN output circuits. 3.3 VCCE1 1.6 to 2.4 RDATAN 2 3 3 1.6 to 2.4 RDATA Retimed data outputs. VEEE1 4 VEEE1 0 Ground for RDATA/RDATAN output circuits. 5, 33 VEEG 0 Ground for digital circuits. 6, 34 VCCG 3.3 7 VEEE2 0 Positive supply for digital circuits. Ground for RCK/RCKN outputs circuits. VCCE2 8 1.6 to 2.4 RCKN 8 9 1.6 to 2.4 RCK Recovered clock outputs. 9 VEEE2 10 VCCE2 11 NC Positive supply for RCK/RCKN output circuits. 3.3 No connect 10p 12 CAP3 12 13 VCCR 2 Connect a peak hold capacitor for signal detector. Typically 470pF. 13 CAP2 2 5µA 5µA VEER –3– CXB1575AQ Typical pin voltage (V) Pin No. Symbol DC AC 14 VEER3 Equivalent circuit Description 0 Ground for signal detector. VCCR Connect to VEER3 through an external resistor to determine signal detect hysteresis width (∆P). When connect to VEER3 directly; ∆P ≈ 6dB (Typ.) When connected 8.2kΩ to VEER3; ∆P ≈ 3dB (Typ.) Bias Generator 15 HYS 0.2 15 VEER3 VCCR 16 DOWN 3 Connect to VCCR through an external resistor to decrease signal detect level (SDL). When open, SDL sets to 18mVp-p. (single-ended) 16 VEER3 17 VCCR 18 D Positive supply for signal detector. 3.3 VCCR Serial data stream inputs. 19 DN 22 18 19 23 2.2 22 CAP1 23 CAP1B 2.2 Connect an external capacitor, which determines low cut-off frequency for DC feedback loop. Typically 0.22µF. 20 VEER2 0 Ground for post amplifier. 21 VEER1 0 Ground for post amplifier. Both VEER1 and VEER2 must be grounded. 24 VCCP 3.3 Positive supply for PLL circuits. VEER1 VEER2 –4– CXB1575AQ Typical pin voltage (V) Pin No. Symbol DC AC Equivalent circuit Description VCCP 25 LPFA 3.1 25 26 26 LPFB Connect an external loop filter capacitor. Typically 0.68µF (155.52Mbps). 3.1 VEEP1 VEEP2 27 VEEP2 28 NC 29, 30 VEEP1 Ground for PLL circuits. 0 No connect Ground for PLL circuits. Both VEEP1 and VEEP2 must be grounded. 0 VCCP 31 REXT Bias Generator 0.4 31 Connect to VEEP1 through an external resistor to determine VCO frequency. Typically 1.8kΩ. VEEP2 VCCG 32 0.2 to 3.1 LKDT 32 Lock detector (TTL). Driven low, while synchronization is lost. VEEG VCCG 35 EXCK 1.3 External clock input (ECL). For testing only. Normally, left open. 35 VEEG –5– CXB1575AQ Typical pin voltage (V) Pin No. Symbol DC AC Equivalent circuit Description VCCG 36 CKSEL 3.3 Clock selector (TTL). When low, EXCK is active instead of VCO output. Normally, left open. 36 VEEG VCCG 37 SQLCH 3.3 TTL input. When Low, RCK and RDATA are fixed Low, in case of data loss. When high, RCK outputs VCO free-run frequency, in case of data loss. 37 VEEG VCCG 38 SDC 0.2 to 3.1 Signal detect output (TTL). Driven low, while input serial data is lost. 38 VEEG 39 SDE VCCG 1.6 to 2.4 39 40 SDEN 40 1.6 to 2.4 VEEG –6– Signal detect outputs (ECL). SDE is driven low, while input serial data is lost. CXB1575AQ Electrical Characteristics • DC characteristics Item (VCC = +3.069 to +3.465V, VEE = GND, Ta = –40°C to +85°C) Symbol Conditions Min. All outputs open Typ. Max. Unit 70 100 mA Supply current ICC TTL input High voltage VIHT 2 3.465 V TTL input Low voltage VILT 0 0.8 V 51Ω to VCC – 2V VCC – 1.1 VCC – 0.83 V 51Ω to VCC – 2V VCC – 1.88 VCC – 1.55 V RDATA/RCK output High voltage RDATA/RCK output Low voltage VOH1∗1 VOL1∗1 510Ω to VEE VCC – 1.1 VCC – 0.83 V SDE output Low voltage VOH2∗1 VOL2∗1 510Ω to VEE VCC – 1.88 VCC – 1.55 V TTL output High voltage VOHT IOH = –0.2mA 2.4 TTL output Low voltage VOLT IOL = 2.1mA Maximum input voltage amplitude Vmax 1600 D/DB input resistance Rin 2250 SDE output High voltage V 0.5 V mV 3000 3750 Ω ∗1 Ta = 0°C to +85°C • AC characteristics Item (VCC = +3.069 to +3.465V, VEE = GND, Ta = –40°C to +85°C) Symbol Post amplifier gain GL Signal detect hysteresis width ∆P Signal detect response assert time∗1 Tas Signal detect response deassert time∗1 Tdas Jitter generation∗2 RJ PLL band width∗2 FC Conditions Min. Max. 50 HYS = VEER3, Rd = 22kΩ Unit dB 3 8 dB 0 100 µs 2.3 100 µs with 12kHz high pass filter 0.008 Jitter peaking∗2 Jitter tolerance∗2, ∗3 Typ. UIrms 90 130 kHz 0.06 0.1 dB f = 10Hz 1.5 16 f = 30Hz 1.5 16 f = 300Hz 1.5 16 f = 6.5kHz 1.5 4 f = 65kHz 0.15 0.5 UIp-p PLL capture range∗2 PLL pull in time∗2 Tp DRSEL = High 42 RCK, RDATA output rise time Tr 51Ω to VCC – 2V, 20% to 80% 600 1000 ps RCK, RDATA output fall time Tf 51Ω to VCC – 2V, 20% to 80% 600 1000 ps DRSEL = High 155.40 155.52 155.60 Mbps ∗1 D = 155.52Mbps, PN23-1 pattern, 100mVp-p single-ended, Rd = OPEN, CAP2/3 = 470pF ∗2 D = 155.52Mbps, PN23-1 pattern, 20mVp-p single-ended, Cp = 0.68µF ∗3 Bit Error Rate Threshold: 1E – 10 –7– ms CXB1575AQ 0.22µF DC Electrical Characteristics Measurement Circuit 0.68µF 28 30 29 27 26 25 23 24 22 21 20 1.8kΩ 31 32 19 Up phase/ charge frequency pump Down detector VCO 33 18 17 1 Mux. 0 34 16 D 35 15 D-FF CK Reset 36 14 peak hold 38 40 Vcc 3.3V 4 5 6 7 9 8 51Ω 3 51Ω 2 2V 51Ω 1 VEE 12 11 51Ω 510Ω peak hold 39 2V 510Ω 470pF 13 37 –8– 10 470pF CXB1575AQ AC Electrical Characteristics Measurement Circuit –1.3V 33µF 0.1µF 0.68µF 28 30 29 27 26 0.22µF 25 23 24 22 21 20 1.8kΩ 31 32 18 0.01µF 17 1 Mux. 0 34 0.01µF 50Ω 50Ω phase/ charge frequency pump Down detector VCO 33 0.1µF 19 Up 16 D 35 15 D-FF CK Reset 36 14 13 37 510Ω peak hold 38 peak hold 39 470pF 12 470pF 11 40 510Ω 2 5 4 3 6 7 8 9 Z = 50Ω 1 Z = 50Ω 0.1µF 10 +2V Data Clock Data Clock 50Ω 50Ω 50Ω 1MΩ 1MΩ 1MΩ 1MΩ Z = 50Ω Z = 50Ω Z = 50Ω 0.1µF Jitter Source Oscilloscope Oscilloscope –9– Bit Error Rate Counter Pulse Pattern Generator CXB1575AQ 0.68µF 28 30 29 27 26 Analog Supply2 Application Circuit 0.1µF 25 0.22µF 23 24 22 21 20 31 32 VCO 33 0.01µF 91Ω 91Ω 18 17 1 Mux. 0 34 130Ω 19 Up phase/ charge frequency pump Down detector 1.8kΩ 130Ω 0.01µF 16 D-FF D 35 0.1µF 15 CK Reset 36 Analog Supply1 14 470pF 13 37 peak hold 38 peak hold 470pF 12 11 39 40 1 2 3 4 5 6 8 9 10 Digital Supply 0.1µF Digital Supply Analog Supply1 Analog Supply2 40µH 33µF 7 3.3V 33µF Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 10 – CXB1575AQ Notes on Operation 1. Limiting amplifier block The limiting amplifier block is equipped with the auto-offset canceler circuit. When external capacitors C1 and C2 are connected as shown in Fig. 1, the DC bias is set automatically in this block. External capacitor C1 and IC internal resistor R1 determine the low input cut-off frequency f2 as shown in Fig. 2. Similarly, external capacitor C2 and IC internal resistor R2 determine the high cut-off frequency f1 for DC bias feedback. Since peaking characteristics may occur in the low frequency area of the amplifier gain characteristics depending on the f1/f2 combination, set the C1 and C2 so as to avoid the occurrence of peaking characteristics. The target values of R1 and R2 and the typical values of C1 and C2 are as indicated below. When a single-ended input is used, provide AC grounding by connecting Pin 19 to a capacitor which has the same capacitance as capacitor C1. R1 (internal): 3kΩ R2 (internal): 10kΩ f2: 5.3kHz f1: 7.2kHz C1 (external): 0.01µF D C2 (external): 0.22µF 18 C1 To IC interior 19 C1 R1 R1 R2 23 R2 Fig. 1 Feedback frequency response Gain C2 22 f1 f2 Frequency Fig. 2 – 11 – Amplifier frequency response CXB1575AQ 2. Alarm block This block provides a signal interruption alarm output used for open fibre control (OFC). Signal detect threshold level and hysteresis width are both user adjustable. Signal detect threshold default level is 18mVp-p (single-ended). An external resister Rd between DOWN and VCCR decrease it. Typical characteristics of Rd vs. threshold level is shown in fig. 7, 8. Hysteresis width can be also decreased by an external resister RH. Typical characteristics of RH vs. ∆P is shown in fig. 9. Timing chart of signal detect function is shown in fig. 5. SD response assert/deassert time are decided by peak hold capacitor CR and CS.Their typical value is 470pF for 155Mbps operation. VDAS → Deassert level VAS → Assert level SD output High level Rd 17 Rh 16 Cs 15 14 Cs : 470pF CR : 470pF CR 13 Low level VAS VDAS Small 12 Large 3dB 3dB Alarm setting input level Hysteresis Input electrical signal amplitude Fig. 4 Fig. 3 Hysteresis width Data input (D) Alarm setting level Alarm output (SDEN) Alarm output (SDE, SDC) Assert time Deassert time Fig. 5. Timing Chart – 12 – CXB1575AQ 3. Clock and Data recovery block Clock recovery is reallized by fully integrated phase locked loop (PLL), which needs no external reference clock. PLL accepts scrambled NRZ data with 50% mark density. Two external components Re and Cp are required. Their recommended values are shown in fig. 6. Cp 30 29 27 26 25 31 Re :1.8k Ω Cp :0.68µF (155.52Mbps) Re Fig. 6 Re is a resistor which decides VCO center frequency. To reduce the temperature dependence of the VCO oscillation frequency, Re should have a small temperature coefficient. In addition, Re should place as near as IC terminal to obtain good jitter performance. Cp is a loop filter capacitance. Since loop damping factor ξ is function of √Cp, Cp is also important to have a small temperature coefficient. Damping factor ξ is given as 20,000 × √Cp (@ρ = 1/2) ∗3 Recommended Cp value gives a ξ of 10, and jitter peaking of under 0.1dB is specified. ∗3 ρ: data transition density 4. Others Pay attention to handling this IC because its electrostatic discharge strength is weak. – 13 – CXB1575AQ Assert/Deassert level [mVp-p, single-ended] 20 15 10 5 0 Vast (mVp-p) Vdast (mVp-p) 1 10 100 15 10 5 0 1000 Vast (mVp-p) Vdast (mVp-p) 1 10 Rd [kΩ] 100 1000 Rd [kΩ] VCC = 3.3V, Ta = 27°C D = 155.52Mbps, PRBS23-1 20mVp-p, single-ended Rh = 0Ω VCC = 3.3V, Ta = 27°C D = 155.52Mbps, PRBS23-1 20mVp-p, single-ended Rh = 8.2kΩ Fig. 7. Rd vs. SD assert/deassert level (Rh = 0Ω) Fig. 8. Rd vs. SD assert/deassert level (Rh = 8.2kΩ) 20 Assert/Deassert level [mVp-p, single-ended] Assert/Deassert level [mVp-p, single-ended] 20 15 10 5 Vast (mVp-p) Vdast (mVp-p) 0 0 5 10 15 Rh [kΩ] 20 25 VCC = 3.3V, Ta = 27°C D = 155.52Mbps, PRBS23-1 20mVp-p, single-ended Rd = ∞Ω Fig. 9. Rh vs. SD assert/deassert level (Rd = ∞) – 14 – CXB1575AQ 400mV/div Example of Representative Characteristics 1.0ns/div VCC = 3.3V, Ta = 27°C D = 155.52Mbps, PRBS23-1 20mVp-p, single-ended Fig. 10. RCK/RDATA output waveform 100 0 OC-3 Mask –5 Amplitude [UI] Jitter amplitude [dB] 5 –10 –15 –20 10 1 OC-3 Template –25 –30 102 103 104 105 106 107 0.1 102 Modulation frequency [Hz] 103 104 105 Modulation frequency [Hz] VCC = 3.3V, Ta = 27°C D = 155.52Mbps, PRBS23-1 20mVp-p, single-ended Threshold = 1E – 10 VCC = 3.3V, Ta = 27°C D = 155.52Mbps, PRBS23-1 20mVp-p, single-ended Fig. 11. Jitter transfer function Fig. 12. Jitter tolerance – 15 – 106 CXB1575AQ Package Outline Unit: mm 40PIN QFP (PLASTIC) + 0.35 1.5 – 0.15 + 0.1 0.127 – 0.05 9.0 ± 0.4 + 0.4 7.0 – 0.1 0.1 21 30 20 31 A 11 40 1 + 0.15 0.3 – 0.1 0.65 10 0.24 M 0° to 10° 0.5 ± 0.2 (8.0) + 0.15 0.1 – 0.1 DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE QFP-40P-L01 LEAD TREATMENT SOLDER / PALLADIUM PLATING EIAJ CODE QFP040-P-0707 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.2g JEDEC CODE – 16 –