CXD1177Q 8-bit 40MSPS YC 2-channel D/A Converter Description The CXD1177Q is an 8-bit high-speed D/A converter for video band use. It has an input/output equivalent to 2 channels of Y and C. It is suitable for use of digital TV, graphic display, and others. Features • Resolution 8-bit • Maximum conversion speed 40MSPS • YC 2-channel input/output • Differential linearity error ±0.3 LSB • Low power consumption 160 mW (200 Ω load at 2 Vp-p output) • Single 5 V power supply • Low glitch noise • Stand-by function Structure Silicon gate CMOS IC 32 pin QFP (Plastic) Absolute Maximum Ratings (Ta=25 °C) • Supply voltage AVDD, DVDD 7 V • Input voltage (All pins) VIN VDD +0.5 to VSS –0.5 V • Output current (Every each channel) IOUT 0 to 15 mA • Storage temperature Tstg –55 to +150 °C Recommended Operating Conditions • Supply voltage AVDD, AVSS 4.75 to 5.25 V DVDD, DVSS 4.75 to 5.25 V • Reference input voltage VREF 2.0 V • Clock pulse width TPW1, TPW0 11.2 ns (min.) to 1.1 µs (max.) • Operating temperature Topr –40 to +85 °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E90602F01 CXD1177Q Block Diagram (LSB) Y0 Y1 2 Y2 3 Y3 4 DECODER 6 Y6 7 (MSB) Y7 8 (LSB) C0 9 31 AVDD 28 YO LATCHES 6MSB'S CURRENT CELLS Y4 5 Y5 32 DVDD 2LSB'S CURRENT CELLS 1 29 YO 19 YCK DECODER CLOCK GENERATOR 23 AVSS 2LSB'S CURRENT CELLS C1 10 21 DVSS C2 11 C3 12 DECODER LATCHES 6MSB'S CURRENT CELLS C4 13 C5 14 C6 15 26 CO 27 CO 20 CCK DECODER 30 VG CLOCK GENERATOR (MSB) C7 16 25 VREF CURRENT CELLS (FOR FULL SCALE) BLK 17 CE 18 24 IREF BIAS VOLTAGE GENERATOR IREF AVss VB DVss CCK YCK CE BLK Pin Configuration 22 VB 24 23 22 21 20 19 18 17 14 C5 YO 28 13 C4 YO 29 12 C3 VG 30 11 C2 AVDD 31 10 C1 DVDD 32 9 C0 1 2 3 4 5 6 7 8 Y7 27 Y6 CO Y5 15 C6 Y4 26 Y3 CO Y2 16 C7 Y1 25 Y0 VREF —2— CXD1177Q Pin Description and I/O Pins Equivalent Circuit Pin No. Symbol 1 to 8 Y0 to Y7 I/O Equivalent circuit Description DVDD Digital input Y0 (LSB) to Y7 (MSB) C0 (LSB) to C7(MSB) 1 I to 16 9 to 16 C0 to C7 DVSS DVDD 17 BLK I Blanking input. This is synchronized with the clock input signal for each channel. No signal at “H” (Output 0 V). Output condition at “L”. 17 DVSS DVDD DVDD 22 VB O Connect a capacitor of about 0.1 µF. 22 DVSS DVDD 19 YCK I Clock input. 19 20 20 CCK 21 23 DVSS AVSS DVSS — — Digital ground Analog ground DVDD 18 CE I Chip enable input. This is not synchronized with the clock input signal. No signal (Output 0 V) at “H” and minimizes power consumption. 18 DVSS —3— CXD1177Q Pin No. 24 Symbol IREF I/O Equivalent circuit O AVDD Description AVDD Connect a resistance 16 times “RIR” that of output resistance value “ROUT”. 24 AVDD 25 VREF I AVSS 25 VG O 31 AVDD — 27 CO Set full-scale output value. AVSS Connect a capacitor of about 0.1 µF. 30 AVSS 30 AVDD Analog power supply AVDD Current output. Voltage output can be obtained by connecting a resistance. 27 29 29 YO AVSS O 26 AVDD CO Inverted current output. Normally dropped to analog ground. 26 28 28 YO 32 DVDD AVSS — Digital power supply —4— CXD1177Q (FCLK=40 MHz, AVDD=DVDD=5 V, ROUT=200 Ω, VREF=2.0 V, Ta=25 °C) Electrical Characteristics Resolution Item Symbol n Conversion speed FCLK Integral non-linearity error Differential non-linearity error Output full-scale voltage Output full-scale ratio ∗1 Output full-scale current Output offset voltage Glitch energy Crosstalk EL ED VFS FSR IFS VOS GE CT IDD ISTB RIN CI VIH VIL IIH IIL ts th tPD tE tD Supply current Analog input resistance Input capacitance Digital input voltage Digital input current Setup time Hold time Propagation delay time CE enable time ∗2 CE disable time ∗2 ∗1 ∗2 Measurement conditions AVDD=DVDD=4.75 to 5.25 V Ta=–40 to +85 °C Endpoint When “00000000” data input ROUT=75 Ω When 1 kHz sine wave input When 14.3 MHz CE=L color bar data input CE=H VREF Min. Max. Unit bit 0.5 40 MSPS –2.5 –0.3 1.8 0 2.5 0.3 2.2 3.0 15 1 LSB LSB V % mA mV pV•s dB 30 57 32 1.2 1 AVDD=DVDD=4.75 to 5.25 V Ta=–20 to +75 °C AVDD=DVDD=4.75 to 5.25 V Ta=–20 to +75 °C ROUT=75 Ω ROUT=75 Ω 2.4 0.8 –5 10 2 2 CE=H→L CE=L→H Electrical Characteristics Measurement Circuit Measurement Circuit +5.25V AVDD, DVDD A CXD1177Q V AVSS, DVSS —5— –1 mA MΩ pF V 5 µA 4 4 ns ns ns ms ms 5 10 Full-scale voltage for each channel Full-scale voltage average value for each channels When the external capacitors for the VG pins are 0.1 µF. } 2.0 1.5 10 9 Full-scale output ratio = Analog Input Resistance Digital Input Current Typ. 8 × 100 (%) CXD1177Q Maximum Conversion Velocity Measurement Circuit Y0 to Y7 1 to 8 8bit COUNTER with LATCH YO 29 200 OSCILLOSCOPE AVss C0 to C7 9 to 16 CO 27 200 AVss 17 BLK 0.1µ 18 CE AVDD 22 VB VG 30 0.1µ 19 YCK CLK 40MHZ SQUARE WAVE Setup Time Hold Time Glitch Energy 1k VREF 25 DVss IREF 24 3.3k 20 CCK AVss } Measurement Circuit Y0 to Y7 1 to 8 8bit COUNTER with LATCH C0 to C7 9 to 16 YO 29 75 OSCILLOSCOPE AVss CO 27 75 AVss 17 BLK DELAY CONTROLLER 0.1µ 18 CE AVDD 22 VB VG 30 0.1µ CLK 1MHZ SQUARE WAVE 19 YCK DELAY CONTROLLER 1k VREF 25 DVss IREF 24 1.2k 20 CCK AVss Crosstalk Measurement Circuit ALL “1” Y0 to Y7 1 to 8 DIGITAL WAVEFORM GENERATOR YO 29 200 AVss C0 to C7 9 to 16 CO 27 200 AVss 17 BLK 0.1µ 18 CE AVDD 22 VB VG 30 0.1µ VREF 25 DVss CLK 40MHZ SQUARE WAVE 19 YCK 1k IREF 24 3.3k 20 CCK AVss —6— SPECTRUM ANALYZER CXD1177Q DC Characteristics Measurement Circuit Y0 to Y7 1 to 8 YO 29 C0 to C7 9 to 16 CO 27 200 CONTROLLER DVM AVss 200 AVss 17 BLK 0.1µ 18 CE AVDD 22 VB VG 30 VREF 25 DVss 19 YCK CLK 40MHZ SQUARE WAVE 0.1µ 1k IREF 24 3.3k 20 CCK AVss Propagation Delay Time Measurement Circuit FREQUENCY DEMULTIPLIER Y0 to Y7 1 to 8 YO 29 C0 to C7 9 to 16 CO 27 200 OSCILLOSCOPE AVss 200 AVss 17 BLK 0.1µ 18 CE AVDD 22 VB VG 30 0.1µ VREF 25 DVss CLK 10MHZ SQUARE WAVE 19 YCK 20 CCK 1k IREF 24 3.3k AVss —7— CXD1177Q Description of Operation tPW1 Timing Chart tPW0 2V CLK AA AA AA AAA AA AAAAAAA ts th ts th ts th DATA tPD D/A OUT 100% 50% tPD tPD 0% I/O Chart (When full-scale output voltage at 2.00 V) Input code Output voltage MSB LSB 1 1 1 1 1 1 1 1 : 1 0 0 0 0 0 0 0 : 0 0 0 0 0 0 0 0 2.0 V 1.0 V 0V Y OUT Application Circuit 200 C OUT 200 AVss AVDD 0.1µF DVDD 32 (LSB) AVss 31 30 AVDD AVss 29 28 27 26 1k 25 AVss 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 3.3k AVss 0.1µF DVss Y IN CLOCK (MSB) 9 10 11 12 13 14 15 (LSB) DVss 16 (MSB) C IN Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. —8— CXD1177Q Notes on Operation • How to select the output resistance The CXD1177Q is a D/A converter of the current output type. To obtain the output voltage connect the resistance to the current output pins Y0, C0. For specifications we have; Output full scale voltage VFS = 1.8 to 2.2 [V] Output full scale current IFS = less than 15 [mA] Calculate the output resistance value from the relation of VFS = IFS × ROUT. Also, 16 times resistance of the output resistance is connected to reference current pin IREF. In some cases, however, this turns out to be a value that does not actually exist. In such a case a value close to it can be used as a substitute. Here please note that VFS becomes VFS = VREF × 16ROUT/RIR. ROUT is the resistance connected to the current output pins YO and CO while RIR is connected to IREF. Increasing the resistance value can curb power consumption. On the other hand glitch energy and data settling time will inversely increase. Set the most suitable value according to the desired application. • Phase relation between data and clock To obtain the expected performance as a D/A converter, it is necessary to set properly the phase relation between data and clock applied from the exterior. Be sure to satisfy the provisions of the setup time (tS) and hold time (tH) as stipulated in the Electrical Characteristics. • Power supply and grand To reduce noise effects separate analog and digital systems in the device periphery. For the power supply pins, both digital and analog, bypass respective grounds by using a ceramic capacitor of about 0.1 µF, as close as possible to the pin. • Latch up AVDD and DVDD have to be common at the PCB power supply source. This is to prevent latch up due to voltage difference between AVDD and DVDD pins when power supply is turned ON. • YO and IO pins The YO and IO pins are the inverted current output pins described in the Pin Description. The sums shown below become the constant value for any input data. a) The sum of the currents output form YO and YO b) The sum of the currents output form CO and CO However, the performances such as the linearity error of the inverted current output pin output current is not guaranteed. —9— CXD1177Q Latch Up Prevention The CXD1177Q is a CMOS IC which requires latch up precautions. Latch up is mainly generated by the lag in the voltage rising time of AVDD (Pin 31) and DVDD (Pin 32), when power supply is ON. 1. Correct usage a. When analog and digital supplies are from different sources DVDD AVDD 31 32 AVDD +5V +5V DVDD C C DIGITAL IC CXD1177Q AVSS DVSS 23 21 AVSS DVSS b. When analog and digital supplies are from a common source (i) DVDD 31 32 AVDD DVDD C +5V C DIGITAL IC CXD1177Q AVSS 23 DVSS 21 AVSS DVSS (ii) DVDD 31 32 AVDD DVDD +5V C AVSS C CXD1177Q AVSS DVSS 23 21 DVSS —10— DIGITAL IC CXD1177Q 2. Example when latch up easily occurs a. When analog and digital supplies are from different sources DVDD AVDD 31 32 AVDD +5V +5V C DVDD DIGITAL IC CXD1177Q AVSS DVSS 23 AVSS 21 DVSS b. When analog and digital supplies are from common source (i) DVDD AVDD 31 32 AVDD DVDD +5V DIGITAL IC CXD1177Q C AVSS DVSS 23 21 AVSS DVSS (ii) DVDD AVDD 31 32 AVDD DVDD +5V DIGITAL IC CXD1177Q AVSS AVSS DVSS 23 21 DVSS —11— CXD1177Q Example of Representative Characteristics AVDD=DVDD=5.0V VREF=2.0V RIR ≈ 16ROUT Ta=25°C 2.0 Glitch energy GE [pV•s] Output full scale voltage VFS [V] 200 1.0 AVDD=DVDD=5.0V ROUT=200Ω RIR=3.3kΩ Ta=25°C 0 1.0 100 2.0 100 200 Output resistance ROUT [Ω] Output resistance vs. Glitch energy 60 2.0 Crosstalk CT [dB] Output full scale voltage VFS [V] Reference voltage VREF [V] Reference voltage vs. Output full scale voltage 1.9 AVDD=DVDD= 5.0V VREF=2.0V ROUT=200Ω RIR=3.3kΩ 50 40 AVDD=DVDD= 5.0V VREF=2.0V ROUT=200 Ω RIR=3.3k Ω Ta=25°C 0 –25 0 25 50 75 100k 1M 10M Output frequency FO [Hz] Output frequency vs. Crosstalk Ambient temperature Ta [°C] Ambient temperature vs. Output full scale voltage —12— CXD1177Q Package Outline Unit : mm 32PIN QFP (PLASTIC) 9.0 ± 0.2 24 0.1 + 0.35 1.5 – 0.15 + 0.3 7.0 – 0.1 17 16 32 9 (8.0) 25 1 + 0.2 0.1 – 0.1 0.8 + 0.15 0.3 – 0.1 0.24 M + 0.1 0.127 – 0.05 0° to 10° PACKAGE MATERIAL EPOXY RESIN SONY CODE QFP-32P-L01 LEAD TREATMENT SOLDER PLATING EIAJ CODE QFP032-P-0707 LEAD MATERIAL 42 ALLOY PACKAGE MASS 0.2g JEDEC CODE —13— 0.50 8