INTERSIL HI2307

®
D
NEW
August 1997
Features
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Description
• Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . Triple 10-Bit
• Maximum Conversion Speed . . . . . . . . . . . . . . . 50MHz
• RGB 3-Channel Input/Output
• Differential Linearity Error . . . . . . . . . . . . . . . ±0.5 LSB
• Low Power Consumption . . . . . . . . . . . . .300mW (Max)
• Single Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . +5V
• Low Glitch
HI2307
NS
Triple 10-Bit, 50 MSPS,
3-Channel D/A Converter
The HI2307 is a triple 10-bit, high-speed, CMOS D/A
converter designed for video band use. It has three separate, 10-bit, pixel inputs, one each for red, green, and blue
video data. A single 5.0V power supply and pixel clock input
is all that is required to make the device operational. A bias
voltage generator is internal. Each channel clock input can
be controlled individually, or connected together as one. The
HI2307 also has BLANK video control signal.
Ordering Information
• Direct Replacement for Sony CXD2307
PART
NUMBER
Applications
• Digital TV
TEMP.
RANGE ( oC)
HI2307JCQ
• Graphics Display
-20 to 75
PACKAGE
PKG. NO.
64 Ld MQFP
Q64.10x10-S
• High Resolution Color Graphics
• Video Reconstruction
• Instrumentation
• Image Processing
• I/Q Modulation
Pinout
R1
RO (LSB)
DVDD
AVDD
AVDD
BO
BO
AVDD
AVDD
GO
GO
AVDD
AVDD
RO
RO
AVSS
HI2307
(MQFP)
TOP VIEW
6463 62 61 60 59 58 57 56 55 54 53 52 51 50 49
R2
R3
R4
R5
R6
R7
R8
R9
G0 (LSB)
G1
G2
G3
G4
G5
G6
G7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VGB
ROB
VGG
ROG
VGR
ROR
VRB
VRG
VRR
IRB
IRG
IRR
AVSS
VB
DVSS
BCK
G8
G9
B0 (LSB)
B1
B2
B3
B4
B5
B6
B7
B8
B9
BLK
CE
RCK
GCK
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
10-1
File Number
4117.1
HI2307
Functional Block Diagram
62 DVDD
(LSB) R0
63
R1
64
R2
1
R3
2
R4
3
60 AVDD
4 LSBs
CURRENT
CELLS
61 AVDD
44 VGR
50 RO
6 MSBs
CURRENT
CELLS
LATCHES
R5
4
R6
5
R7
6
R8
7
R9
8
(LSB) G0
9
G1
10
G2
11
G3
12
G4
13
G5
14
G6
15
G7
16
G8
17
G9
18
(LSB) B0
19
B1
20
B2
21
B3
22
B4
23
B5
24
B6
25
B7
26
B8
27
B9
28
CURRENT
CELLS FOR
FULL SCALE
BLK
29
BIAS VOLTAGE
GENERATOR
CE
30
51 RO
31 RCK
DECODER
CLOCK
GENERATOR
43 ROR
-
DECODER
CURRENT
CELLS FOR
FULL SCALE
+
40 VRR
37 IRR
56 AVDD
4 LSBs
CURRENT
CELLS
57 AVDD
46 VGG
54 GO
6 MSBs
CURRENT
CELLS
LATCHES
55 GO
32 GCK
DECODER
CLOCK
GENERATOR
DECODER
CURRENT
CELLS FOR
FULL SCALE
45 ROG
-
+
41 VRG
38 IRG
52 AVDD
4 LSBs
CURRENT
CELLS
54 AVDD
48 VGB
58 BO
6 MSBs
CURRENT
CELLS
DECODER
59 BO
LATCHES
33 BCK
CLOCK
GENERATOR
DECODER
47 ROB
-
+
42 VRB
39 IRB
35 VB
36 AVSS
49 AVSS
34 DVSS
10-2
HI2307
Pin Descriptions
NUMBER
SYMBOL
63 to 8
R0 to R9
9 to 18
G0 to G9
19 to 28
B0 to B9
EQUIVALENT CIRCUIT
DESCRIPTION
Digital Input.
DVDD
63
28
DVSS
29
BLK
Blanking pin. No signal for High (0V output).
Output generated for Low.
DVDD
29
DVSS
35
VB
DVDD
Connect to DVSS with a capacitor of approximately
0.1µF.
DVDD
+
-
35
DVSS
31
RCK
32
GCK
33
BCK
Clock pins. All input pins are TTL compatible.
DVDD
31
32
33
DVSS
34
DVSS
Digital GND.
36, 49
AVSS
Analog GND.
30
CE
Chip Enable pin. No signal for High (0V output) to
minimize power consumption.
DVDD
30
DVSS
52, 53, 56,
57, 60, 61
AVDD
Analog VDD .
10-3
HI2307
Pin Descriptions
NUMBER
SYMBOL
43
45
47
ROR
ROG
ROB
44
46
48
VGR
VGG
VGB
37
38
39
IRR
IRG
IRB
40
41
42
VRR
VRG
VRB
(Continued)
EQUIVALENT CIRCUIT
DESCRIPTION
Connect to VGR, VGG, and VGB with the control
method of output amplitude. See Application
Circuit.
AVDD
43
Connect a capacitor of approximately 0.1µF.
45
47
Connect to AVSS with a resistance of 3.3kΩ.
AVSS
AVDD
Set output fullscale value (2.0V).
44
46
48
AVSS
AVDD
37
38
39
AVSS
+
-
AVDD
40
41
42
AVSS
50
RO
54
GO
58
BO
50
51
RO
54
55
GO
58
59
BO
Current output pins. Output can be retrieved by
connecting a resistance of 200Ω to AVSS.
AVDD
Reverse current output pins. Normally connect to
AVSS.
AVSS
AVDD
51
55
59
AVSS
62
DVDD
Digital VDD .
10-4
HI2307
Absolute Maximum Ratings TA = 25oC
Thermal Information
Supply Voltage, V DD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD to VSS
Output Current (for Each Channel), lOUT . . . . . . . . . . . . . 0 to 15mA
Thermal Resistance (Typical, Note 7)
Operating Conditions
Supply Voltage
AVDD , AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.75V to 5.25V
DV DD , DVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.75V to 5.25V
Reference Input Voltage, VREF . . . . . . . . . . . . . . . . . . .0.5V to 2.0V
Clock Pulse Width
tPW1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ns (Min)
tPW0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ns (Min)
Temperature Range, TOPR . . . . . . . . . . . . . . . . . . . . -20oC to 75oC
θJA (oC/W)
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
93
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
TA = 25oC, fCLK = 50MHz, VDD = 5V, ROUT = 200Ω, VREF = 2.0V
PARAMETER
MIN
TYP
MAX
UNITS
n
-
10
-
Bit
fMAX
50
-
-
MHz
Linearity Error
EL
-2.0
-
2.0
LSB
Differential Linearity Error
ED
-0.5
-
0.5
LSB
Output Full Scale Voltage
VFS
1.8
1.9
2.0
V
Output Full Scale Ratio (Note 8)
FSR
0
1.5
3
%
Output Full Scale Current
IFS
-
9.5
10
mA
Output Offset Voltage
VOS
-
-
1
mV
Supply Current
IDD
-
55
60
mA
High Level
IIH
-
-
5
µA
Low Level
IIL
-5
-
-
µA
VOC
1.8
1.9
2.0
V
Setup Time
tS
-
5
7
ns
Hold Time
tH
-
1
3
ns
Propagation Delay Time
tPD
-
10
-
ns
Glitch Energy
GE
-
100
-
pV-s
Cross Talk
CT
-
54
-
dB
Resolution
Maximum Conversion Speed
Digital Input
Current
Precision Guaranteed Output Voltage
Range
SYMBOL
TEST CONDITIONS
For the Equal Gain
For 10MHz Sinewave Output
NOTE:
Full scale voltage of channel
2. Output Full Scale Ratio = ------------------------------------------------------------------------------------------------------------------------------- ( – 1 ) x 100(%) .
Average of the full scale voltage of the channels
10-5
HI2307
I/O Correspondence Table
(Output Full Scale Voltage: 2.0V)
INPUT CODE
MSB
OUTPUT VOLTAGE
LSB
1 1 1 1 1 1 1 1 1 1
2.0V
••
•
1 0 0 0 0 0 0 0 0 0
1.0V
••
•
0 0 0 0 0 0 0 0 0 0
0V
Timing Diagram
tPW1
tPW0
CLK
tS
tH
tS tH
tS tH
DATA
tPD
100%
50%
D/ A OUT
tPD
tPD
0%
Test Circuits
10
10-BIT
COUNTER
WITH
LATCH
10
10
R0 TO R9
63 TO 8
RO
52
G0 TO G9
9 TO 18
RO
53
200
AVSS
B0 TO B9
9 TO 28
OSCILLOSCOPE
GO
56
GO
57
200
HI2307
0.1µ
AVSS
29 BLK
BO
60
30 CE
BO
61
200
AVDD
35 VB
DVSS
CLK
50MHz
SQUARE
WAVE
31 RCK
32 GCK
33 BCK
VGR TO VGB
44, 46, 48
ROR TO ROB
43, 45, 47
VRR TO VRB
40 TO 42
IRR TO IRB
37 TO 39
0.1µ
2V
3.3K
FIGURE 1. MAXIMUM CONVERSION RATE
10-6
AVSS
HI2307
Test Circuits
(Continued)
10
10-BIT
COUNTER
WITH
LATCH
10
10
R0 TO R9
63 TO 8
RO
52
G0 TO G9
9 TO 18
RO
53
200
AVSS
B0 TO B9
9 TO 28
OSCILLOSCOPE
GO
56
GO
57
BO
60
BO
61
200
AVSS
29 BLK
DELAY
CONTROLLER
0.1µ
HI2307
30 CE
200
AVDD
35 VB
DVSS
CLK
50MHz
SQUARE
WAVE
DELAY
CONTROLLER
31 RCK
32 GCK
33 BCK
VGR TO VGB
44, 46, 48
ROR TO ROB
43, 45, 47
VRR TO VRB
40 TO 42
IRR TO IRB
37 TO 39
AVSS
0.1µ
2V
3.3K
FIGURE 2. SETUP HOLD TIME AND GLITCH ENERGY TEST CIRCUIT
10-7
HI2307
Test Circuits
(Continued)
ALL “1” 10
DIGITAL
WAVEFORM
GENERATOR
10
10
R0 TO R9
63 TO 8
RO
50
G0 TO G9
9 TO 18
RO
51
200
AVSS
B0 TO B9
9 TO 28
GO
54
GO
55
BO
58
BO
59
OSCILLOSCOPE
200
AVSS
29 BLK
HI2307
30 CE
0.1µ
200
AVDD
35 VB
DVSS
31 RCK
CLK
50MHz
SQUARE
WAVE
VGR TO VGB
44, 46, 48
ROR TO ROB
43, 45, 47
32 GCK
VRR TO VRB
40 TO 42
33 BCK
IRR TO IRB
37 TO 39
AVSS
0.1µ
2V
3.3K
FIGURE 3. CROSS TALK TEST CIRCUIT
Typical Performance Curves
CURRENT CONSUMPTION (mA)
CROSS TALK (dB)
80
70
60
50
VDD = 5.0V
TA = 25 oC
40
100K
1M
10M
60
VDD = 5.0V
fCLK = 50MHz
VREF = 2.0V
50
-20
0
25
50
AMBIENT TEMPERATURE (oC)
OUTPUT FREQUENCY (Hz)
FIGURE 4. OUTPUT FREQUENCY vs CROSS TALK
FIGURE 5. CURRENT CONSUMPTION vs AMBIENT
TEMPERATURE
10-8
75
HI2307
Typical Performance Curves
(Continued)
FULLSCALE VOLTAGE (V)
1.9
VDD = 5.0V
VREF = 2.0V
1.8
-20
0
25
50
75
AMBIENT TEMPERATURE (oC)
FIGURE 6. FULL SCALE VOLTAGE vs AMBIENT TEMPERATURE
Application Circuits
3.3kΩ
1kΩ
0.1µF
0.1µF
48
ROUT
GOUT
200Ω
200Ω
NC
NC
47 46
45
NC NC
44
43
42 41
38
37
36 35
34
CLOCK INPUT
33
32
50
31
51
30
52
29
53
28
54
27
55
26
25
HI2307
57
200Ω
39
49
56
BOUT
40
24
58
23
59
22
60
21
61
20
62
19
63
18
64
17
1
2
3
4
5
6
7
8
9
R CHANNEL INPUT
10
11
12
13 14
G CHANNEL INPUT
FIGURE 7. GAIN EQUAL
10-9
15
16
B CHANNEL INPUT
DVDD
AVDD
DVSS
AVSS
HI2307
Application Circuits
(Continued)
3.3kΩ
1kΩ
0.1µF
48
ROUT
GOUT
200Ω
200Ω
NC
NC
47 46
45
NC NC
44
43
42 41
39
38
37
36 35
34
CLOCK INPUT
33
32
50
31
51
30
52
29
53
28
54
27
55
26
25
HI2307
57
200Ω
40
49
56
BOUT
0.1µF
24
58
23
59
22
60
21
61
20
62
19
63
18
64
17
1
2
3
4
5
6
7
8
9
R CHANNEL INPUT
10
11
12
13 14
G CHANNEL INPUT
FIGURE 8. GAIN INDEPENDENTLY
10-10
15
16
B CHANNEL INPUT
DVDD
AVDD
DVSS
AVSS