CXD2308Q 10-bit 50MSPS RGB 3-channel D/A Converter Description The CXD2308Q is a 10-bit high-speed D/A converter for video band, featuring RGB 3-channel I/O. This is ideal for use in high-definition TVs and high-resolution displays. Features • Resolution 10-bit • Maximum conversion speed 50MSPS • RGB 3-channel I/O • Differential linearity error ±0.5LSB • Low power consumption 500 mW (Typ.) • Single +5 V power supply • Low glitch • Stand-by function Structure Silicon gate CMOS IC 64 pin QFP (Plastic) Absolute Maximum Ratings (Ta=25 °C) • Supply voltage AVDD, DVDD 7 V • Input voltage (All pins) VIN VDD+0.5 to VSS–0.5 V • Output current (for each channel) IOUT 0 to 30 mA • Storage temperature Tstg –55 to +150 °C Recommended Operating Conditions • Supply voltage AVDD, AVSS 4.75 to 5.25 V DVDD, DVSS 4.75 to 5.25 V • Reference input voltage VREF 1.8 to 2.0 V • Clock pulse width TPW1,TPW0 9 ns (min.) to 1.1 µs (max.) • Operating temperature Topr –20 to +75 °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E92929D01 CXD2308Q Block Diagram 64 DVDD (LSB) R0 1 R1 2 R2 3 4LSB'S CURRENT CELLS 5 R5 6 6MSB'S CURRENT CELLS 33 RCK CLOCK GENERATOR R7 8 DECODER CURRENT CELLS (FOR FULL SCALE) 4LSB'S CURRENT CELLS (LSB) G0 11 G1 12 6MSB'S CURRENT CELLS G3 14 G4 15 CLOCK GENERATOR DECODER CURRENT CELLS (FOR FULL SCALE) 4LSB'S CURRENT CELLS (LSB) B0 21 B1 22 47 ROG 40 IRG 54 AVDD 55 AVDD 50 VGB B2 23 6MSB'S CURRENT CELLS B3 24 B4 25 LATCHES DECODER B6 27 60 BO 61 BO 35 BCK CLOCK GENERATOR B7 28 BLK 31 57 GO 43 VRG (MSB)G9 20 (MSB) B9 30 56 GO 34 GCK G7 18 B8 29 58 AVDD 59 AVDD LATCHES DECODER G6 17 B5 26 39 IRR 48 VGG G2 13 G8 19 45 ROR 42 VRR (MSB) R9 10 G5 16 52 RO 53 RO LATCHES DECODER R6 7 R8 9 63 AVDD 46 VGR R3 4 R4 62 AVDD 49 ROB 44 VRB DECODER CURRENT CELLS (FOR FULL SCALE) 41 IRB BIAS VOLTAGE GENERATOR 37 VB 38 AVSS CE 32 51 AVSS 36 DVSS —2— RCK GCK DVss BCK VB AVss IRR IRB IRG VRR VRG VRB ROR ROG VGR VGG ROB AVss Pin Configuration VGB CXD2308Q 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RO 52 32 CE RO 53 31 BLK AVDD 54 30 B9 (MSB) AVDD 55 29 B8 GO 56 28 B7 GO 57 27 B6 AVDD 58 26 B5 AVDD 59 25 B4 BO 60 24 B3 BO 61 23 B2 G7 G8 G6 G5 G4 G3 G2 9 10 11 12 13 14 15 16 17 18 19 G1 8 (LSB) G0 7 R8 6 (MSB) R9 5 R7 4 R6 3 R5 2 R4 1 R3 20 G9 (MSB) R2 DVDD 64 R1 22 B1 21 B0 (LSB) (LSB) R0 AVDD 62 AVDD 63 Pin Description and Equivalent Circuit Pin No. Symbol 1 to 10 11 to 20 21 to 30 R0 to R9 G0 to G9 B0 to B9 31 BLK I/O Equivalent circuit DVDD 1 I to 35 32 CE 33 34 35 RCK GCK BCK 36 DVSS DVSS Description Digital input. R0 (LSB) to R9 (MSB) G0 (LSB) to G9 (MSB) B0 (LSB) to B9 (MSB) Blanking input. This is synchronized with the clock input signal for each channel. No signal for High (0 V output). Output generated for Low. Chip enable input. This is not synchronized with the clock input signal. No signal at for High (0 V output) to minimize power consumption. Clock inputs. Digital ground. — —3— CXD2308Q Pin No. Symbol I/O Equivalent circuit Description DVDD DVDD 37 Connect to DVSS with a capacitor of approximately 0.1 µF. VB 37 DVSS 38, 51 AVSS — Analog grounds. AVDD 45 45 47 49 ROR ROG ROB Connect to VGR, VGG, and VGB with the control method of output amplitude. See Application Circuit. 47 O 49 AVSS AVDD 46 48 50 VGR VGG VGB 46 I Connect a capacitor of approximately 0.1 µF. 48 50 AVSS AVDD 39 40 41 IRR IRG IRB Reference current output. Connect to AVSS with a resistance of 1.2 kΩ. 39 O 40 41 AVSS AVDD 42 43 44 VRR VRG VRB I Reference voltage input. Set output full-scale value (2.0 V). 42 43 44 AVSS —4— CXD2308Q Pin No. Symbol 52 RO I/O Equivalent circuit Description AVDD Current output. Output can be retrieved by connecting a resistance of 75 Ω to AVSS. 52 56 GO 56 60 60 BO 53 RO AVSS AVDD 53 57 Reverse current output. Normally connected to AVSS. 57 GO 61 61 54, 55, 58, 59, 62, 63 64 BO AVSS AVDD — Analog VDD. DVDD Digital VDD. Description of Operation Timing Chart tPW1 tPW0 1.5V CLK AA AA AAA AA AAAAAAAAA ts th DATA ts th ts th tPD D/A OUT 100% 50% tPD tPD 0% I/O Correspondence Table (output full-scale voltage: 2.00 V) Input code MSB LSB 1 1 1 1 1 1 1 1 1 1 : 1 0 0 0 0 0 0 0 0 0 : 0 0 0 0 0 0 0 0 0 0 Output voltage 2.0 V 1.0 V 0V —5— CXD2308Q (FCLK=50 MHz, AVDD=DVDD=5 V, ROUT=75 Ω, VREF=2.0 V, Ta=25 °C) Electrical Characteristics Resolution Item Symbol n Conversion speed FCLK AVDD=DVDD=4.75 to 5.25 V Ta=–20 to +75 °C Integral non-linearity error Differential non-linearity error Precision guaranteed output voltage range Output full-scale voltage EL ED Endpoint VOC VFS Output full-scale ratio ∗1 FSR Output full-scale current Output offset voltage Glitch energy Crosstalk IFS VOS GE CT IDD ISTB Supply current Analog input resistance RIN Input capacitance Output capacitance CI CO VIH VIL IIH IIL ts th tPD tE tD Digital input voltage Digital input current Setup time Hold time Propagation delay time CE enable time ∗2 CE disable time ∗2 ∗1 ∗2 Min. Measurement conditions For the same gain (See the Application Circuit) Typ. 10 Max. Unit bit 0.5 50 MSPS –2.0 –0.5 2.0 0.5 LSB LSB 1.8 1.9 2.0 V 1.8 1.9 2.0 V 0 1.5 3 % 27 30 1 mA mV pV•s dB When data “0000000000” input 50 54 100 When 1 kHz sine wave input CE= “L” CE= “H” VGR, VGG, VGB, VRR, VRG, VRB 110 1 1 MΩ 9 50 RO, GO, BO AVDD=DVDD=4.75 to 5.25 V Ta=–20 to +75 °C AVDD=DVDD=4.75 to 5.25 V Ta=–20 to +75 °C 2.15 0.85 –5 10 1 1 Full-scale voltage for each channel Full-scale voltage average value for each channel When the external capacitors for the VGR, VGG and VGB pins are 0.1 µF. Output full-scale ratio = Electrical Characteristics Measurement Circuit Analog Input Resistance Measurement Circuit Digital Input Current –1 } AVDD, DVDD A CXD2308Q V AVSS, DVSS —6— V µA 2 2 ns ns ns ms ms × 100 (%) +5.25V pF pF 5 7 3 CE=H→L CE=L→H mA CXD2308Q Maximum Conversion Speed Measurement Circuit R0 to R9 1 to 10 G0 to G9 11 to 20 B0 to B9 21 to 30 10 bit COUNTER WITH LATCH RO 52 CLK 50MHZ SQUARE WAVE Setup Time Hold Time Glitch Energy } AVss GO 56 75 GO 57 31 BLK BO 60 32 CE BO 61 37 VB 0.1µ DVss 75 RO 53 VGR to VGB 46, 48, 50 ROR to ROB 45, 47, 49 33 RCK VRR to VRB 34 GCK 42 to 44 35 BCK IRR to IRB 39 to 41 AVss 75 AVss AVDD 0.1µ 2V 1.2k Measurement Circuit R0 to R9 1 to 10 G0 to G9 11 to 20 B0 to B9 21 to 30 10 bit COUNTER WITH LATCH DELAY CONTROLLER RO 52 75 RO 53 AVss GO 56 75 GO 57 31 BLK BO 60 32 CE BO 61 VGR to VGB 0.1µ 46, 48, 50 ROR to ROB DVss 45, 47, 49 33 RCK VRR to VRB 34 GCK 42 to 44 35 BCK IRR to IRB 39 to 41 DELAY CONTROLLER OSCILLO SCOPE AVss 75 AVss 37 VB CLK 50MHZ SQUARE WAVE OSCILLO SCOPE AVDD 0.1µ 2V 1.2k Cross Talk Measurement Circuit ALL “1” DIGITAL WAVEFORM GENERATOR R0 to R9 1 to 10 G0 to G9 11 to 20 B0 to B9 21 to 30 AVss GO 56 75 GO 57 BO 60 32 CE BO 61 VGR to VGB 0.1µ 46, 48, 50 ROR to ROB DVss 45, 47, 49 33 RCK VRR to VRB 34 GCK 42 to 44 35 BCK IRR to IRB 39 to 41 —7— 75 RO 53 31 BLK 37 VB CLK 50MHZ SQUARE WAVE RO 52 AVss 75 AVss AVDD 0.1µ 2V 1.2k SPECTRUM ANALYZER CXD2308Q DC Characteristics Measurement Circuit R0 to R9 1 to 10 G0 to G9 11 to 20 B0 to B9 21 to 30 CONTROLLER RO 52 AVss GO 56 31 BLK BO 60 32 CE BO 61 VGR to VGB 0.1µ 46, 48, 50 DVss ROR to ROB 45, 47, 49 33 RCK VRR to VRB 34 GCK 42 to 44 35 BCK IRR to IRB 39 to 41 DVM 75 GO 57 37 VB CLK 50MHZ SQUARE WAVE 75 RO 53 AVss 75 AVss AVDD 0.1µ 2V 1.2k Propagation Delay Time Measurement Circuit FREQUENCY DEMULTIPLIER R0 to R9 1 to 10 G0 to G9 11 to 20 B0 to B9 21 to 30 AVss GO 56 75 GO 57 BO 60 32 CE BO 61 VGR to VGB 0.1µ 46, 48, 50 DVss ROR to ROB 45, 47, 49 33 RCK VRR to VRB 34 GCK 42 to 44 35 BCK IRR to IRB 39 to 41 —8— 75 RO 53 31 BLK 37 VB CLK 50MHZ SQUARE WAVE RO 52 AVss 75 AVss AVDD 0.1µ 2V 1.2k OSCILLO SCOPE CXD2308Q Application Circuit 1.2kΩ 0.1µF (Gain equal) 1kΩ Clock input 0.1µF NC NC NC NC 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ROUT 32 52 75Ω GOUT 75Ω BOUT 75Ω 53 31 54 30 55 29 56 28 57 27 58 26 59 25 60 24 61 23 62 22 63 21 64 20 1 2 3 4 5 6 8 7 B channel input AVDD DVDD AVSS DVSS 9 10 11 12 13 14 15 16 17 18 19 R channel input G channel input (Gain independently) 0.1µF 1.2kΩ 1kΩ 0.1µF 0.1µF Clock input 0.1µF 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ROUT 32 52 75Ω GOUT 75Ω BOUT 75Ω 53 31 54 30 55 29 56 28 57 27 58 26 59 25 60 24 61 23 62 22 63 21 64 20 1 2 3 4 5 6 7 8 B channel input AVDD DVDD AVSS DVSS 9 10 11 12 13 14 15 16 17 18 19 R channel input G channel input Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. —9— CXD2308Q Notes on Operation • How to select the output resistance The CXD2308Q is a D/A converter of the current output type. To obtain the output voltage connect the resistance to RO, GO and BO pin. For specifications we have: Output full scale voltage VFS=1.8 to 2.0 [V] Output full scale current IFS=less than 30 [mA] Calculate the output resistance value from the relation of VFS=IFS × ROUT. Also, 16 times resistance of the output resistance is connected to reference current pin IRR, IRG and IRB. In some cases, however, this turns out to be a value that does not actually exist. In such a case a value close to it can be used as a substitute. Here please note that VFS becomes VFS=VREF × 16ROUT/RIR. VREF is the voltage set at the VRR, VRG and VRB pins and ROUT is the resistance connected to RO, GO and BO while RIR is connected to IRR, IRG and IRB. Increasing the resistance value can curb power consumption. On the other hand glitch energy and data settling time will inversely increase. Set the most suitable value according to the desired application. • Phase relation between data and clock To obtain the expected performance as a D/A converter, it is necessary to set properly the phase relation between data and clock applied from the exterior. Be sure to satisfy the provisions of the setup time (tS) and hold time (tH) as stipulated in the Electrical Characteristics. • Power supply and ground To reduce noise effects separate analog and digital systems in the device periphery. For power supply pins, both digital and analog, bypass respective grounds by using a ceramic capacitor of about 0.1 µF, as close as possible to the pin. • Latch up Analog and digital power supply have to be common at the PCB power supply source. This is to prevent latch up due to voltage difference between AVDD and DVDD pins when power supply is turned ON. • RO, GO and BO pins The RO, GO and BO pins are the inverted current output pins described in the Pin Description. The sums shown below become the constant value for any input data. a) The sum of the currents output from RO and RO b) The sum of the currents output from GO and GO c) The sum of the currents output from BO and BO However, the performances such as the linearity error of the inverted current output pin output current is not guaranteed. • Output full-scale voltage For the applications using the RGB signal, the color balance may be broken up when the no-adjusted output full-scale voltage of RO, GO and BO are used. —10— CXD2308Q Latch Up Prevention The CXD2308Q is a CMOS IC which requires latch up precautions. Latch up is mainly generated by the lag in the voltage rising time of AVDD and DVDD, when power supply is ON. 1. Correct usage a. When analog and digital supplies are from different sources DVDD AVDD AVDD +5V +5V DVDD C C DIGITAL IC CXD2308Q AVSS DVSS AVSS DVSS b. When analog and digital supplies are from a common source (i) DVDD AVDD DVDD C +5V C DIGITAL IC CXD2308Q AVSS DVSS AVSS DVSS (ii) DVDD AVDD DVDD C +5V DIGITAL IC CXD2308Q C AVSS DVSS AVSS DVSS —11— CXD2308Q 2. Example when latch up easily occurs a. When analog and digital supplies are from different sources DVDD AVDD AVDD +5V +5V C DVDD C CXD2308Q AVSS DIGITAL IC DVSS AVSS DVSS b. When analog and digital supplies are from common source (i) DVDD AVDD AVDD DVDD +5V C CXD2308Q C AVSS DIGITAL IC DVSS AVSS DVSS (ii) DVDD AVDD AVDD DVDD +5V C CXD2308Q AVSS DVSS AVSS DVSS —12— DIGITAL IC CXD2308Q Example of Representative Characteristics 80 Crosstalk CT [dB] 70 60 50 AVDD=DVDD=5.0V FCLK=50MSPS VREF=2.0V Ta=25°C ROUT=75Ω RIR=1.2kΩ 40 100k 1M 10M Output frequency FO [HZ] Output frequency vs. Crosstalk 110 Full-scale voltage VFS [V] Current consumption IDD [mA] 1.9 AVDD=DVDD=5.0V FCLK=50MSPS VREF=2.0V ROUT=75 Ω RIR=1.2k Ω 100 AVDD=DVDD=5.0V FCLK=50MSPS VREF=2.0V ROUT=75Ω RIR=1.2kΩ 1.8 –20 0 25 50 75 –20 Ambient temperature Ta [°C] Ambient temperature vs. Current consumption 0 25 50 70 Ambient temperature Ta [°C] Ambient temperature vs. Full-scale voltage —13— CXD2308Q Package Outline Unit : mm 64PIN QFP(PLASTIC) 23.9 ± 0.4 + 0.4 20.0 – 0.1 + 0.1 0.15 – 0.05 0.15 64 20 1 16.3 32 + 0.4 14.0 – 0.1 52 17.9 ± 0.4 33 + 0.2 0.1 – 0.05 19 + 0.35 2.75 – 0.15 + 0.15 0.4 – 0.1 1.0 0.2 M 0° to10° 0.8 ± 0.2 51 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE QFP-64P-L01 LEAD TREATMENT SOLDER/PALLADIUM PLATING EIAJ CODE QFP064-P-1420 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 1.5g JEDEC CODE —14—