DATA SHEET MOS INTEGRATED CIRCUIT µPD75328 4-BIT SINGLE-CHIP MICROCOMPUTER DESCRIPTION The µPD75328 is one of the 75X Series 4-bit single-chip microcomputer, and has a data processing capability comparable to that of an 8-bit microcomputer. In addition to high-speed operation with 0.95 µ s minimum instruction execution time for the CPU, the µPD75328 can also process data in 1-, 4-, and 8-bit units. Therefore, as a 4-bit single-chip microcomputer chip having a built-in LCD controller/driver and A/D converter, its data processing capability is the highest in its class in the world. The µPD75P328 with one-time PROM, which is replaced with the internal mask ROM for a µPD75328, is applicable for evaluating systems under development, or for small-scale production of developed systems. "Detailed functions are described in the following user's manual. Be sure to read it for designing." " µPD75328 User's Manual: IEM-5045" FEATURES • Capable of high-speed operation and variable instruction execution time to power save • 0.95 µ s, 1.91 µ s, 15.3 µ s (Main system clock: operating at 4.19 MHz) • 122 µs (Subsystem clock: operating at 32.768 kHz) • 75X architecture comparable to that for an 8-bit microcomputer is employed • Built-in programmable LCD controller/driver • Built-in 8-bit resolution A/D converter: 6 channels • Clock operation at reduced power dissipation: 5 µA TYP. (operating at 3 V) • Timer function: 3 channels • Interrupt functions especially enhanced for applications, such as remote control receiver • Pull-up resistors can be provided for 35 I/O lines • Built-in NEC standard serial bus interface (SBI) APPLICATIONS Cameras, blood pressure gauges, airconditioners, etc. ORDERING INFORMATION Part Number Package Quality Grade µPD75328GC-xxx-3B9 80-pin plastic QFP (■ ■ 14mm) Standard Remarks: xxx is ROM code number. Please refer to “Quality Grade on NEC Semiconductor Devices” (Document Number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. The information in this document is subject to change without notice. Document No. IC-2763B (O. D. No. IC-7628D) Date Published November 1993 P Printed in Japan The mark ★ shows the major revised points. NEC Corporation 1990 µPD75328 FUNCTIONAL OUTLINE (1/2) Item Function Number of Basic Instructions 41 Instruction Execution Time 0.95, 1.91, and 15.3 µs, (Main system clock: operating at 4.19 MHz) 122 µs (Subsystem clock: operating at 32.768 kHz) Internal Memory ROM RAM General-Purpose Registers I/O Line Including the pins which also serve as LCD drive pins. Excluding the pins which is specifically provided for driving LCD. 8064 × 8-bit 512 × 4-bit 4-bit manipulation: 8×4 banks, 8-bit manipulation: 4×4 banks 8 44 CMOS Input pins CMOS input/output pins Internal pull-up resistor specification by software is possible (except P00). 8 CMOS output pins Also serve as segment pins 8 N-ch open-drain input/output Withstand voltage: 10V Internal pull-up resistor specification by mask option is possible. 20 LCD Controller/ Driver • LCD drive output pins • Segment output pins: 20 (CMOS output pins: 8) • Common output pins: 4 • Capable of driving up to 20 × 4 segments • Display output mode: Static, 1/2, 1/3, 1/4 duty A/D Converter 8-bit resolution x 6 channels (successive approximation type) • Operating voltage VDD = 3.5 to 6.0 V • A/D conversion speed 40.1 µs (operating at 4.19 MHz) 8-bit timer/event counter • Clock source: 4 steps • Event count is possible Timer MHz) 3 chs 8-bit basic interval timer • Reference time generation (1.95, 7.82, 31.3, 250 ms: operating at 4.19 • Can be used as watchdog timer Clock timer • 0.5 second interval generation • Count clock source slectable (4.19 MHz/32.768 kHz) • Clock advance mode (3.9 ms time interval generation) • Buzzer output (2 kHz) Serial Interface 2 Clock • • • synchronized serial interface Internal NEC standard serial bus interface (SBI mode) 3-line serial I/O mode ... MSB/LSB first selectable 2-line serial I/O mode Bit Sequential Buffer Special bit manipulation memory: 16 bits Clock Output (PCL) Φ, 524, 262, 65.5 kHz (Main system clock: 4.19 MHz) Buzzer Output (BUZ) 2 kHz (with main system clock or subsystem clock operated) Vector Interrupt • External: 3 • Internal: 3 Test Input • External: 1 • Internal: 1 µPD75328 FUNCTIONAL OUTLINE (2/2) Item Function System Clock Generator • Main system clock generation ceramic/crystal oscillator; 4.194304 MHz • Subsystem clock generation crysal oscillator: 32.768 kHz Standby STOP/HALT mode Operating Temperature Range –40 to +85°C Operating Supply Voltage VDD = 2.7 to 6.0 V Package 80-pin plastic QFP (■ ■ 14 mm) 3 µPD75328 CONTENTS 1. PIN CONFIGURATION (TOP VIEW) ........................................................................................ 6 2. BLOCK DIAGRAM ......................................................................................................................7 3. PIN FUNCTIONS ........................................................................................................................8 3.1 PORT PINS ........................................................................................................................................ 8 3.2 NON PORT PINS ............................................................................................................................ 10 3.3 PIN INPUT/OUTPUT CIRCUITS ................................................................................................... 12 3.4 RECOMMENDED PROCESSING OF UNUSED PINS .................................................................. 14 3.5 SELECTION OF MASK OPTION ................................................................................................... 15 3.6 NOTES ON USING THE P00/INT4, AND RESET PINS .............................................................. 15 4. MEMORY CONFIGURATION ................................................................................................. 16 5. PERIPHERAL HARDWARE FUNCTIONS ............................................................................... 18 5.1 PORTS ............................................................................................................................................. 18 5.2 CLOCK GENERATOR CIRCUIT ..................................................................................................... 19 5.3 CLOCK OUTPUT CIRCUIT ............................................................................................................. 20 5.4 BASIC INTERVAL TIMER .............................................................................................................. 21 5.5 WATCH TIMER ............................................................................................................................... 22 5.6 TIMER/EVENT COUNTER ............................................................................................................. 22 5.7 SERIAL INTERFACE ....................................................................................................................... 24 5.8 LCD CONTROLLER/DRIVER ......................................................................................................... 26 5.9 A/D CONVERTER .......................................................................................................................... 28 5.10 BIT SEQUENTIAL BUFFER .... 16 BITS ....................................................................................... 29 6. INTERRUPT FUNCTIONS ......................................................................................................... 29 7. STANDBY FUNCTIONS ............................................................................................................ 31 8. RESET FUNCTION .................................................................................................................... 32 9. INSTRUCTION SET ................................................................................................................. 34 10. ELECTRICAL SPECIFICATIONS ............................................................................................. 40 11. CHARACTERISTIC CURVES (REFERENCE VALUE) ............................................................ 53 12. PACKAGE DRAWINGS ........................................................................................................... 59 13. RECOMMENDED SOLDERING CONDITIONS ...................................................................... 61 4 µPD75328 APPENDIX A. COMPARISON OF FEATURES BETWEEN µPD75328 AND µPD75308 ........ 62 APPENDIX B. DEVELOPMENT TOOLS ...................................................................................... 63 APPENDIX C. RELATED DOCUMENTS ..................................................................................... 64 5 µPD75328 AN3 AN4 AN5 AV SS AV REF V DD XT1 XT2 NC X1 X2 RESET P60/KR0 P61/KR1 P62/KR2 P63/KR3 P70/KR4 P71/KR5 S31/BP7 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 60 AN2 S30/BP6 2 59 AN1 S29/BP5 3 58 AN0 S28/BP4 4 57 P83 S27/BP3 5 56 P82 S26/BP2 6 55 P81 S25/BP1 7 54 P80 S24/BP0 8 53 P33 S23 9 52 P32 S22 10 51 P31/SYNC S21 11 50 P30/LCDCL S20 12 49 P23/BUZ S19 13 48 P22/PCL S18 14 47 P21 S17 15 46 P20/PTO0 S16 16 45 P13/TI0 S15 17 44 P12/INT2 S14 18 43 P11/INT1 S13 19 42 P10/INT0 S12 20 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P03/SI/SB1 P02/SO/SB0 P01/SCK P00/INT4 P53 P52 P51 V SS P50 P43 P42 P41 P40 VLC2 VLC1 BIAS VLC0 COM3 COM2 COM0 µ PD75328GC– ××× –3B9 6 P72/KR6 P73/KR7 PIN CONFIGURATION (Top View) COM1 1. P00-P03 : Port 0 AV SS : Analog Ground P10-P13 : Port 1 AN0-AN5 : Analog Input 0-5 P20-P23 : Port 2 S12-S31 : Segment Output 12-31 P30-P33 : Port 3 COM0-COM3 : Command Output 0-3 P40-P43 : Port 4 VLC0-VLC2 : LCD Power Supply 0-2 P50-P53 : Port 5 BIAS : LCD Power Supply Bias Control P60-P63 : Port 6 LCDCL : LCD Clock P70-P73 : Port 7 SYNC : LCD Synchronization P80-P83 : Port 8 TI0 : Timer Input 0 BP0-BP7 : Bit Port PTO0 : Programmable Timer Output 0 KR0-KR7 : Key Return BUZ : Buzzer Clock : Programmable Clock SCK : Serial Clock PCL SI : Serial Input INT0,INT1,INT4 : External Vectored Interrupt 0,1,4 SO : Serial Output INT2 : External Test Input 2 SB0,SB1 : Serial Bus 0,1 X1,X2 : Main System Clock Oscillation 1,2 RESET : Reset Input XT1,XT2 : Subsystem Clock Oscillation 1,2 AVREF : Analog Reference NC : No Connection A/D CONVERTER BASIC INTERVAL TIMER INTBT PROGRAM COUNTER (13) SP (8) PTO0/P20 ALU BANK INTT0 WATCH TIMER BUZ/P23 GENERAL REG. INTW SI/SB1/P03 P00-P03 PORT 1 4 P10-P13 PORT 2 4 P20-P23 PORT 3 4 P30-P33 PORT 4 4 P40-P43 PORT 5 4 P50-P53 PORT 6 4 P60-P63 PORT 7 4 P70-P73 PORT 8 4 P80-P83 12 S12-S23 8 S24/BP0 -S31/BP7 4 COM0-COM3 f LCD CLOCKED SERIAL INTERFACE SO/SB0/P02 SCK/P01 4 CY TIMER/EVENT COUNTER #0 TI0/P13 PORT 0 PROGRAM MEMORY (ROM) 8064 × 8 BITS DECODE AND CONTROL DATA MEMORY (RAM) 512 × 4 BITS INTCSI BLOCK DIAGRAM AV REF AV SS 2. AN0–AN5 6 INT0/P10 INT1/P11 INTERRUPT CONTROL INT2/P12 8 f X /2 BIT SEQ. BUFFER (16) CLOCK OUTPUT CONTROL 7 PCL/P22 CLOCK DIVIDER LCD CONTROLLER /DRIVER N SYSTEM CLOCK GENERATOR SUB MAIN XT1 XT2 X1 X2 3 STAND BY CONTROL CPU CLOCK V DD V SS RESET V LC0 -V LC2 f LCD BIAS LCDCL/P30 SYNC/P31 µPD75328 INT4/P00 KR0/P60 –KR7/P73 µPD75328 3. PIN FUNCTIONS 3.1 PORT PINS (1/2) Also Served Pin Name Input/Output As P00 Input INT4 P01 Input/ Output SCK P02 Input/ Output SO/SB0 P03 Input/ Output SO/SB1 P10 INT0 P11 Input INT1 P12 INT2 P13 TI0 P20 PTO0 P21 Input/ Output P22 P23 — PCL Function 8-Bit I/O B 4-bit input port (PORT0) Pull-up resistors can be specified in 3-bit units for the P01 to P03 pins by software. F -A X Input F -B M -C With noise elimination function 4-bit input port (PORT1) Internal pull-up resistors can be specified in 4-bit units by software. X Input B -C 4-bit input/output port (PORT2) Internal pull-up resistors can be specified in 4-bit units by software. X Input E-B Programmable 4-bit input/output port (PORT3) This port can be specified for input/ output in bit units. Internal pull-up resistors can be specified in 4-bit units by software. X Input E-B BUZ P30* 2 P31* 2 LCDCL Input/ Output P32*2 P33*2 SYNC — — 2 P40-43* Input/ Output — N-ch open-drain 4-bit input/output port (PORT4) Internal pull-up resistors can be specified in bit units. (mask option) Resistive voltage is 10 V in the opendrain mode. — N-ch open-drain 4-bit input/output port (PORT5) Internal pull-up resistors can be specified in bit units. (mask option) Resistive voltage is 10 V in the opendrain mode. ● P50-53*2 Input/ Output *1: Circles indicate Schmitt trigger inputs. 2: Can directly drive LED. 8 When Reset Input/ Output Circuit TYPE*1 High level (with internal pull-up resistor) or high impedance High level (with internal pull-up resistor) or high impedance M M µPD75328 3.1 PORT PINS (2/2) Pin Name Input/Output Also Served As P60 P61 P62 KR0 KR1 Input/ Output KR2 P63 KR3 P70 KR4 P71 P72 KR5 Input/ Output KR6 Function 8-Bit I/O Programmable 4-bit input/output port (PORT6) This port can be specified for input/ output in bit units. Internal pull-up resistors can be specified in 4-bit units by software. When Reset Input/ Output Circuit TYPE*1 Input F -A Input F -A ● 4-bit input/output port (PORT7) Internal pull-up resistors can be specified in 4-bit units by software. KR7 P73 P80 P81 P82 Input/ Output — 4-bit input/output port (PORT8) Internal pull-up resistors can be specified in 4-bit units by software. X Input E-B 1-bit output port (BIT PORT) Shared with a segment output pin. X *2 G-C P83 BP0 S24 BP1 S25 Output BP2 S26 BP3 S27 BP4 S28 BP5 S29 Output BP6 S30 BP7 S31 *1: Circles indicate schmidt trigger inputs. 2: For BP0-7, V LC1 indicated below are selected as the input source. However, the output level is changed depending on BP0-7 and the VLC1 external circuits. Example: Since BP0-7 are connected to each other within the µPD75328 as shown in the diagram below, the output level of BP0-7 depends on the sizes of R1, R 2 and R 3. µ PD75328 V DD R2 BP 0 V LC1 ON BP 1 R1 ON R3 9 µPD75328 3.2 NON PORT PINS Also Served Pin Name Input/Output As Functon When Reset Input/ Output Circuit TYPE*1 Input P13 Timer/event counter external event pulse Input Input B -C PTO0 Output P20 Timer/event counter output Input E-B PCL Input/ Output P22 Clock output Input E-B BUZ Input/ Output P23 Fixed frequency output (for buzzer or for trimming the system clock) Input E-B SCK Input/ Output P01 Serial clock input/output Input F -A SO/SB0 Input/ Output P02 Serial data output Serial bus input/output Input F -B SI/SB1 Input/ Output P03 Serial data input Serial bus input/output Input M -C Input P00 Edge detection vector interrupt input (both rising and falling edge detection are effective) Input B Input B -C TI0 INT4 P10 INT0 INT1 INT2 Input Clock synchronous P11 Edge detection vector interrupt input (detection edge can be selected) P12 Edge detection testable input (rising edge detection) Asynchronous Input B -C Input Asynchronous KR0-KR3 Input/ Output P60-P63 Parallel falling edge detection testable input/output Input F -A KR4-KR7 Input/ Output P70-P73 Parallel falling edge detection testable input/output Input F -A S12-S23 Output — Segment signal output *4 G-A S24-S31 Output BP0-7 Segment signal output *4 G-C COM0COM3 Output — Common signal output *4 G-B VLC0-VLC2 — — LCD drive power Step-down resistor network (mask option) — — BIAS Output — External expanded driver for disconnect output *5 LCDCL*3 Input/ Output P30 Externally expanded driver for clock output Input E-B SYNC*3 Input/ Output P31 Externally expanded driver sync clock output Input E-B AN0-AN5 Input — 6-bit analog input for A/D converter Input Y AVREF Input — A/D converter reference voltage input Input Z AVSS — — GND potential for A/D converter reference voltage input. Connected to VSS. — — 10 µPD75328 (cont'd) When Reset Input/ Output Circuit TYPE*1 — To connect the crystal/ceramic oscillator to the main system clock generator. When inputting the external clock, input the external clock to pin X1, and the reverse phase of the external clock to pin X2. — — — — Pin Name Input/Output Also Served As X1, X2 — Function XT1, XT2 — — To connect the crystal oscillator to the subsystem clock generator. When the external clock is used, pin XT1 inputs the external clock. In this case, pin XT2 must be left open. Pin XT1 can be used as a 1-bit input pin. RESET Input — System reset input — B NC *2 — — No connection — — VDD — — Positive power supply — — VSS — — GND — — *1: Circles indicate schmidt trigger inputs. 2: When sharing the printed circut board with the µ PD75P328, the NC pin must be connected to VDD . 3: These pins are provided for future system expansion. At present, these pins are used only as pins P30 and P31. 4: For these display output, VLCX indicated below are selected as the input source. S12 to S31: VLC1, COM0 to COM2: VLC2, COM3: VLC0 However, display output level varies depending on the particular display output and VLCX external circuit. Example: Since BP0-7 are connected to each other within the µ PD75328 as shown in the diagram below, the output level of BP0-7 depends on the size of R1, R 2 and R 3. µ PD75328 V DD R2 BP 0 V LC1 ON BP 1 R1 ON R3 5: Step-down resistor network provided : Low level Step-down resistor network not provided : High impedance 11 µPD75328 3.3 PIN INPUT/OUTPUT CIRCUITS The following shows a simplified input/output circuit diagram for each pin of the µPD75328. TYPE D (for TYPE E– B, F– A) TYPE A (for TYPE E–B) VDD VDD data P–ch P–ch OUT IN output disable N–ch Input buffer of CMOS standard N–ch Push–pull output that can be set in a output high–impedance state (both P–ch and N–ch are off) TYPE E–B TYPE B VDD P.U.R. P.U.R. enable P–ch IN data IN/OUT Type D output disable Type A Schmitt trigger input with hysteresis characteristics TYPE B–C P.U.R. : Pull–Up Resistor TYPE F–A VDD P.U.R. VDD P.U.R. enable P.U.R. P–ch P.U.R. enable P–ch data IN/OUT Type D IN output disable Type B P.U.R. : Pull–Up Resistor Schmitt trigger input with hysteresis characteristics 12 P.U.R. : Pull–Up Resistor µPD75328 TYPE F–B TYPE G– C VDD V DD P.U.R. P-ch P.U.R. enable output disable (P) P–ch V LC0 VDD V LC1 P-ch IN/OUT data output disable P-ch SEG data/Bit Port data N-ch OUT N-ch output disable (N) V LC2 N-ch P.U.R. : Pull–Up Resistor TYPE M TYPE G–A VDD P.U.R. enable (Mask option) V LC0 IN/OUT P-ch data V LC1 P-ch SEG data OUT N-ch output disable N-ch V LC2 Middle voltage input buffer (resistive voltage: +10 V) N-ch P.U.R. : Pull–Up Resistor TYPE M–C TYPE G–B VDD V LC0 P.U.R. P-ch P.U.R. enable V LC1 P–ch P-ch N-ch IN/OUT OUT COM data N-ch P-ch data N-ch output disable V LC2 N-ch P.U.R. : Pull–Up Resistor 13 µPD75328 TYPE Y TYPE Z IN V DD IN P–ch N–ch + V DD Sampling C – Reference voltage AVSS Reference voltage (from a voltage tap of series resistor string) AVSS input enable 3.4 AVSS RECOMMENDED PROCESSING OF UNUSED PINS Pin P00/INT4 Recommended Connections Connect to VSS P01/SCK P02/SO/SB0 Connect to VSS or VDD P03/SI/SB1 P10/INT0-P12/INT2 P13/TI0 Connect to VSS P20/PTO0 P21 P22/PCL P23/BUZ P30-P33 Input : Connect to VSS or V DD P40-P43 Output: Open P50-P53 P60-P63 P70-P73 P80-P83 S12-S23 S24/BP0-S31/BP7 Open COM0-COM3 VLC0-VLC2 Connect to VSS BIAS Connect to VSS only when All of the VLC0-VLC2 pins are unused, otherwise, open. 14 XT1 Connect to VSS or VDD XT2 Open AVREF Connect to VSS AV SS Connect to VSS AN0-AN5 Connect to VSS or VDD µPD75328 3.5 SELECTION OF MASK OPTION The following mask operations are available and can be specified for each pin. Table 3-1 Mask Option Selection Pin P40-P43, P50-P53 Mask Option Remarks With pull-up resistor Without pull-up resistor Specification in bit units VLC0-VLC2 BIAS With voltage dividing resistor for LCD drive power source Without voltage dividing resistor for LCD drive power source Specification in 4-bit units XT1, XT2 With feed back resistor (when using the subsystem clock) Without feed back resistor (when using the subsystem clock) 3.6 ★ NOTES ON USING THE P00/INT4, AND RESET PINS In addition to the functions described in Sections 3.1 and 3.2, an exclusive function for setting the test mode, in which the internal fuctions of the µPD75328 are tested, is provided to the P00/INT4 and RESET pins. If a voltage exceeding VDD is applied to either of these pins, the µ PD75328 is put into test mode. Therefore, even when the µ PD75328 is in normal operation, if noise exceeding the VDD is input into any of these pins, the µ PD75328 will enter the test mode, and this will cause problems for normal operation. As an example, if the wiring to the P00/INT4 pin or the RESET pin is long, stray noise may be picked up and the above montioned problem may occur. Therefore, all wiring to these pins must be made short enough to not pick up stray noise. If noise cannot be avoided, suppress the noise using a capacitor or diode as shown in the figure below. • Connect a diode having a low VF across P00/INT4 and RESET, and V DD. • Connect a capacitor across P00/INT4 and RESET, and VDD . VDD VDD Low VF diode VDD VDD P00/INT4, RESET P00/INT4, RESET 15 µPD75328 4. MEMORY CONFIGURATION • Program memory (ROM) ... 8064 words × 8 bits • 0000H, 0001H : Vector table to which address from which program is started is written after reset • 0002H-000BH : Vector table to which address from which program is started is written after interrupt • 0020H-007FH : Table area referenced by GETI instruction • Data memory • Data area .... 512 words × 4 bits (000H–1FFH) • Peripheral hardware area .... 128 words × 4 bits (F80H–FFFH) Address 0000H 7 6 5 MBE 0 0 0 Internal reset start address (upper 5 bits) Internal reset start address (lower 8 bits) 0002H MBE 0 0 INTBT/INT4 start address (upper 5 bits) INTBT/INT4 start address (lower 8 bits) 0004H MBE 0 0 INT0 start address (upper 5 bits) INT0 start address (lower 8 bits) 0006H MBE 0 0 INT1 start address (upper 5 bits) INT1 start address (lower 8 bits) 0008H MBE 0 0 INTCSI start address (upper 5 bits) INTCSI start address (lower 8 bits) 000AH MBE 0 0 CALLF !faddr instruction entry address INTT0 start address (upper 5 bits) INTT0 start address (lower 8 bits) 0020H GETI instruction reference table 007FH 0080H BRCB ! caddr BR ! addr instruction instruction branch branch address address BR $addr instruction relational branch address (–15 to –1, +2 to +16) Branch destination address and subroutine entry address for GETI instruction 07FFH 0800H 0FFFH 1000H 1F7FH Fig. 4-1 Program Memory Map 16 CALL ! addr instruction subroutine entry address µPD75328 General-purpose register area 000H (8 x 4) 007H 008H Bank 0 Data area Static RAM (512 x 4) Stack area 256 x 4 (248 x 4) 0FFH 100H 256 x 4 (236 x 4) Bank 1 1EBH Display data memory 1ECH (20 x 4) 1FFH Not provided F80H Peripheral hardware area 128 x 4 Bank 15 FFFH Fig. 4-2 Data Memory Map 17 µPD75328 5. PERIPHERAL HARDWARE FUNCTIONS 5.1 PORTS I/O ports are classified into the following 4 kinds: • CMOS input (PORT0, 1) : 8 • CMOS input/output (PORT2, 3, 6, 7, and 8) : 20 • CMOS output (BP0-BP7) : 8 • N-ch open-drain input/output (PORT4, 5) : 8 Total : 44 Table 5-1 Port Function Port Name Function Operation and Feature PORT0 4-bit input PORT1 PORT2 Can be set in input or output mode in 4-bit units. Ports 6 and 7 are used in pairs to input/output data in 8-bit units. PORT7 PORT8 Can be always read or tested regardless of operation mode of multiplexed pin. 4-bit Input/Output Remarks Multiplexed with INT4, SCK, SO/SB0, and SI/SB1 Multiplexed with INT0INT2 and TI0 Multiplexed with PTO0, PCL, and BUZ Multiplexed with KR4-KR7 — Multiplexed with LCDCL and SYNC PORT3 Can be set in input or output mode in 1-bit units. Multiplexed with KR0-KR3 PORT6 PORT4 * PORT5 * 4-bit Input/Output (N-ch open-drain, 10 V) Can be set in input or output mode in 4-bit units. Ports 4 and 5 are used in pairs to input/output data in 8-bit units. BP0-BP7 1-bit output Output data in 1-bit units. Can be used as LCD drive segment output pins S24-S31 through software. *: Can directly drive LED. 18 Can be connected to a pull-up resistor in 1-bit units by using mask option. — µPD75328 5.2 CLOCK GENERATOR CIRCUIT The operation of the clock generator circuit is determined by the processor clock control regiser (PPC) and system clock control register (SCC). This circuit can generate two types of clocks: main system clock and subsystem clock. In addition, it can also change the instruction execution time. • 0.95 µs, 1.91 µs, 15.3 µs (main system clock: 4.19 MHz) • 122 µs (subsystem clock: 32.768 kHz) · Basic interval timer (BT) · Timer/event counter · Serial interface · Watch timer · LCD controller/driver · A/D converter · INT0 noise rejecter circuit · Clock output circuit XT1 V DD XT2 Subsystem clock oscillator f XT LCD controller /driver Watch timer X1 Main system f X clock oscillator WM.3 SCC SCC3 1/8 to 1/4096 Frequency divider 1/2 1/16 Oscillator disable signal Frequency divider Selector X2 Selector V DD 1/4 Internal bus SCC0 PCC PCC0 Φ · CPU · INT0 noise rejecter circuit · Clock output circuit PCC1 4 HALT F/F PCC2 S HALT* STOP* PCC3 PCC2, PCC3 clear signal R STOP F/F Q S Q Wait release signal from BT RESET signal R Standby release signal from interrupt control circuit *: instruction execution. Remarks 1: fX = Main system clock frequency 2: fXT = Subsystem clock frequency 3: Φ = CPU clock 4: PCC: Processor clock control register 5: SCC: System clock control register 6: One clock cysle (tCY) of Φ is one machine cycle of an instruction. For tCY, refer to AC ★ characteristics in 10. ELECTRICAL SPECIFICATIONS. Fig. 5-1 Clock Generator Block Diagram 19 µPD75328 5.3 CLOCK OUTPUT CIRCUIT The clock output circuit outputs clock pulse from the P22/PCL pin. This clock pulse is used for the remote control output, peripheral LSIs, etc. From the clock generator Φ Output buffer fX/23 Selector fX/24 PCL/P22 fX/26 PORT2.2 CLOM3 0 CLOM1 CLOM0 CLOM P22 output latch Bit 2 of PMGB Port 2 input/ output mode specification bit 4 Internal bus Fig. 5-2 Clock Output Circuit Configuration Remarks: A measures to prevent outputting narrow width pulse when selecting clock output enable/disable is taken. 20 µPD75328 5.4 BASIC INTERVAL TIMER The µ PD75328 is provided with the 8-bit basic interval timer. The basic interval timer has these functions: • Interval timer operation which generates a reference time interrupt • Watchdog timer application which detects a program runaway • Selects the wait time for releasing the standby mode and counts the wait time • Reads out the count value From the clock generator Clear Clear fX/25 fX/27 Set signal Basic interval timer (8-bit frequency divider circuit) MPX fX/29 BT fX/212 3 BTM3 SET1* BT interrupt request flag BTM2 BTM1 Vector interrupt request IRQBT signal Wait release signal for standby release BTM0 BTM 4 8 Internal bus Remarks : *: Instruction execution Fig. 5-3 Basic Interval Timer Configuration 21 µPD75328 5.5 WATCH TIMER The µPD75328 has a built-in 1-ch watch timer. The watch timer is configured as shown in Fig. 5-4. • Sets the test flag (IRQW) with 0.5 sec interval. The standby mode can be released by IRQW. • 0.5 second interval can be generated either from the main system clock or subsystem clock. • Time interval can be advanced to 128 times faster (3.91 ms) by setting the fast mode. This is convenient for program debugging, test, etc. • Fixed frequency (2.048 kHz) can be output to the P23/BUZ pin. This can be used for beep and system clock frequency trimming. • The frequency divider circuit can be cleared so that zero second watch start is possible. fW (512 Hz: 1.95 ms) 26 f LCD fW (256 Hz: 3.91 ms) 27 fX From the 128 (32.768 kHz) clock generator f XT (32.768 kHz) Selector fW (32.768 kHz) Frequency divider f W (2.048 16 kHz) fW 2 14 INTW (IRQW set signal) Selector (2 Hz 0.5 sec) Clear Output buffer P23/BUZ WM WM7 PORT2.3 0 0 0 WM3 WM2 WM1 WM0 8 P23 output latch Bit 2 of PMGB Port 2 input/output mode Bit test instruction Internal bus ( ) is for fX = 4.194304 MHz, fXT = 32.768 kHz. Fig. 5-4 Watch Timer Block Diagram 5.6 TIMER/EVENT COUNTER The µ PD75328 has a built-in 1-ch timer/event counter. The timer/even counter has these functions: • Programmable interval timer operation • Outputs square-wave signal of an arbitrary frequency to the PTO0 pin. • Event counter operation • Divides the TI0 pin input in N and outputs to the PTO0 pin (frequency divider operation). • Supplies serial shift clock to the serial interface circuit. • Count condition read out function 22 Internal bus 8 SET1* TM0 8 8 TMOD0 TOE0 TO enable flag Modulo register (8) TM07 TM06 TM05 TM04 TM03 TM02 TM01 TM00 Coincidence Comparator (8) Input buffer Bit 2 of PGMB Port 2 input/ output mode To serial interface 8 PORT1.3 PORT2.0 P20 output latch 8 TOUT F/F Reset P20/PTO0 Output buffer T0 P13/TI0 From the clock generator Count register (8) MPX CP Clear ( INTT0 IRQT0 set signal ) Timer operation start signal RESET IRQT0 clear signal *:Instruction execution Fig. 5-5 Timer/Event Counter Block Diagram µPD75328 23 µPD75328 5.7 SERIAL INTERFACE The µPD75328 is equipped with an 8-bit clocked serial interface that operates in the following four modes: • Operation stop mode • Three-line serial I/O mode • Two-line serial I/O mode • SBI mode (serial bus interface mode) 24 Internal bus 8/4 CSIM 8 Bit test 8 8 Slave address register (SVA) (8) SBIC Coincidence signal Address comparator RELT CMDT (8) P03/SI/SB1 SET CLR Shift register (SIO) (8) D SO latch Q ACKT ACKE BSYE Selector Bit test Bit manipulation Selector P02/SO/SB0 Busy/ acknowledge output circuit Bus release/ command/ acknowledge detector circuit P01/SCK Serial clock counter P01 output latch Serial clock control circuit RELD CMDD ACKD INTCSI control circuit ( Serial clock selector INTCSI IRQCSI set signal fX/23 fX/24 fX/26 TOUT F/F (from timer/ event counter) 25 µPD75328 External SCK Fig. 5-6 Serial Interface Block Diagram ) µPD75328 5.8 LCD CONTROLLER/DRIVER The µPD75328 is provided with a display controller that generates segment and common signals and a segment driver and a common driver that can directly drive an LCD panel. These LCD controller and drivers have the following functions: • Generate segment and common signals by automatically reading the display data memory by means of DMA • Five display modes selectable • Static • 1/2 duty (divided by 2), 1/2 bias • 1/3 duty (divided by 3), 1/2 bias • 1/3 duty (divided by 3), 1/3 bias • 1/4 duty (divided by 4), 1/3 bias • Four types of frame frequencies selectable in each display mode • Up to 20 segment signals (S12-S31) and four common signals (COM0-COM3) can be output. • Four segment signal output pins (S24-S27, S28-S31) can be used as an output port (BP0-BP3, BP4BP7). • Dividing resistor for LCD driving power source can be provided (by mask option). • All bias modes and LCD drive voltages can be used. • Current flowing to dividing resistor can be cut when display is off. • Display data memory not used for display can be used as ordinary data memory. • Can also operate on subsystem clock. 26 Internal bus 4 Display 1FEH 1FFH data memory 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 1F9H 1F8H 8 4 4 8 Display mode register Display control register Port 3 output latch 1 0 Port mode register group A 1 0 1ECH Timing controller f LCD Multiplexer Selector Segment driver S30/BP6 S24/BP0 S23 S12 LCD driving voltage control COM3 COM2 COM1 COM0 V LC2 Fig. 5-7 LCD Controller/Driver Block Diagram V LC1 V LC0 P31/ SYNC P30/ LCDCL 27 µPD75328 S31/BP7 Common driver µPD75328 5.9 A/D CONVERTER The µPD75328 is provided with an 8-bit resolution analog-to-digital (A/D) converter with six channels of analog inputs (AN0-AN5). This A/D converter is of a successive approximation type. Internal bus 8 ADM 0 ADM6 ADM5 ADM4 SOC EOC ADM1 0 8 AN0 Control circuit AN2 AN3 Multiplexer AN1 Sample hold circuit SA register (8) + – AN4 Comparator AN5 8 Tap decoder AVREF R/2 R R R R/2 Serial resistor string AVSS Fig. 5-8 Block Diagram of A/D Converter 28 µPD75328 5.10 BIT SEQUENTIAL BUFFER .... 16 BITS The bit sequential buffer is a data memory specifically provided for bit manipulation. With this buffer, addresses and bit specifications can be sequentially up-dated in bit manipulation operation. Therefore, this buffer is very useful for processing long data in bit units. FC3H Address bit 3 Symbol L register 2 FC2H 1 0 3 BSB3 L=F 2 FC1H 1 0 3 BSB2 L=C L=B 2 FC0H 1 0 3 BSB1 L=8 L=7 2 1 0 BSB0 L=4 L=3 L=0 DECS L INCS L Remarks: For the pmem.@L addressing, the specification bit is shifted according to the L register. Fig. 5-9 Bit Sequential Buffer Format 6. INTERRUPT FUNCTIONS The µPD75328 has 6 different interrupt sources and multiplexed interrupt with priority order. In addition to that, the µ PD75328 is also provided with two types of test sources, of which INT2 has two types of edge detection testable inputs. The interrupt control circuit of the µ PD75328 has these functions: • Hardware controlled vector interrupt function which can control whether or not to accept an interrupt by using the interrupt flag (IExxx) and interrupt master enable flag (IME). • The interrupt start address can be arbitrarily set. • Interrupt request flag (IRQxxx) test function (an interrupt generation can be confirmed by means of software). • Standby mode release (Interrupts to be released can be selected by the interrupt enable flag). 29 30 Internal bus 2 1 3 IM2 IM1 IM0 Interrupt enable flag (IE ××× ) INT BT INT0 /P10 INT1 /P11 Both edge detection circuit Edge Noise detection elimination circuit circuit Edge detection circuit IRQ1 INTT0 IRQT0 INTW IRQW KR0/P60 Falling edge detection circuit KR7/P73 IRQ0 IRQCSI Rising edge detection circuit VRQn IRQ4 INTCSI INT2 /P12 Decoder IRQBT Selector INT4 /P00 IST0 IME Priority control circuit Vector table address generator IRQ2 Standby release signal IM2 µPD75328 Fig. 6-1 Interrupt Control Block Diagram µPD75328 7. STANDBY FUNCTIONS The µPD75328 has two different standby modes (STOP mode and HALT mode) to reduce the power consumption while waiting for program execution. Table 7-1 Each Status in Standby Mode Mode Item STOP Mode HALT Mode Setting Instruction STOP instrtuction HALT instruction System Clock for Setting Can be set only when operating on the main system clock Can be set either with the main system clock or the subsystem clock Operation Status Clock Generator Only the main system clock stops its operation. Only the CPU clock Φ stops its operation. (oscillation continues) Basic Interval Timer No operation Can operate only when main system clock oscillates (Sets IRQBT at reference time interval) Serial Interface Can operate only when the external SCK input is selected for the serial clock Can operate only when main system clock oscillates, or when external SCK input is selected as serial clock Timer/Event Counter Can operate only when the TI0 pin input is selected for the count clock Can operate only when main system clock oscillates, or when TI0 pin input is selected as count clock Watch Timer Can operate when fXT is selected as the count clock Can operate LCD controller Can operate only when fXT is selected as LCDCL Can operate A/D Convertor No operation Can operate only when the main system clock is operating. External Interrupt INT1, INT2, and INT4 can operate. Only INT0 can not operate. CPU No operation Release Signal An interrupt request signal from a hardware whose operation is enabled by the interrupt enable flag or the RESET signal input An interrupt request signal from a hardware whose operation is enabled by the interrupt enable flag or the RESET signal input 31 µPD75328 8. RESET FUNCTION When the RESET signal is input, the µPD75328 is reset and each hardware is initialized as indicated in Table 8-1. Fig. 8-1 shows the reset operation timing. Wait (31.3ms/4.19MHz) RESET input Operation mode or standby mode HALT mode Operation mode Internal reset operation Fig. 8-1 Reset Operation by RESET Input Table 8-1 Status of Each Hardware after Reset (1/2) Hardware RESET Input in Standby Mode RESET Input during Operation The contents of the lower 5 bits of address 0000H of the program memory are set to PC12-8, and the contents of address 0001H are set to PC7-0. The contents of the lower 5 bits of address 0000H of the program memory are set to PC12-8, and the contents of address 0001H are set to PC7-0. Retained Undefined Skip Flag (SK0-2) 0 0 Interrupt Status Flag (IST0) 0 0 Program Counter (PC) PSW Carry Flag (CY) Bank Enable Flag (MBE) The contents of bit 7 of address 0000H of the program memory are set to MBE. Stack Pointer (SP) Undefined Undefined Data Memory (RAM) Retained * 1 Undefined Retained Undefined 0 0 Undefined Undefined 0 0 General-Purpose Register (X, A, H, L, D, E, B, C) Bank Selection Register (MBS) Basic Interval Counter (BT) Timer Mode Register (BTM) Timer/Event Counter Counter (T0) Module Register (TMOD0) Mode Register (TM0) TOE0, TOUT F/F Watch Timer 32 The contents of bit 7 of address 0000H of the program memory are set to MBE. Mode Register (WM) 0 0 FFH FFH 0 0 0, 0 0, 0 0 0 µPD75328 Table 8-1 Status of Each Hardware after Reset (2/2) Hardware Serial Interface Clock Generator, Clock Output Circuit LCD Controller Shift Register (SIO) Retained Undefined 0 0 SBI Control Register (SBIC) 0 0 Slave Address Register (SVA) Retained Undefined Processor Clock Control Register (PCC) 0 0 System Clock Control Register (SCC) 0 0 Clock Output Mode Register (CLOM) 0 0 Display Mode Register (LCMD) 0 0 Display Control Register (LCDC) 0 0 04H (EOC = 1) 04H (EOC = 1) SA Register Digital Port Pin States RESET Input during Operation Operation Mode Register (CSIM) A/D Converter Mode Regiseter (ADM), EOC Interrupt Function RESET Input in Standby Mode 7FH 7FH Reset (0) Reset (0) Interrupt Enable Flag (IExxx) 0 0 Interrupt Master Enable Flag (IME) 0 0 INT0, INT1, INT2 Mode Registers (IM0, 1, 2) 0, 0, 0 0, 0, 0 Interrupt Request Flag (IRQxxx) Output Buffer Off Off Output Latch Clear (0) Clear (0) Input/Output Mode Register (PMGA, B, C) 0 0 Pull-Up Resistor Specification Register (POGA, B) 0 0 Input Input P00-P03, P10-P13, P20-P23, P30-P33, P60-P63, P70-P73, P80-P83 P40-P43, P50-P53 S12-S23, COM0-COM3 BIAS Bit Sequential Buffer (BSB0-3) • Internal pull-up resistors ... High level • Open drain ... High impedance Same as at left *2 *2 • Internal step-down resistors ... Low level • External step-down resistors ... High impedance Same as at left Retained Specified 33 µPD75328 *1: Data of address 0F8H to 0FDH of the data memory becomes undefined when a RESET signal is input. 2: Select V LCX as shown below as the input source for each display output. S12-31 : VLC1 COM0-2 : VLC2 COM3 : VLC0 However, the level of each display output varies according to the display output and the external circuit for VLCX. 9. INSTRUCTION SET (1) Operand representation and description Describe one or more operands in the operand field of each instruction according to the operand representation and description methods of the instruction (for details, refer to RA75X Assembler Package User's Manual - Language (EEU-730)). With some instructions, only one operand should be selected from several operands. The uppercase characters, +, and – are keywords and must be described as is. Describe an appropriate numeric value or label as immediate data. Representation 34 Description reg reg1 X, A, B, C, D, E, H, L X, B, C, D, E, H, L rp rp1 rp2 XA, BC, DE, HL BC, DE, HL BC, DE rpa rpa1 HL, DE, DL DE, DL n4 n8 4-bit immediate data or label 8-bit immediate data or label mem bit 8-bit immediate data or label 2-bit immediate data or label fmem pmem FB0H to FBFH,FF0H to FFFH immediate data or label FC0H to FFFH immediate data or label addr caddr faddr 0000H to 1F7FH immediate data or label 12-bit immediate data or label 11-bit immediate data or label taddr 20H to 7FH immediate data (where bit0 = 0) or label PORTn IExxx MBn PORT0 to PORT8 IEBT, IECSI, IET0, IE0, IE1, IE2, IE4, IEW MB0, MB1, MB15 µPD75328 (2) Legend of operation field A : A register; 4-bit accumulator B : B register; 4-bit accumulator C : C register; 4-bit accumulator D : D register; 4-bit accumulator E : E register; 4-bit accumulator H : H register; 4-bit accumulator L : L register; 4-bit accumulator X : X register; 4-bit accumulator XA : Register pair (XA); 8-bit accumulator BC : Register pair (BC); 8-bit accumulator DE : Register pair (DE); 8-bit accumulator HL : Register pair (HL); 8-bit accumulator PC : Program counter SP : Stack pointer CY : Carry flag; or bit accumulator PSW : Program status word MBE : Memory bank enable flag PORTn : Port n (n = 0 to 8) IME : Interrupt mask enable flag IExxx : Interrupt enable flag MBS : Memory bank selector register PCC . : Processor clock control register (xx) : Contents addressed by xx xxH : Hexadecimal data : Delimiter of address and bit 35 µPD75328 (3) Symbols in addressing area field *1 MB = MBE . MBS (MBS = 0, 1, 15) *2 MB = 0 *3 MBE = 0 : MB = 0 (00H-7FH) MB = 15 (80H-FFH) MBE = 1 : MB = MBS (MBS = 0, 1, 15) *4 MB = 15, fmem = FB0H-FBFH, FF0H-FFFH *5 MB = 15, pmem = FC0H-FFFH *6 addr = 000H-1F7FH *7 addr = (Current PC) – 15 to (Current PC) – 1 (Current PC) + 2 to (Current PC) + 16 *8 caddr = 0000H-0FFFH (PC 12 = 0) or 1000H-1F7FH (PC 12 = 1) *9 faddr = 0000H-07FFH *10 taddr = 0020H-007FH Remarks 1: Data memory addressing Program memory addressing MB indicates memory bank that can be accessed. 2: In *2, MB = 0 regardless of MBE and MBS. 3: In *4 and *5, MB = 15 regardless of MBE and MBS. 4: *6 to *10 indicate areas that can be addressed. (4) Machine cycle field In this field, S indicates the number of machine cycles required when an instruction having a skip function skips. The value of S varies as follows: • When no instruction is skipped .................................................................................. S = 0 • When 1-byte or 2-byte instruction is skipped ........................................................... S = 1 • When 3-byte instruction (BR ! addr or CALL ! addr) is skipped ............................ S = 2 Note : The GETI instruction is skipped in one machine cycle. One machine cycle equals to one cycle of the CPU clock Φ, (=tCY), and can be changed in three steps depending on the setting of the processor clock control register (PCC). 36 µPD75328 Instructions Mnemonics Transfer MOV XCH MOVT Arith- ADDS metic Operand Machine Bytes Cycles 1 1 A ← n4 reg1, #n4 2 2 reg1 ← n4 XA, #n8 2 2 XA ← n8 String effect A HL, #n8 2 2 HL ← n8 String effect B rp2, #n8 2 2 rp2 ← n8 A, @HL 1 1 A ← (HL) A, @rpa1 1 1 A ← (rpa1) *2 XA, @HL 2 2 XA ← (HL) *1 @HL, A 1 1 (HL) ← A *1 @HL, XA 2 2 (HL) ← XA *1 A,mem 2 2 A ← (mem) *3 2 2 XA ← (mem) *3 2 2 (mem) ← A *3 *3 mem, XA 2 2 (mem) ← XA A, reg 2 2 A ← reg XA, rp 2 2 XA ← rp reg1, A 2 2 reg1 ← A rp1, XA 2 2 rp1 ← XA A, @HL 1 1 A ↔ (HL) *1 A, @rpa1 1 1 A ↔ (rpa1) *2 XA, @HL 2 2 XA ↔ (HL) *1 A, mem 2 2 A ↔ (mem) *3 XA, mem 2 2 XA ↔ (mem) *3 A, reg1 1 1 A ↔ reg1 XA, rp 2 2 XA ↔ rp XA, @PCDE 1 3 XA ← (PC12-8+DE)ROM XA, @PCXA 1 3 XA ← (PC12-8 +XA)ROM A, #n4 1 1+S A ← A+n4 A, @HL 1 1+S A ← A+(HL) carry *1 A, CY ← A+(HL)+CY *1 A ← A-(HL) *1 1 A, CY ← A-(HL)-CY *1 A ← A ∧ n4 A, @HL 1 1 SUBS A, @HL 1 1+S SUBC A, @HL 1 Accumu- RORC lator Manipu- NOT lation *1 mem, A ADDC XOR String effect A XA, mem tion OR Skip Conditions A, #n4 Opera- AND Operation Addressing Area A, #n4 2 2 A, @HL 1 1 A ← A ∧ (HL) A, #n4 2 2 A ← A ∨ n4 A, @HL 1 1 A ← A ∨ (HL) A, #n4 2 2 A ← A ∨ n4 A, @HL 1 1 A ← A ∨ (HL) A 1 1 CY ← A0, A3 ← CY, An-1 ← An A 2 2 A←A carry borrow *1 *1 *1 37 µPD75328 Instructions Mnemonics Incre- INCS Operand Machine Bytes Cycles Operation Addressing Area Skip Conditions reg 1 1+S reg ← reg+1 ment/ @HL 2 2+S (HL) ← (HL)+1 *1 (HL) = 0 Decre- mem 2 2+S (mem) ← (mem)+1 *3 (mem) = 0 ment DECS Compare SKE reg = 0 reg 1 1+S reg ← reg-1 reg = FH reg, #n4 2 2+S Skip if reg = n4 reg = n4 @HL, #n4 2 2+S Skip if (HL) = n4 A, @HL 1 1+S Skip if A = (HL) A, reg 2 2+S Skip if A = reg *1 (HL) = n4 *1 A = reg Carry SET1 CY 1 1 CY ← 1 flag CLR1 CY 1 1 CY ← 0 Manipu- SKT CY 1 1+S lation CY 1 1 CY ← CY mem.bit 2 2 (mem.bit) ← 1 *3 Bit fmem.bit 2 2 (fmem.bit) ← 1 *4 Manipu- pmem.@L 2 2 (pmem7-2 + L 3-2.bit(L1-0)) ← 1 *5 lation @H+mem.bit 2 2 (H + mem 3-0.bit) ← 1 *1 mem.bit 2 2 (mem.bit) ← 0 *3 fmem.bit 2 2 (fmem.bit) ← 0 *4 pmem.@L 2 2 (pmem 7-2 + L 3-2.bit(L1-0)) ← 0 *5 NOT1 Memory/ SET1 CLR1 SKT SKF OR1 XOR1 38 Skip if CY = 1 CY = 1 @H+mem.bit 2 2 (H+mem3-0.bit) ← 0 *1 mem.bit 2 2+S Skip if (mem.bit) = 1 *3 fmem.bit 2 2+S Skip if (fmem.bit) = 1 *4 (fmem.bit) = 1 pmem.@L 2 2+S Skip if (pmem 7-2+L 3-2.bit (L1-0 )) = 1 *5 (pmem.@L) = 1 @H+mem.bit 2 2+S Skip if (H + mem 3-0.bit) = 1 *1 (@H+mem.bit) = 1 (mem.bit) = 0 (mem.bit) = 1 mem.bit 2 2+S Skip if (mem.bit) = 0 *3 fmem.bit 2 2+S Skip if (fmem.bit) = 0 *4 (fmem.bit) = 0 pmem.@L 2 2+S Skip if (pmem7-2 +L3-2.bit (L1-0)) = 0 *5 (pmem.@L) = 0 @H+mem.bit 2 2+S Skip if (H + mem 3-0.bit) = 0 *1 (@H+mem.bit) = 0 2 2+S Skip if (fmem.bit) = 1 and clear *4 (fmem.bit) = 1 pmem.@L 2 2+S Skip if (pmem 7-2+L 3-2.bit (L 1-0)) = 1 and clear *5 (pmem.@L) = 1 @H+mem.bit 2 2+S Skip if (H+mem3-0.bit) = 1 and clear *1 (@H+mem.bit) = 1 *4 SKTCLR fmem.bit AND1 A = (HL) CY,fmem.bit 2 2 CY ← CY ∧ (fmem.bit) CY,pmem.@L 2 2 CY ← CY ∧ (pmem7-2+L 3-2.bit(L1-0)) *5 CY,@H+mem.bit 2 2 CY ← CY ∧ (H+mem3-0.bit) *1 CY,fmem.bit 2 2 CY ← CY ∨ (fmem.bit) *4 CY,pmem.@L 2 2 CY ← CY ∨ (pmem7-2+L3-2.bit (L1-0)) *5 CY,@H+mem.bit 2 2 CY ← CY ∨ (H+mem3-0.bit) *1 CY,fmem.bit 2 2 CY ← CY ∨ (fmem.bit) *4 CY,pmem.@L 2 2 CY ← CY ∨ (pmem7-2+L 3-2.bit (L1-0)) *5 CY,@H+mem.bit 2 2 CY ← CY ∨ (H+mem3-0.bit) *1 µPD75328 Instructions Mnemonics Branch BR Subroutine/ Operand addr Machine Bytes Cycles — — PC12-0 ← addr (The most suitable instruction is selectable from among BR !addr, BRCB !caddr, and BR $addr depending on the assembler.) *6 3 3 PC12-0 ← addr *6 $addr 1 2 PC12-0 ← addr *7 BRCB !caddr 2 2 PC11-0 ← caddr 11-0 *8 CALL !addr 3 3 (SP-4)(SP-1)(SP-2) ← PC11-0 (SP-3) ← MBE, 0, 0, PC12 PC12-0 ← addr, SP ← SP-4 *6 CALLF !faddr 2 2 (SP-4)(SP-1)(SP-2) ← PC11-0 (SP-3) ← MBE, 0, 0, PC12 PC12-0 ← 00, faddr, SP ← SP-4 *9 RET 1 3 MBE, x, x, PC12 ← (SP+1) PC11-0 ← (SP)(SP+3)(SP+2) SP ← SP+4 RETS 1 3+S MBE, x, x, PC12 ← (SP+1) PC11-0 ← (SP)(SP+3)(SP+2) SP ← SP+4, then skip unconditionally RET1 1 3 MBE, x, x, PC12 ← (SP+1) PC11-0 ← (SP)(SP+3)(SP+2) PSW ← (SP+4)(SP+5), SP ← SP+6 rp 1 1 (SP-1)(SP-2) ← rp, SP ← SP-2 BS 2 2 (SP-1) ← MBS, (SP-2) ← 0, SP ← SP-2 rp 1 1 rp ← (SP+1)(SP), SP ← SP+2 BS 2 2 MBS ← (SP+1), SP ← SP+2 2 2 IME ← 1 IExxx 2 2 IExxx ← 1 2 2 IME ← 0 IExxx 2 2 IExxx ← 0 *1 A,PORTn 2 2 A ← PORTn (n = 0-8) 2 2 XA ← PORTn+1,PORTn (n = 4, 6) PUSH POP Inter- Operation !addr Stack Control Addressing Area EI rupt Control DI I/O IN XA,PORTn OUT * 1 PORTn,A 2 2 PORTn ← A (n = 2-8) PORTn,XA 2 2 PORTn+1 ,PORTn ← XA (n = 4, 6) CPU HALT 2 2 Set HALT Mode (PCC.2 ← 1) Control STOP 2 2 Set STOP Mode (PCC.3 ← 1) NOP 1 1 No Operation Special SEL MBn GETI *2 taddr 2 2 1 3 MBS ← n (n = 0, 1, 15) . Where TBR instruction, PC12-0 ← (taddr)4-0+(taddr+1) ......................................................... . Where TCALL instruction, (SP-4)(SP-1)(SP-2) ← PC11-0 (SP-3) ← MBE, 0, 0, PC 12 PC12-0 ← (taddr)4-0+(taddr+1) SP ← SP-4 ......................................................... . Except for TBR and TCALL instructions, Instruction execution of (taddr)(taddr+1) Skip Conditions Undefined *10 ............................. ............................. Depends on referenced instruction *1: When executing the IN/OUT instruction, MBE = 0, or MBE = 1, and MBS = 15. 2: The TBR, and TCALL instructions are the assembler pseudo-instructions for the table definition of GETI instruction. 39 µPD75328 10. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (Ta = 25°C) Parameter Symbol Supply Voltage Conditions Ratings VDD Input Voltage VI1 Other than ports 4, 5 VI2 Ports 4, 5 w/pull-up resistor -0.3 to +7.0 V -0.3 to VDD +0.3 V -0.3 to VDD +0.3 Open drain Output Voltage VO High-Level Output Current IOH Low-Level Output IOL* Unit -0.3 to +11 V V -0.3 to VDD +0.3 V 1 pin -15 mA All pins -30 mA 1 pin Current Other than ports 0, 2, 3, 5, 8 Total of ports 4, 6, 7 Peak 30 mA rms 15 mA Peak 100 mA rms 60 mA Peak 100 mA 60 mA Operating Temperature Topt rms -40 to +85 °C Storage Temperature Tstg -65 to +150 °C *: rms = Peak value x √Duty CAPACITANCE (Ta = 25°C, V DD = 0 V) Parameter Symbol Input Capacitance CIN Output Capacitance COUT Input/Output Capacitance CIO Conditions MIN. TYP. f = 1 MHz Pins other than thosemeasured are at 0 V MAX. Unit 15 pF 15 pF 15 pF OPERATING SUPPLY VOLTAGE Parameter A/D Converter Supply voltage Ambient temperature Other Circuits Supply voltage Ambient temperatuare 40 Symbol Conditions MIN. MAX. Unit VDD 3.5 6.0 V Ta -10 +70 °C VDD 2.7 6.0 V Ta -40 +85 °C µPD75328 MAIN SYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS (Ta = -40 to +85°C, VDD = 2.7 to 6.0 V) Oscillator Recommended Constants Ceramic *3 Item Conditions Oscillation frequency(fXX )*1 X1 X2 C1 C2 MIN. TYP. 1.0 MAX. 5.0 Oscillation stabiliza- After VDD came to MIN. of oscillation tion time*2 voltage range *4 4 Unit MHz ms VDD Crystal *3 Oscillation frequency (fXX )*1 X1 X2 C1 1.0 4.19 Oscillation stabiliza- VDD = 4.5 to 6.0 V tion time*2 5.0 *4 MHz 10 ms 30 ms C2 VDD External Clock X1 input frequency (f X)* 1 X1 X2 µ PD74HCU04 1.0 X1 input high-, low-level widths (t XH, t XL) 5.0 100 *4 500 MHz ns *1: The oscillation frequency and X1 input frequency are indicated only to express the characteristics of the oscillator circuit. For instruction execution time, refer to AC Characteristics. 2: Time required for oscillation to stabilize after V DD reaches the minimum value of the oscillation voltage range or the STOP mode has been released. 3: The oscillators on the next page are recommended. 4: When the oscillation frequency is 4.19 MHz < fx ≤ 5.0 MHz, do not select PCC = 0011 as the instruction execution time: otherwise, one machine cycle is set to less than 0.95 µs, falling short of the rated minimum value of 0.95 µs. SUBSYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS (Ta = -40 to +85°C, VDD = 2.7 to 6.0 V) Oscillator Recommended Constants Crystal XT1 Conditions Oscillation frequency (fXT) XT2 R C3 Item MIN. TYP. MAX. 32 32.768 35 kHz 1.0 2 s 10 s Oscillation stabiliza- VDD = 4.5 to 6.0 V tion time* C4 Unit VDD External Clock XT1 XT2 Open XT1 input frequency (f XT)* 32 100 kHz XT1 input high-, low-level widths (t XTH, t XTL ) 5 15 µs 41 ★ µPD75328 *: Time required for oscillation to stabilize after VDD reaches the minimum value of the oscillation voltage range. Note: When using the oscillation circuit of the main system clock and subsystem clock, wire the portion enclosed in dotted line in the figures as follows to avoid adverse influences on the wiring capacity: • Keep the wiring length as short as possible. • Do not cross the wiring over the other signal lines. Do not route the wiring in the vicinity of lines through which a high alternating current flows. • Always keep the ground point of the capacitor of the oscillator circuit at the same potential as VDD . Do not connect the power source pattern through which a high current flows. • Do not extract signals from the oscillation circuit. The amplification factor of the subsystem clock oscillation circuit is designed to be low to reduce the current dissipation and therefore, the subsystem clock oscillation circuit is influenced by noise more easily than the main system clock oscillation circuit. When using the subsystem clock, therefore, exercise utmost care in wiring the circuit. RECOMMENDED OSCILLATION CIRCUIT CONSTANTS MAIN SYSTEM CLOCK: CERAMIC OSCILLATOR (Ta = -40 to +85°C) Manufacturer Murata Mfg. Co., Ltd. Product Name CSAx.xxMG093 Frequency (MHz) 2.00 to 2.44 CSTx.xxMG093 CSAx.xxMGU 2.45 to 5.00 CSTx.xxMGU CSAx.xxMG Recommended Circuit Constants Operating Voltage Range C1 (pF) C2 (pF) MIN. (V) 30 30 2.7 Unnecessary Unnecessary 2.7 30 30 2.7 Unnecessary Unnecessary 2.7 30 30 3.0 MAX. (V) 6.0 2.00 to 5.00 CSTx.xxMG Kyoto Ceramic Co., Ltd. Unnecessary Unnecessary 3.0 KBR-2.0MS 2.00 47 47 2.7 KBR-4.0MS 4.00 33 33 2.7 KBR-5.0M 5.00 33 33 3.0 6.0 MAIN SYSTEM CLOCK: CRYSTAL OSCILLATOR (Ta = -20 to +70°C) Manufacturer Kinseki Product Name HC-18U HC-43U, 49/U Frequency (MHz) 2.0 to 5.0 Operating Voltage Range Recommended Circuit Constants C1 (pF) C2 (pF) MIN. (V) MAX. (V) 22 * 22 2.7 6.0 *: Adjust the oscillation frequency in a range of C1 = 15 to 33 pF. SUBSYSTEM CLOCK: CRYSTAL OSCILLATOR (Ta = -10 to +60°C) Manufacturer Kinseki Product Name P3 Frequency (MHz) 32.768 C3 (pF) C4 (pF) R (kΩ) MIN. (V) MAX. (V) 22 * 22 330 2.7 6.0 *: Adjust the oscillation frequency in a range of C3 = 3 to 30 pF. 42 Operating Voltage Range Recommended Circuit Constants µPD75328 DC CHARACTERISTICS (Ta = -40 to +85°C, VDD = 2.7 to 6.0 V) Parameter High-Level Input Voltage Low-level Input Voltage High-Level Output Voltage Low-Level Output Voltage High-Level Input Leakage Current Low-Level Input Leakage Current High-Level Output Leakage Current Low-Level Output Leakage Current Symbol Conditions MIN. TYP. MAX. Unit VIH1 Ports 2, 3, 8 0.7VDD VDD V VIH2 Ports 0, 1, 6, 7, RESET 0.8VDD VDD V VIH3 Ports 4, 5 w/pull-up resistor 0.7VDD VDD V Open-drain 0.7VDD 10 V VDD -0.5 VDD V VIH4 X1, X2, XT1 VIL1 Ports 2, 3, 4, 5, 8 0 0.3VDD V VIL2 Ports 0, 1, 6, 7, RESET 0 0.2VDD V VIL3 X1, X2, XT1 0 0.4 V VOH1 Ports 0, 2, 3, 6, 7, 8, and BIAS VOH2 BP0-7 (with two IOH outputs) VOL1 Ports 0, 2, 3, 4, 5, 6, 7, and 8 Ports 3, 4, and 5 VDD = 4.5 to 6.0 V IOL = -15 mA VDD = 4.5 to 6.0 V IOH = -1 mA VDD -1.0 V IOH = -100 µA VDD -0.5 V VDD = 4.5 to 6.0 V IOH = -100 µA VDD -2.0 V IOH = -50 µA VDD -1.0 V 0.4 2.0 V VDD = 4.5 to 6.0 V IOL = 1.6 mA 0.4 V IOL = 400 µA 0.5 V 0.2V DD V V SB0, 1 Open-drain Pull-up resistor ≥ 1 kΩ VOL2 BP0-7 (with two IOL outputs) VDD = 4.5 to 6.0 V IOL = 100 µA 1.0 IOL = 50 µA 1.0 V ILIH1 VIN = VDD Other than below 3 µA X1, X2, XT1 20 µA ILIH3 VIN = 10 V Ports 4, 5 (open-drain) 20 µA ILIL1 VIN = 0 V Other than below -3 µA X1, X2, XT1 -20 µA 3 µA 20 µA -3 µA 80 kΩ ILIH2 ILIL2 ILOH1 VOUT = VDD Other than below ILOH2 VOUT = 10 V Ports 4, 5 (open-drain) ILOL VOUT = 0 V Internal Pull-Up Resistor RL1 RL2 Ports 0, 1, 2, 3, 6, 7, 8 (except P00) V IN = 0V VDD = 5.0 V±10% 15 VDD = 3.0 V±10% 30 Ports 4, 5 VOUT = VDD-2.0 V VDD = 5.0 V±10% 15 LCD Drive Voltage VLCD LCD Step-down Resistor RLCD LCD Output Voltage Deviation (Common) * 1 VODC IO = ±5 µA LCD Output Voltage Deviation (Segment) * 1 VODS IO = ±1 µA VDD = 3.0 V±10% 300 kΩ 70 kΩ 10 60 kΩ 2.5 VDD V 60 VLCD0 = VLCD VLCD1 = VLCD ×2/3 VLCD2 = VLCD ×1/3 2.7 V ≤ VLCD ≤ VDD 40 40 140 kΩ 0 100 ±0.2 V V 0 ±0.2 V V 43 µPD75328 Parameter Supply Current Symbol *2 IDD1 IDD2 IDD3 Conditions MHz*3 TYP. MAX. Unit 2.5 8 mA VDD = 3 V±10%*5 0.35 1.2 mA VDD = 5 V±10% 500 1500 µA 4.19 crystal oscillator C1 = C2 = 22pF VDD = 5 VDD = 3 V±10% 150 450 µA 32 kHz*6 crystal oscillator Operation mode VDD = 3 V±10% 30 90 µA HALT mode VDD = 3 V±10% IDD4 IDD5 MIN. V±10%*4 XT1 = 0 V STOP mode HALT mode 5 15 µA VDD = 5 V±10% 0.5 20 µA VDD = 3 V±10% 0.1 10 µA 0.1 5 µA Ta = 25°C *1: "Voltage deviation" means the difference between the ideal segment or common output value (VLCDn: n = 0, 1, 2) and output voltage. 2: Currents for the built-in pull-up resistor and the LCD step-down resistor are not included. 3: Including when the subsystem clock is operated. 4: When operand in the high-speed mode with the processor clock control register (PCC) set to 0011. 5: When operated in the low-speed mode with the PCC set to 0000. 6: When operated with the subsystem clock by setting the system clock control register (SCC) to 1011 to stop the main system clock operation. 44 µPD75328 A/D CONVERTER (Ta = -10 to +85°C, VDD = 3.5 to 6.0 V, AV SS = VSS = 0 V) Parameter Symbol Conditions Resolution MIN. TYP. 8 8 2.5 V ≤ AVREF ≤ VDD *2 Absolute Accuracy*1 MAX. Unit 8 bit ±1.5 LSB Conversion Time tCONV *3 168/fX S Sampling Time tSAMP *4 44/f X S Analog Input Voltage VIAN AVREF V AVSS Analog Input Impedance RAN 1000 AVREF Current IREF 0.25 *1: Absolute accuracy excluding quantization error (± MΩ 2.0 mA 1 –2 LSB) 2: Set ADM1 as follows, in respect to the reference voltage of the AD converter (AVREF). 2.5 V 0.6 V DD 0.65 V DD V DD (3.5 to 6.0 V) AV REF ADM1=0 ADM1=1 ADM1 can be set to either 0 or 1 when 0.6VDD ≤ AVREF ≤ 0.65VDD 3: Time since execution of conversion start instruction until EOC = 1 (fX = 4.19 MHz: 40.1 µs) 4: Time since execution of conversion start instruction until end of sampling (fX = 4.19 MHz: 10.5 µ s) 45 µPD75328 AC CHARACTERISTICS (Ta = -40 to +85°C, VDD = 2.7 to 6.0 V) Parameter Symbol Conditions w/main system clock MIN. VDD = 4.5 to 6.0 V TYP. MAX. Unit 0.95 64 µs 3.8 64 µs 125 µs CPU Clock Cycle Time (Minimum Instruction Execution Time = 1 Machine Cycle)*1 tCY TI0 Input Frequency fTI VDD = 4.5 to 6.0 V 0 1 MHz 0 275 kHz TI0 Input High-, LowLevel Widths tTIH, tTIL VDD = 4.5 to 6.0 V 0.48 µs 1.8 µs Interrupt Input High-, Low-Level Widths tINTH, tINTL INT0 *2 µs INT1, 2, 4 10 µs 10 µs RESET Low-Level Width tRSL 10 µs w/sub-system clock 114 KR0-7 122 tCY vs VDD *1: The CPU clock (Φ) cycle time is (with main system clock) 70 determined by the oscillation frequency 64 30 of the connected oscillator, system clock control register (SCC), and processor 6 The figure on the right is cycle time tCY 5 vs. supply voltage VDD characteristics 4 at the main system clock. 2: 2tCY or 128/fX depending on the setting of the interrupt mode register (IM0). Cycle time tCY [µs] clock control register (PCC). 3 2 1 0.5 0 1 2 3 4 Supply voltage VDD [V] 46 5 6 µPD75328 SERIAL TRANSFER OPERATION Two-Line and Three-Line Serial I/O Modes (SCK: internal clock output) Parameter SCK Cycle Time SCK High-, Low-Level Widths SI Set-Up Time (vs. SCK ↑) Symbol tKCY1 tKL1 Conditions MIN. VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V MAX. Unit 1600 ns 3800 ns tKCY1/2-50 ns tKH1 tKCY1/2-150 ns tSIK1 150 ns SI Hold Time (vs. SCK ↑ ) tKSI1 SCK ↓→ SO Output Delay Time TYP. tKSO1 400 RL = 1 kΩ, CL = 100 pF* ns V DD = 4.5 to 6.0 V 250 ns 1000 ns MAX. Unit *: RL and CL are load resistance and load capacitance of the SO output line. TWO-LINE AND THREE-LINE SERIAL I/O MODES (SCK: external clock input) Parameter SCK Cycle Time SCK High-, Low-Level Widths Symbol tKCY2 tKL2 Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V MIN. TYP. 800 ns 3200 ns 400 ns tKH2 1600 ns SI Set-Up Time (vs. SCK ↑) tSIK2 100 ns SI Hold Time (vs. SCK ↑) tKSI2 400 ns SCK ↓→ SO Output Delay Time tKSO2 RL = 1 kΩ, CL = 100 pF* VDD = 4.5 to 6.0 V 300 ns 1000 ns *: RL and CL are load resistance and load capacitance of the SO output line. 47 µPD75328 SBI MODE (SCK: internal clock output (master)) Parameter SCK Cycle Time Symbol tKCY3 Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V MIN. TYP. MAX. Unit 1600 ns 3800 ns SCK High-, Low-Level Widths tKL3 tKH3 SB0, 1 Set-Up Time (vs. SCK ↑ ) tSIK3 SB0, 1 Hold Time (vs. SCK ↑ ) tKSI3 SCK ↓← SB0, 1 Output Delay Time tKSO3 SCK ↑→ SB0, 1 ↓ tKSB tKCY3 ns SB0,1 ↓→ SCK tSBK tKCY3 ns SB0, 1 Low-Level Width tSBL tKCY3 ns SB0, 1 High-Level Width tSBH tKCY3 ns RL = 1 kΩ, CL = 100 pF* VDD = 4.5 to 6.0 V tKCY3/2-50 ns tKCY3/2-150 ns 150 ns tKCY3/2 ns 0 250 ns 0 1000 ns *: RL and CL are load resistance and load capacitance of the SO output line. SBI MODE (SCK: external clock input (slave)) Parameter SCK Cycle Time Symbol tKCY4 Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V MIN. MAX. Unit 800 ns 3200 ns SCK High-, Low-Level Widths tKL4 tKH4 SB0, 1 Set-Up Time (vs. SCK ↑ ) tSIK4 SB0, 1 Hold Time (vs. SCK ↑ ) tKSI4 SCK ↓← SB0, 1 Output Delay Time tKSO4 SCK ↑→ SB0, 1 ↓ tKSB tKCY4 ns SB0,1 ↓→ SCK ↓ tSBK tKCY4 ns SB0, 1 Low-Level Width tSBL tKCY4 ns SB0, 1 High-Level Width tSBH tKCY4 ns RL = 1 kΩ, CL = 100 pF* VDD = 4.5 to 6.0 V 400 ns 1600 ns 100 ns tKCY4/2 ns 0 300 ns 0 1000 ns *: RL and CL are load resistance and load capacitance of the SO output line. 48 TYP. µPD75328 AC TIMING TEST POINT (excluding X1 and XT1 inputs) 0.8 VDD 0.8 VDD Test points 0.2 VDD 0.2 VDD CLOCK TIMING 1/fX tXL tXH X1 input VDD –0.5V 0.4 V 1/fXT tXTL tXTH XT1 input VDD –0.5V 0.4 V TI0 TIMING 1/fTI tTIL tTIH TI0 49 µPD75328 SERIAL TRANSFER TIMING THREE-LINE SERIAL I/O MODE: tKCY1 tKL1 tKH1 SCK tSIK1 SI tKSI1 Input data tKSO1 Output data SO TWO-LINE SERIAL I/O MODE: tKCY2 tKH2 tKL2 SCK tSIK2 SB0,1 tKSO2 50 tKSI2 µPD75328 SERIAL TRANSFER TIMING BUS RELEASE SIGNAL TRANSFER: t KCY3,4 tKL3,4 tKH3,4 SCK tKSB tSBL tSBH tSIK3,4 tSBK tKSI3,4 SB0,1 tKSO3,4 COMMAND SIGNAL TRANSFER: tKCY3,4 tKL3,4 tKH3,4 SCK tKSB tSIK3,4 tSBK tKSI3,4 SB0,1 tKSO3,4 INTERRUPT INPUT TIMING: tINTL tINTH INT0, 1, 2, 4 KR0-7 RESET INPUT TIMING: tRSL RESET 51 µPD75328 LOW-VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE (Ta = –40 to +85 °C) Parameter Symbol Data Retention Supply Voltage VDDDR Data Retention Supply Current* 1 IDDDR Release Signal Set Time tSREL Oscillation Stabilization tWAIT Wait Time* 2 Conditions MIN. TYP. MAX. Unit 6.0 V 10 µA 2.0 V DDDR = 2.0 V 0.1 µs 0 Released by RESET Released by interrupt 217/fX ms *3 ms *1: Does not include current flowing through internal pull-up resistor 2: The oscillation stabilization wait time is the time during which the CPU is stopped to prevent unstable operation when oscillation is started. 3: Depends on the setting of the basic interval timer mode register (BTM) as follows: BTM3 BTM2 BTM1 BTM0 – 0 0 0 220/fXX (approx. 250 ms) – 0 1 1 217/fXX (approx. 31.3 ms) – 1 0 1 215/fXX (approx. 7.82 ms) – 1 1 1 213/fXX (approx. 1.95 ms) WAIT time ( ): fXX = 4.19 MHz DATA RETENTION TIMING (releasing STOP mode by RESET) Internal reset operation HALT mode STOP mode Operation mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT DATA RETENTION TIMING (standby release signal: releasing STOP mode by interrupt) HALT mode STOP mode Operation mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT 52 µPD75328 11. CHARACTERISTIC CURVES (REFERENCE VALUE) I DD vs V DD (Crystal oscillation: 4.19 MHz) (Ta = 25˚C) 5000 High-speed mode PCC=0011 Middle-speed mode PCC=0010 Low-speed mode PCC=0000 1000 Main system clock HALT mode Power supply current I DD [ µ A] 500 Main system clock STOP mode + Subsystem clock operation mode 100 50 Main system clock STOP mode + 32 kHz oscillation only or subsystem clock HALT mode X1 10 5 22 pF X2 XT1 XT2 Crystal 4.19 MHz Crystal 32.768 kHz 330 kΩ 22 pF 22 pF 22 pF V DD V DD 2 0 1 2 3 4 5 6 7 Power supply valtage V DD [V] 53 µPD75328 I DD vs V DD (Ceramic oscillation: 4.19 MHz) (Ta= 25˚C) 5000 High-speed mode PCC=0011 Middle-speed mode PCC=0010 Low-speed mode PCC=0000 1000 Main system clock HALT mode Power supply current I DD [ µ A] 500 Main system clock STOP mode + Subsystem clock operation mode 100 50 Main system clock STOP mode + 32 kHz oscillation only or subsystem clock HALT mode X1 10 5 30 pF X2 XT1 XT2 Ceramic oscillator CSA4.19MG Crystal 32.768 kHz 330 kΩ 30 pF 22 pF 22 pF V DD V DD 2 0 1 2 3 4 5 Power supply valtage V DD [V] 54 6 7 µPD75328 I DD vs V DD (Ceramic oscillation: 2.00 MHz) (Ta= 25˚C) 5000 High-speed mode PCC=0011 Middle-speed mode PCC=0010 Low-speed mode PCC=0000 1000 Main system clock HALT mode Power supply current I DD [ µ A] 500 Main system clock STOP mode + Subsystem clock operation mode 100 50 Main system clock STOP mode + 32 kHz oscillation only or subsystem clock HALT mode X1 10 5 30 pF X2 XT1 XT2 Ceramic oscillator CSA2.00MG Crystal 32.768 kHz 330 kΩ 30 pF 22 pF 22 pF V DD V DD 2 0 1 2 3 4 5 6 7 Power supply valtage V DD [V] 55 µPD75328 IDD vs fX I DD vs fX (V DD = 5 V, Ta = 25˚C) 3 X1 0.5 External clock High-speed mode PCC = 0011 (V DD = 3 V, Ta = 25˚C) 0.6 X2 High-speed mode PCC = 0011 Middle-speed mode PCC = 0010 X1 X2 External clock 0.4 Low-speed mode PCC = 0000 2 Middle-speed mode PCC = 0010 I DD [mA] I DD [mA] 0.3 0.2 Main system clock HALT mode 1 0.1 Low-speed mode PCC = 0000 0 1 2 Main system clock HALT mode 0 1 2 3 f X [MHz] 4 4 5 5 VOL vs IOL (PORT 0, 2, 6, 7, 8) VOL vs IOL (PORT 3, 4, 5) (Ta = 25˚C) 40 3 f X [MHz] (Ta = 25˚C) 40 V DD = 6 V 30 V DD = 6 V V DD = 5 V V DD = 4 V 30 V DD = 4 V V DD = 5 V I OL [mA] I OL [mA] 20 20 V DD = 3 V V DD = 3 V V DD = 2.7 V V DD = 2.7 V 10 0 10 1 2 3 V OL [V] 56 4 5 0 1 2 3 V OL [V] 4 5 µPD75328 VOH vs IOH (Except for P83) (Ta = 25˚C) 20 15 VOH vs IOH (P83) V DD = 6 V 15 V DD = 5 V (Ta = 25˚C) 20 V DD = 6 V V DD = 5 V V DD = 4 V V DD = 3.5 V V DD = 3 V V DD = 4 V I OH 10 [mA] I OH 10 [mA] V DD = 2.7 V V DD = 3 V 5 0 5 V DD = 2.7 V 1 2 V DD 3 – V OH [V] 4 5 0 1 2 3 V DD – V OH [V] 4 5 57 µPD75328 VOL vs IOL (BP0-3, BP4-7) VOH vs IOH (BP0-3, BP4-7) (V DD = 5 V, Ta = 25˚C) 800 Number of simultaneous output* : 1 700 (V DD = 5 V, Ta = 25˚C) –600 Number of simultaneous output : 1 –500 600 –400 500 I OH [ µ A] –300 2 2 3 I OL [ µ A] 400 –200 4 3 300 –100 4 200 0 1 2 3 V DD – V OH [V] 4 100 0 1 2 3 4 5 V OL [V] * Of pins BP0-BP3 and BP4-BP7, for each, the number of pins simultaneously outputting the same level. VOL vs IOL (BP0-3, BP4-7) 250 VOH vs IOH (BP0-3, BP4-7) (V DD = 3 V, T a = 25˚C) (V DD = 3 V, T a = 25˚C) –200 Number of simultaneous output* : 1 Number of simultaneous output : 1 200 –150 150 2 I OH [ µ A] –100 2 I OL [ µ A] 3 4 3 100 –50 4 0 50 0 1 2 V OL [V] 58 3 1 2 V DD – V OH [V] 3 5 µPD75328 12. PACKAGE DRAWINGS 80 PIN PLASTIC QFP ( 14) A B 41 40 60 61 Q 5°±5° S C D detail of lead end 21 20 F 80 1 G H I M J M P K N L S80GC-65-3B9-3 NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 17.2 ± 0.4 0.677 ± 0.016 B 14.0 ± 0.2 0.551+0.009 –0.008 C 14.0 ± 0.2 0.551+0.009 –0.008 D 17.2 ± 0.4 0.677 ± 0.016 F 0.8 0.031 G 0.8 0.031 H 0.30 ± 0.10 0.012+0.004 –0.005 I 0.13 0.005 J 0.65 (T.P.) 0.026 (T.P.) K 1.6 ± 0.2 0.063 ± 0.008 L 0.8 ± 0.2 0.031+0.009 –0.008 M 0.15+0.10 –0.05 0.006+0.004 –0.003 N 0.10 0.004 P 2.7 0.106 Q 0.1 ± 0.1 0.004 ± 0.004 S 3.0 MAX. 0.119 MAX. 59 µPD75328 ★ 13. RECOMMENDED SOLDERING CONDITIONS It is recommended that µ PD75328 be soldered under the following conditions. For details on the recommended soldering conditions, refer to Information Document "Semiconductor Devices Mounting Manual" (IEI-616). The soldering methods and conditions are not listed here, consult NEC. Table 13-1 Soldering Conditions µPD75328GC - xxx - 3B9: 80-pin plastic QFP (■ ■ 14 mm) Soldering Method *: Soldering Conditions Symbol for Recommended Condition Wave Soldering Soldering bath temperature: 260°C max., time: 10 seconds max., number of times: 1, pre-heating temperature: 120°C max. (package surface temperature), maximum number of days: 2 days*, (beyond this period, 16 hours of pre-baking is required at 125°C). WS60-162-1 Infrared Reflow Package peak temperature: 230°C, time: 30 seconds max. (210°C min.), number of times: 1, maximum number of days: 2 days* (beyond this period, 16 hours of pre-baking is required at 125°C) IR30-162-1 VPS Reflow Package peak temperature: 215°C, time: 40 seconds max. (200°C min.), number of times: 1, maximum number of days: 2 days* (beyond this period, 16 hours of pre-baking is required at 125°C) VP15-162-1 Pin Partial Heating Pin temperature: 300°C max., time: 3 seconds max. (per side) — Number of days after unpacking the dry pack. Storage conditions are 25°C and 65%RH max. Caution: Do not use two or more soldering methods in combination (except the pin partial heating method). Notice A model that can be soldered under the more stringent conditions (infrared reflow peak temperature: 235°C, number of times: 2, and an extended number of days) is also available. For details, consult NEC. 61 µPD75328 APPENDIX A. COMPARISON OF FEATURES BETWEEN µPD75328 AND µPD75308 Name µPD75328 µPD75308 Item ROM (Bytes) 8064 RAM (× 4 Bits) 512 General-Purpose Register • 4-bit manipulation: 8 × 4 banks • 8-bit manipulation: 4 × 4 banks Instruction Cycle Selectable from 0.95 µs, 1.91 µs, 15.3 ms (main system clock: operating at 4.19 MHz) and 122 µs (subsystem clock: operating at 32.768 kHz) Input/ Output Port COMS Input 8 (shared with INT, SI, SO) CMOS Input/ Output 20 (4 lines can directly drive LED) CMOS Output N-ch Input/ Output 36 (44 max.) 4/8 (shared with segment output, can be selected using software) 32 (40 max.) 8 (can directly drive LED, can be sustain with 10 V, and can be pulled up by mask option) 16 (4 lines can directly drive LED) 8 (can directly drive LED, can be sustain with 10 V, and can be pulled up by mask option) • Timer/event counter • Basic interval timer • Watch timer Serial Interface • Built-in NEC-standard serial bus interface (SBI) • Normal clock synchronized serial interface is also possible A/D Converter 6-channel analog input, 8-bit resolution Vector Interrupt External: 3, internal: 3 — External: 1, internal: 1 Instruction Set • Bit data set/reset/test/boolean operation • 4-bit data transfer/arithmetic/increment/decrement/comparison • 8-bit data transfer Display Function LCD controller • Segment outputs: 20 (4/8 can be set for output port by using software) • Common outputs: 4 • Display mode (static, 1/2, 1/3, 1/4) • Built-in step-down resistor network for LCD drive voltage supply (mask option) Operating Voltage Package Can be pulled up using software, except for P00 4/8 (shared with segment output, can be selected using software) Timer/Counter Test Input 62 8 (shared with INT, SI, SO) Can be pulled up using software, except for P00 LCD controller • Segment outputs: 32 (4/8 can be set for output port by using software) • Common outputs: 4 • Display mode (static, 1/2, 1/3, 1/4) • Built-in step-down resistor network for LCD drive voltage supply (mask option) 2.7 to 6.0 V 80-pin plastic QFP ( 14mm) 80-pin plastic QFP (14×20 mm) µPD75328 ★ APPENDIX B. DEVELOPMENT TOOLS Name The following development support tools are readily available to support development of systems µPD75328 µPD75308 Item using µPD75328: ROM (Bytes) 8064 RAMPROM (× 4 Bits) 512 writing tools General-Purpose • 4-bit manipulation: 8 × 4 banks Register • 8-bit manipulation: 4 × 4 banks Hardware IE-75000-R *1 In-circuit emulator for 75X series Instruction Cycle IE-75001-R Selectable from 0.95 µs, 1.91 µs, 15.3 µs (main system clock: operating at 4.19 MHz) and 122 µs (subsystem clock: operating at for 32.768 kHz) IE-75000-R-EM *2 Emulation board IE-75000-R and IE-75001-R Input/ Output Port COMS EP-75328GC-R 8 (shared with (shared with Emulation prove for µPD75328GC,8provided with 80-pin conversion socket Input INT, SI, SO) EV-9200GC-80. INT, SI, SO) EV-9200GC-80 CMOS 20 (4 lines can 16 (4 lines can PG-1500 PROM programmer Input/ directly drive directly drive PROM programmer adapter solelyLED) used for µPD75P328GC. It is connected Output PA-75P328GC LED) to PG-1500. CMOS 4/8 (shared with segment output, 4/8 (shared with segment output, Hostusing machine Software Output IE Control Program can be selected software) can be selected using software) • PC-9800 series (MS-DOSTM Ver.3.30 to Ver.5.00A* 3) N-ch 8 (can directly drive LED, can be 8 (can directly drive LED, can be TM (PC DOSTM Ver.3.1)sustain with 10 V, and can be PC/AT Input/ PG-1500 Controller sustain with •10IBM V, and can be Output RA75X Relocatable pulled up by mask option) pulled up by mask option) Assembler • Timer/event counter • Basic interval timer • Watch timer *1: Maintenance product Timer/Counter Serial Interface • Built-in 2: Not provided with NEC-standard IE-75001-R. serial bus interface (SBI) • Normal clock synchronized serial interface is also possible 3: Ver.5.00/5.00A has a task swap function, but this function cannot be used with this software. A/D Converter 6-channel analog input, 8-bit resolution Vector Interrupt External: 3, internal: 3 — Remarks: For development tools from other companies, refer to 75X Series Selection Guide (IF-151). Test Input External: 1, internal: 1 Instruction Set • Bit data set/reset/test/boolean operation • 4-bit data transfer/arithmetic/increment/decrement/comparison • 8-bit data transfer Display Function LCD controller • Segment outputs: 20 (4/8 can be set for output port by using software) • Common outputs: 4 • Display mode (static, 1/2, 1/3, 1/4) • Built-in step-down resistor network for LCD LCD controller • Segment outputs: 32 (4/8 can be set for output port by using software) • Common outputs: 4 • Display mode (static, 1/2, 1/3, 1/4) • Built-in step-down resistor network for LCD drive voltage supply (mask option) Operating Voltage Package 62 drive voltage supply (mask option) 2.7 to 6.0 V 80-pin plastic QFP ( 63 µPD75328 ★ APPENDIX C. RELATED DOCUMENTS 64 µPD75328 GENERAL NOTES ON CMOS DEVICES 1 STATIC ELECTRICITY (ALL MOS DEVICES) Exercise care so that MOS devices are not adversely influenced by static electricity while being handled. The insulation of the gates of the MOS device may be destroyed by a strong static charge. Therefore, when transporting or storing the MOS device, use a conductive tray, magazine case, or conductive buffer materials, or the metal case NEC uses for packaging and shipment, and use grounding when assembling the MOS device system. Do not leave the MOS device on a plastic plate and do not touch the pins of the device. Handle boards on which MOS devices are mounted similarly . 2 PROCESSING OF UNUSED PINS (CMOS DEVICES ONLY) Fix the input level of CMOS devices. Unlike bipolar or NMOS devices, if a CMOS device is operated with nothing connected to its input pin, intermediate level input may be generated due to noise, and an inrush current may flow through the device, causing the device to malfunction. Therefore, fix the input level of the device by using a pull-down or pull-up resistor. If there is a possibility that an unused pin serves as an output pin (whose timing is not specified), each pin should be connected to VDD or GND through a resistor. Refer to “Processing of Unused Pins” in the documents of each devices. 3 STATUS BEFORE INITIALIZATION (ALL MOS DEVICES) The initial status of MOS devices is undefined upon power application. Since the characteristics of an MOS device are determined by the quantity of injection at the molecular level, the initial status of the device is not controlled during the production process. The output status of pins, I/O setting, and register contents upon power application are not guaranteed. However, the items defined for reset operation and mode setting are subject to guarantee after the respective operations have been executed. When using a device with a reset function, be sure to reset the device after power application. 65 µPD75328 [MEMO] No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties b y or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for uses in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for the applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime system, etc. M4 92.6 MS-DOS is a trademark of Microsoft Corporation. PC DOS and PC/AT are trademarks of IBM Corporation. 66