CXD2027Q/R
DBS Audio Signal Processor
For the availability of this product, please contact the sales office.
Description
The CXD2027Q/R are audio signal processors
designed for DBS applications. These LSIs perform
all digital processing from QPSK demodulation to
analog audio output on a single chip.
CXD2027Q
64 pin QFP (Plastic)
CXD2027R
80 pin LQFP (Plastic)
Features
QPSK and PCM demodulators and DAC output
are configured on a single chip.
Descrambler interface according to the COATEC
system and SkyPort system .
Functions
QPSK demodulator
• Carrier, clock and data regeneration
• ALC and VCXO adjustment-free
PCM demodulator
• Frame sync protection by correlation detection
• De-interleaving and descrambling
• BCH error correction, range bit error correction
• Audio data range control
Expansion from 10 to 14 bits in A mode
Upper bit majority correction in B mode
• Control sign integration correction, chargeable
flag integration correction by master frame
synchronization
• Interface output for external DAC
• Digital interface output
1-bit DAC output
• Quadruple oversampling filter
• Digital de-emphasis circuit
• 1-bit stereo DAC with 2nd-order ∆∑ format noise
shaper
S/N ratio : 90dB (Typ.)
Distortion : 0.011% (Typ.)
CPU interface
• I2C bus
Descrambler interface
• COATEC system, SkyPort system
Mute functions
• Error occurrence frequency detection mute
• Audio chargeable flag detection mute
• Control sign (B7) detection mute
Structure
Silicon gate CMOS IC
Applications
TVs, VCRs with built-in BS tuners
Absolute Maximum Ratings (Ta = 25°C, Vss = 0V)
• Supply voltage
VDD Vss – 0.5 to +7.0 V
• Input voltage
VI Vss – 0.5 to VDD + 0.5 V
• Output voltage
VO Vss – 0.5 to VDD + 0.5 V
• Storage temperature Tstg
–55 to +150
°C
Operating Conditions
• Supply voltage
VDD
• Operating temperature Topr
4.75 to 5.25
–20 to +75
V
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E94808-ST
–2–
66
65
64
58
57
M23I
M23O
PHAB
MCKI
67
PHAA
ALCO
GR 77
15
38
51
SCLK
50
SDA
47
DTUP
14
CC1
11
I2C BUS I/F
MAJORITY
ERROR
CORRECTION
BCH DECODER
(63, 56)
9
13
DIGITAL FILTER
DE-ENPHASIS
CLOCK GENERATOR
DIGITAL
INTERFACE
10 → 14 BIT
DATA EXPAND
DE-SCRAMBLER
AUDIO DATA
INTERPOLATOR
8TH RANGE BIT
INTEGRAL
CORRECTION
DE-INTERLEAVER
4 kBIT-RAM
FRAME SYNC
SASL
CK2M
12
TIMING
GENERATOR
SYSTEM CLOCK
GENERATOR
CONTROL WORD
INTEGRAL
CORRECTION
MASTER FRAME
SYNC
DATA
RECOVERY
7
TX
FRAM
56
CLOCK
RECOVERY
CARRIER
RECOVERY
ALC SIGNAL
GENERATOR
BITO
RB 76
ADC
DSLB
73
NSYN
48
DATO
ADIN
5
DATA
71
BITI
6
DSLA
4
AUDIO
INTERFACE
DAC2
DAC1
MUTE SIGNAL
GENERATOR
SHIFTER
&
RANGE BIT
BCH (7, 3)
RNO
LRCK
46 F256
45 BCLK
44
43 AUD
35
32 RPO
25 LNO
28 LPO
54 MUTE
Note) Pin numbers are for the CXD2027R.
8
DATB
RT
Block Diagram
CXD2027Q/R
MCKO
CXD2027Q/R
SASL
TST6
AUD
LRCK
BCLK
DTUP
F256
NSYN
VDD3
SDA
SCLK
VSS7
TST8
MUTE
VSS8
MCKO
MCKI
PHAB
VDD4
Pin Configuration 1
CXD2027Q
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VDD5
52
32
VSS6
M23O
53
31
VSS5
M23I
54
30
RNO
PHAA
55
29
VDD2
ALCO
56
28
RPO
VSS9
57
27
VSS4
TST7
58
26
TST1
23
VDD1
ADVS
62
22
LNO
RB
63
21
VSS2
GR
64
20
VSS1
–3–
TST5
TST4
9 10 11 12 13 14 15 16 17 18 19
TST3
8
TST2
7
TX
6
CC1
5
DATO
4
FRAM
3
CK2M
2
VDD0
1
DATA
61
DSLA
ADVD
DATB
LPO
BITI
24
DSLB
60
BITO
VSS3
VSS0
25
MRST
59
TST0
RT
ADIN
CXD2027Q/R
N.C.
TST6
AUD
LRCK
BCLK
DTUP
F256
NSYN
VDD3
SDA
SCLK
VSS7
TST8
MUTE
VSS8
MCKO
MCKI
PHAB
VDD4
N.C.
Pin Configuration 2
CXD2027R
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
N.C.
61
40
N.C.
N.C.
62
39
N.C.
VDD5
63
38
SASL
M23O
64
37
VSS6
M23I
65
36
VSS5
PHAA
66
35
RNO
ALCO
67
34
N.C.
VSS9
68
33
VDD2
N.C.
69
32
RPO
TST7
70
31
VSS4
RT
71
30
TST1
N.C.
72
29
VSS3
ADIN
73
28
LPO
ADVD
74
27
VDD1
ADVS
75
26
N.C.
79
22
N.C.
N.C.
80
21
N.C.
–4–
N.C.
TST5
TST4
9 10 11 12 13 14 15 16 17 18 19 20
TST3
8
TST2
7
TX
6
CC1
5
DATO
4
CK2M
3
FRAM
2
VDD0
1
DATA
N.C.
DATB
VSS1
DSLA
VSS2
23
DSLB
24
78
BITI
77
TST0
VSS0
LNO
BITO
25
N.C.
76
MRST
RB
GR
CXD2027Q/R
Pin Description 1
CXD2027Q (64pin QFP)
Pin
No.
Symbol
I/O
Pin Description
Remarks
1
TST0
I
Test pin; normally low
2
MRST
I
Master reset; H: normal operation; L: reset
3
VSS Digital
—
Digital ground
4
BITO
O
Bit stream output after PSK demodulation
5
BITI
I
Bit stream input after PSK demodulation
TTL input
6
DSLB
I
External descrambler pin
TTL input
7
DSLA
I
External descrambler pin
TTL input
8
DATB
I
Data input 2 after BCH correction (for COATEC)
TTL input
9
DATA
I
Data input 1 after BCH correction (for SkyPort)
TTL input
10
VDD Digital
—
Digital +5V power supply
11
CK2M
O
2.048MHz clock output
12
FRAM
O
Frame start bit flag
13
DATO
O
Data output after BCH correction
14
CC1
O
Control sign first bit output
15
TX
O
Digital format audio output
16
TST2
I
Test pin; normally low
Internal pull down
17
TST3
I
Test pin; normally low
Internal pull down
18
TST4
I
Test pin; normally low
Internal pull down
19
TST5
I
Test pin; normally high
20
VSS Digital
—
Digital ground
21
VSS D/A
—
Analog ground
22
LNO
O
Lch D/A converter output
23
VDD D/A
—
Analog +5V power supply
24
LPO
O
Lch D/A converter output
25
VSS D/A
—
Analog ground
26
TST1
I
27
VSS D/A
—
Analog ground
28
RPO
O
Rch D/A converter output
29
VDD D/A
—
Analog +5V power supply
30
RNO
O
Rch D/A converter output
31
VSS D/A
—
Analog ground
32
VSS Digital
—
Digital ground
33
SASL
I
I2C bus slave address select (L: D4, H: D6)
Internal pull down
34
TST6
I
Test pin; normally low
Internal pull down
Internal pull down
Test pin; normally low
Internal pull up
Internal pull down
–5–
CXD2027Q/R
Pin
No.
Symbol
I/O
Pin Description
Remarks
35
AUD
O
Audio data output for external DF/DAC
36
LRCK
O
LR clock output for external DF/DAC
37
BCLK
O
Bit clock output for external DF/DAC
38
F256
O
Clock output for external DF/DAC
39
DTUP
O
CCUP: control sign update flag / DED: BCH 2 error detection
40
NSYN
O
Asynchronous flag (H: asynchronous; L: synchronous)
41
VDD Digital
—
Digital +5V power supply
42
SDA
I
SDA (I2C bus)
I2C bus compatible
43
SCLK
I
SCL (I2C bus)
I2C bus compatible
44
VSS Digital
—
Digital ground
45
TST8
I
Test pin; normally low
46
MUTE
I
External forced muting input
47
VSS Digital
—
Digital ground
48
MCKO
O
MCKI inversion output
49
MCKI
I
24.576MHz clock input
50
PHAB
O
Clock regeneration phase error data output
51
VDD Digital
—
Digital +5V power supply
52
VDD Digital
—
Digital +5V power supply
53
M23O
O
M23I inversion output
54
M23I
I
22.909088MHz clock input
55
PHAA
O
Carrier regeneration phase error data output
56
ALCO
O
ALC A/D control output
57
VSS Digital
—
Digital ground
58
TST7
I
Test pin; normally low
59
RT
I
A/D converter VRT input
60
ADIN
I
Analog data input
61
VDD A/D
—
Analog +5V power supply
62
VSS A/D
—
Analog ground
63
RB
I
A/D converter VRB input; connect to analog ground
64
GR
I
A/D converter VGR input; connect to analog ground
–6–
Switched by I2C bus
TTL input
CXD2027Q/R
Pin Description 2
CXD2027R (80pin LQFP)
Pin
No.
Symbol
I/O
Pin Description
Remarks
Non-connection
1
N.C.
2
MRST
3
VSS Digital
—
Digital ground
4
BITO
O
Bit stream output after PSK demodulation
5
BITI
I
Bit stream input after PSK demodulation
TTL input
6
DSLB
I
External descrambler pin
TTL input
7
DSLA
I
External descrambler pin
TTL input
8
DATB
I
Data input 2 after BCH correction (for COATEC)
TTL input
9
DATA
I
Data input 1 after BCH correction (for SkyPort)
TTL input
10
VDD Digital
—
Digital +5V power supply
11
CK2M
O
2.048MHz clock output
12
FRAM
O
Frame start bit flag
13
DATO
O
Data output after BCH correction
14
CC1
O
Control sign first bit output
15
TX
O
Digital format audio output
16
TST2
I
Test pin; normally low
Internal pull down
17
TST3
I
Test pin; normally low
Internal pull down
18
TST4
I
Test pin; normally low
Internal pull down
19
TST5
I
Test pin; normally high
20
N.C.
—
Non-connection
21
N.C.
—
Non-connection
22
N.C.
—
Non-connection
23
VSS Digital
—
Digital ground
24
VSS D/A
—
Analog ground
25
LNO
O
Lch DAC output
26
N.C.
—
Non-connection
27
VDD D/A
—
Analog +5V power supply
28
LPO
O
Lch DAC output
29
VSS D/A
—
Analog ground
30
TST1
31
VSS D/A
—
Analog ground
32
RPO
O
Rch DAC output
33
VDD D/A
—
Analog +5V power supply
34
N.C.
—
Non-connection
—
I
I
Master reset; H: normal operation; L: reset
Internal pull up
Internal pull down
Test pin; normally low
–7–
CXD2027Q/R
Pin
No.
Symbol
I/O
Pin Description
Remarks
35
RNO
O
Rch D/A converter output
36
VSS D/A
—
Analog ground
37
VSS Digital
—
Digital ground
38
SASL
I
39
N.C.
—
Non-connection
40
N.C.
—
Non-connection
41
N.C.
—
Non-connection
42
TST6
I
Test pin; normally low
43
AUD
O
Audio data output for external DF/DAC
44
LRCK
O
LR clock output for external DF/DAC
45
BCLK
O
Bit clock output for external DF/DAC
46
F256
O
Clock output for external DF/DAC
47
DTUP
O
CCUP: control sign update flag/DED: BCH 2 error detection
48
NSYN
O
Asynchronous flag (H: asynchronous; L: synchronous)
49
VDD Digital
—
Digital +5V power supply
50
SDA
I
SDA (I2C bus)
I2C bus compatible
51
SCLK
I
SCL (I2C bus)
I2C bus compatible
52
VSS Digital
—
Digital ground
53
TST8
I
Test pin; normally low
54
MUTE
I
External forced muting input
55
VSS Digital
—
Digital ground
56
MCKO
O
MCKI inversion output
57
MCKI
I
24.576MHz clock input
58
PHAB
O
Clock regeneration phase error data output
59
VDD Digital
—
Digital +5V power supply
60
N.C.
—
Non-connection
61
N.C.
—
Non-connection
62
N.C.
—
Non-connection
63
VDD Digital
—
Digital +5V power supply
64
M23O
O
M23I inversion output
65
M23I
I
22.909088MHz clock input
66
PHAA
O
Carrier regeneration phase error data output
67
ALCO
O
ALC A/D control output
68
VSS Digital
—
Digital ground
69
N.C.
—
Non-connection
70
TST7
I
I2C bus slave address select (L: D4, H: D6)
Internal pull down
Internal pull down
Test pin; normally low
–8–
Switched by I2C bus
TTL input
CXD2027Q/R
Pin
No.
Symbol
I/O
I
Description
Remarks
71
RT
A/D converter VRT input
72
N.C.
—
73
ADIN
I
74
VDD A/D
—
Analog +5V power supply
75
VSS A/D
—
Analog ground
76
RB
I
A/D converter VRB input; connect to analog ground
77
GR
I
A/D converter VGR input; connect to analog ground
78
TST0
I
A/D test pin; normally low
79
N.C.
—
Non-connection
80
N.C.
—
Non-connection
Non-connection
Analog data input
Absolute Maximum Ratings
Item
Internal pull down
(Ta = 25°C, Vss = 0V)
Symbol
Ratings
Unit
Vss – 0.5 to +7.0
V
Supply voltage
VDD
Input voltage
VI
Vss – 0.5 to VDD + 0.5
V
Output voltage
VO
Vss – 0.5 to VDD + 0.5
V
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +150
°C
I/O Pin Capacitance
Item
Input pin capacitance
(VDD = VI = 0V, f = 1MHz)
Symbol
Min.
Typ.
CIN
Max.
Unit
Corresponding pins
9
∗1
10
∗2
11
pF
∗3
Output pin capacitance
COUT
11
∗4
Input/output pin capacitance
CI/O
10
∗5
∗1 Input pins other than ∗2 and ∗3
∗2 SCLK
∗3 BITI, DSLB, DSLA, DATB, DATA, TST5
∗4 All output pins
∗5 SDA
–9–
CXD2027Q/R
Electrical Characteristics
[DC characteristics]
Item
(VDD = 5V ± 0.25V, Vss = 0V, Ta = –20 to +75°C)
Measurement
conditions
Min.
Typ.
Max.
Unit
VDD = 4.75 to 5.25V
180
280
350
mW
VDD
V
Symbol
Power consumption
PD
Input/output voltage
VI, VO
Vss
VIH
CMOS input
0.7VDD
TTL input
0.3VDD
Vt+
Low level
Vt–
Hysteresis voltage
Vt+ – Vt–
Input rise/fall time
Output voltage
2.2
∗3
VIL
High level
∗1
∗2
VIL
VIH
Input
voltage
Corresponding
pins
0.8
V
0.7VDD
∗4
0.3VDD
0.5
tr, tf
0
500
VOH
IOH = –2mA
VOL
IOL = 4mA
VOH
IOH = –4mA
VOL
IOL = 4mA
VOH
IOH = –4mA
VOL
IOL = 8mA
VOL
IOL = 3mA
0
0.4
VOL
IOL = 6mA
0
0.6
ns
VDD – 0.8
∗5
∗6
0.4
VDD – 0.8
∗7
0.4
VDD – 0.8
V
∗8
0.4
∗1 All pins
∗2 Input pins other than ∗3 and ∗4
∗3 BITI, DSLB, DSLA, DATB, DATA, MUTE
∗4 SDA, SCLK
∗5 All input pins
∗6 Output pins other than ∗7, ∗8 and ∗9
∗7 LNO, LPO, RPO, RNO
∗8 BITO, CK2M, FRAM, DATO, CCI, TX
∗9 SDA, SCLK
– 10 –
∗9
CXD2027Q/R
Item
Input
leak
current
Measurement
conditions
Min.
Typ.
Max.
Unit
10
µA
Corresponding
pins
∗1
Normal input pin
II
VIN = VSS or VDD
–10
With pull-up
resistor
IIL
VIN = VSS
–40
–100
–240
µA
∗2
With pull-down
resistor
IIH
VIN = VDD
40
100
240
µA
∗3
Bidirectional pin
(during input state)
II
VIN = VSS or VDD
–40
40
µA
∗4
IOZ
VIN = VSS
–10
–10
µA
∗5
Output leak current
(I2C bus)
∗1
∗2
∗3
∗4
∗5
Symbol
Input pins other than ∗2, ∗3 and ∗4
MRST
TST0, TST1, TST2, TST3, TST4, SASL, TST6
BITI, DSLB, DSLA, DATB, DATA, TST5
SDA, SCLK
[Oscillation cell electrical characteristics]
Item
Logic threshold value
Input voltage
Feedback resistance
Output voltage
Symbol
(VDD = 5V ± 0.25V, Ta = –20 to +75°C)
Measurement
conditions
Min.
LVth
Typ.
Max.
VDD/2
VIH
V
VIL
VIN = VSS or VDD
250k
VOH
IOH = –12mA
VDD/2
VOL
IOL = 12mA
∗6 MCKI, M23I
∗7 MCKI, MCKO, M23I, M23O
∗8 MCKO, M23O
– 11 –
1M
Corresponding
pins
V
0.7VDD
RFB
Unit
0.3VDD
V
2.5M
Ω
VDD/2
V
∗6
∗7
∗8
CXD2027Q/R
[Internal A/D converter characteristics]
Absolute Maximum Ratings
(Ta = 25°C)
Symbol
Item
Ratings
Unit
Supply voltage
AVD
+7.0
V
Input voltage (analog)
AIN
AVD to AVS
V
VDD to VSS
V
AVD to AVS
V
Ratings
Unit
4.75 to 5.25
V
Input voltage (digital)
Reference voltage
RB, RT
Operating Conditions
Item
Supply voltage
Symbol
AVD, AVS
l DVS – AVS l
0 to 100
Reference input
voltage
RB
0 to
Analog input
AIN
RT
to 3.75
Amplitude
DC level
Operating ambient
temperature
Topr
mV
V
100 to 300
(typ. 200)
typ.1.25
mVp-p
–20 to +75
°C
– 12 –
V
CXD2027Q/R
[AC characteristics]
(VDD = 5.0V ± 0.25V, Ta = 25°C)
Item
ALC characteristics
Carrier
regeneration
PLL pull-in range
Clock
regeneration
PLL pull-in range
Conditions
Min.
Deviation from standard input level 200mVp-p
Pull-in frequency∗ relative to 5.7272MHz.
Includes temperature characteristics (–20 to +75°C)
and supply voltage fluctuation (±5%) of VCXO.
Pull-in frequency∗ relative to 2.048MHz.
Includes temperature characteristics (–20 to +75°C)
and supply voltage fluctuation (±5%) of VCXO.
Typ.
Max.
Unit
±50
%
Upper +750
Hz
Lower –450
Upper +300
Hz
Lower –100
∗ Performance guaranteed only when using constants of the recommended oscillation circuit.
22.909088MHz (for carrier regeneration PLL) VCXO circuit
PHAA
M23I
M23O
100K
2.7µ
68
4.7K
12p (UJ)
390p (CH)
22K
HVU359
0.01µ
X'tal : Daishinku AG8865C
VC : Hitachi HVU359
L
: Matsushita ELJ-FC series
24.576MHz (for clock regeneration PLL) VCXO circuit
PHAB
MCKI
MCKO
100K
330
4.7K
1800p (CH)
10p (UJ)
22K
0.047µ
HVU359
X'tal : Daishinku AG8865C
VC : Hitachi HVU359
– 13 –
CXD2027Q/R
(VDD = 5.0V ± 0.25V, Ta = –20 to +75°C, CL = 60pF)
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
BITI set-up time
DATA set-up time
tsu1
Value relative to CK2M fall
32
ns
th1
Value relative to CK2M fall
0
ns
DATB set-up time
BITI hold time
DATA hold time
DATB hold time
(VDD = 5.0V ± 0.25V, Ta = –20 to +75°C, CL = 60pF)
Item
Symbol
td1
td2
td3
BITO delay time
DATO delay time
NSYN delay time
td4
td5
td6
td7
td8
FRAM delay time
DTUP delay time
CC1 delay time
AUD delay time
LRCK delay time
BITI, DATA, DATB
Conditions
Value relative to CK2M fall
Value relative to BCLK fall
AAAAA
tsu1
th1
CK2M
CK2M
AA
AA
AA
AA
td1 to td6
BITO, DATO, NSYN,
FRAM, DTUP, CC1
BCLK
td7 to td8
AUD, LRCK
– 14 –
Min.
Typ.
Max.
Unit
17
ns
24
ns
37
ns
23
ns
38
ns
21
ns
28
ns
26
ns
CXD2027Q/R
Internal 1-bit DAC analog characteristics
(fs = 48kHz, VDD = 5.0V, Ta = 25°C, signal frequency = 1kHz, measurement band = 4Hz to 20kHz, B mode)
Item
Min.
Typ.
S/N
Max.
Unit
Remarks
(EIAJ) ∗1
90
dB
THD + N
0.011
%
Output level
1.95
V(rms)
(EIAJ)
∗2
∗1 "A" characteristic weighting filter used
∗2 When master clock is 256fs
The following circuit is used for analog characteristics measurement.
820p
CXD2027Q/R
5.4k
130k
4.7k
0.015
LNO (RNO)
4.7k
47p
4.7k
4.7k
4.7k
820p
1800p
820p
130k
LPO (RPO)
47p
Lch
DATA
TEST DISC
22
100
5.4k
CXD2027Q/R
Rch
ANALOG
ANALOG
CIRCUIT
– 15 –
ANALOG TESTER
(ADVANTEST T7342)
12k
OUTPUT
CXD2027Q/R
Description of Functions
• ALC
This detects the fluctuation of the input QPSK modulated signal level and absorbs the fluctuation by
controlling A/D VRT. With this function, a signal is output from ALCO after PWM modulation, and should be
fed back to the RT pin after integration.
• Carrier regeneration
A 5.727272MHz carrier is regenerated.
The input QPSK modulated signal is A/D converted at a sample rate of 22.909088MHz (5.727272MHz × 4),
and control voltage is generated using that sampling position as phase error data. The control voltage is
output from the PHAA pin after PWM modulation, and controls VCXO, which consists of an internal
oscillation cell and external crystal.
• Clock regeneration
This is a PLL circuit with 24.576MHz clock. It is 512 × fs, for use with the DAC.
Phase comparison is carried out using the regenerated I and Q signals and VCXO divided output, and
control voltage is generated. After PWM modulation, the control voltage is output from the PHAB pin, and
controls VCXO, which consists of an internal oscillation cell and external crystal.
• Data regeneration
A 2.048MHz bit stream is regenerated from the regenerated I and Q signals.
• Frame sync and master frame sync
Correlated detection and competitive counter format is used for sync protection. The number of rear
protection is set at three times, and that of front protection is set at 3, 5, 7, or 9 times.
Also, synchronizing to the master frame can be done when the master frame signal is being sent to the
control sign 14th bit. In this case, the number of rear protection is set to 2 times, and that of front protection
is set at 7, 9 or 11 times.
• Descramble
A superimposed PN signal is removed for BS.
Also, there is a built-in interface for an external descrambler unit.
• De-interleave
The data interleaved by the built-in 4kbit SRAM is returned to the correct data array.
• (63, 56) BCH sign error correction
This performs (63, 56) BCH sign error correction. Error capability is 1 error correction, 2 errors detection.
• Range bit BCH sign error correction
This performs (7, 3) BCH sign error correction. Error capability is 1 error correction, 2 errors detection.
When there are 2 errors, the previous value is held.
– 16 –
CXD2027Q/R
• Control sign integration detection and 8th range bit integration detection
Integration detection is carried out in units of 15 frames. When a match of 12/15 or more is obtained, a
defined control sign is detected. However, updating is every 18 frames.
When a match of 12/15 or more is not obtained, the previous value is held.
Further, synchronizing to the master frame can be done when the master frame signal is being sent to the
control sign 14th bit.
After integration detection, the control sign and range bit can be read by the I2C bus.
• 10 → 14 bit data expansion
During A mode, the instantaneously compressed 10 bits of audio data are expanded to 14 bits according to
the range expansion rule. The lower bits of data are fixed at a set value during expansion, and the data is
treated as 16 bits.
• Upper bit majority detection
During B mode, this carries out upper bit majority detection and protects the upper bits.
• Mute signal generation
This performs muting by the external MUTE signal and internal logic, and also generates a mute signal
according to the mute setting from the I2C bus.
• Audio data interpolation
This receives the bit error detection signal and interpolation indication signal from majority detection, and
then carries out the average value interpolation or the previous value hold.
• Clock generation for D/A converter
This generates the clock for the DAC.
• Digital filter (DF) and de-emphasis
A 2ch 1-bit DAC with 2nd-order ∆∑ format noise shaper of quadruple oversampling filter is built in.
The output format is differential.
De-emphasis function corresponding to the mode is also built in.
• Audio interface
One of the following three output formats can be selected.
1) SONY: bit clock 32 fs/ MSB first/ 16 bits (for built-in D/A converter)
2) IIS: SONY format 1 BCLK delay
3) Bit clock 64fs / MSB first / 16 bits rearward truncation
• Digital interface
Conforms to the following digital audio interface format: type II form I (for consumer digital audio equipment)
• I2C bus interface
Control by microcomputer is carried out by the I2C bus I/F.
The slave address can be switched by controlling SASL; for low: D4, for high: D6.
– 17 –
CXD2027Q/R
• Output channel selection
The output channels provided are analog output for built-in D/A converter Lch/Rch, one output system for
external D/A audio output and one for digital audio output. Channel selection can be done easily through
the I2C bus.
Unused channels can be suppressed using the I2C bus.
• Audio output selection
Mode selection can be carried out via the I2C bus.
• Zero cross muting
The I2C bus can be used for zero cross muting.
When a mute signal is input, muting is not carried out until zero cross conditions are satisfied for 1 frame.
If these conditions are not met for 1 frame, muting is forced at the next frame.
Zero cross mute cancel is performed in frame units.
The conditions for zero cross are a change in audio data MSB, or when audio data value is between 00ffh
and ff00h.
• Description of mute function
A signal is treated as a mute signal in the following cases:
1) when asynchronous
2) control sign 7th bit (non-broadcast flag) or 16th bit (audio suppression flag) is high
3) 8th range bit (audio chargeable flag) is high (however, only channel for high)
4) number of double error flags goes over a certain TH level (error frequency detection mute)
5) audio carrier (5.7272MHz) can not be detected
6) an I2C bus mute flag is up
7) for other than audio
1. Asynchronous flag mute
Muting is applied when an asynchronous state exists. Also, the number of front sync protection can be
changed among 3, 5, 7 or 9 times by the I2C bus, so the conditions for asynchronous flag muting can be
changed.
2. Muting by control sign 7th and 16th bits
The control sign 7th bit is a flag indicating broadcast or non-broadcast. If this bit is high, muting is
applied. Also, the I2C bus can be used so that this bit does not apply muting.
The control sign 16th bit audio suppression flag is used when broadcast channels are switched and
when transmission modes are switched. Both use the value after integration detection.
3. Chargeable flag detection mute
The 8th range bit indicates if audio data is for a chargeable broadcast or not. For a chargeable
broadcast, a flag ("H") goes up in that bit's position. When this bit is high, the broadcast is detected as
chargeable and muting is applied. Further, the I2C bus can be used for each channel so that this bit
does not apply muting. The value after every 18 frames of integration detection is used.
– 18 –
CXD2027Q/R
4. Error frequency detection mute
Muting is applied after BCH (63, 56) sign error correction is executed for every 64 data, when the
number of double error detection flags goes over a certain TH (threshold value) level during a certain
number of frames. Also, the I2C bus can be used so that muting is not applied. The setting values are
indicated below.
Number of frames: 128, 256, 512, 1024
Up to 32 double errors can be detected in one frame, so 1/16, 1/8, 1/4 and 1/2 of the maximum
detections for each frame number are set as the TH levels.
Therefore, there are 16 possible combinations, and the value is set by the I2C bus.
The TH level for muting cancel is half of the TH value when muting is applied; in other words, 1/32, 1/16,
1/8 and 1/4, respectively.
5. Carrier detection mute
When the BS broadcast audio carrier frequency of 5.7272MHz can not be detected by the PSK
demodulator unit, muting is applied. Also, the I2C bus can be used so that muting is not applied.
6. I2C bus muting
The I2C bus can apply forced muting to analog and AUD outputs. TX output is locked to analog output.
7. Muting other than audio
Muting is done for other than audio mode when the control sign 2nd and 3rd, or 4th and 5th bits are "H, H".
– 19 –
CXD2027Q/R
External descramble I/F circuit example
COATEC and SkyPort units can be connected simultaneously.
DASLC
CXD2027Q/R
BITO
BITI
DSLB
BSTMI
DATO
BSTMO
RGND
DATI
Unit connection
COATEC unit
DSLA
DSLB
0
0
Descramble format
COATEC, SkyPort ∗
0
1
SkyPort
1
0
COATEC
1
1
Internal
DATB
DSDO
I2C BUS
register
DATA
DATI
DSLA
DATO
DASL
SkyPort unit
∗ The COATEC unit and SkyPort unit can be connected simultaneously.
However, use the I2C bus to set DASLC at high when turning off the COATEC unit power supply.
– 20 –
CXD2027Q/R
Bit stream signal interface
CK2M
BITO is output at falling sync.
BITO
2048
1
2
3
4
2047 2048
1
2
Data interface after BCH error correction
CK2M
FRAM
DATO is output at falling sync.
DATO
2048
1
2
3
4
2047 2048
1
2
1ms
1 frame
Examples of error detection countermeasures for low C/N control sign and chargeable flag integration
detection
When C/N is low, NSYN frequently goes high level (asynchronous state).
In this case, problems such as wrong display or wrong detection of control sign 7th bit "broadcast/nonbroadcast" flag may occur due to incorrect integration detection. This can be improved using the
microcomputer software shown below.
Integration detection result can be updated only when NSYN is low level. Detection results of this IC are read
by the standard trigger of the microcomputer, and if the result values match for 5 to 6 times continuously, the
detection result is taken as an update for the system. It is also possible to update the integration detection
result by the continuous matching of 7 times or more. However, standard trigger cycle of the microcomputer
must be set about 18ms.
NSYN
Control sign,Chargeable flag
(IC)
Control sign,Chargeable flag
(microcomputer)
→ integration detection results
Standard trigger
(microcomputer)
1
18ms
– 21 –
2
3
4
5
6
CXD2027Q/R
Description of I2C bus
The I2C bus is a bidirectional serial bus system developed by Philips. It can transmit and receive data
between multiple devices using two lines, SCLK (Serial Clock) and SDA (Serial Data).
This LSI has a built-in I2C bus interface circuit and is compatible with slave RECEIVER and slave
TRANSMITTER operation modes.
For the transfer configuration, both RECEIVER mode and TRANSMITTER mode have sub-addresses.
RECEIVER mode
The first byte is the slave address, the second byte is the sub-address, and data is read at the third byte
and after. Continuous data reading is also possible. After transmission of the first byte, the sub-address
is made (+1) automatically.
TRANSMITTER mode
The first byte is the slave address, and data is sent at the second byte and after. Continuous data output
is also possible. After transmission of the first byte, the sub-address is made (+1) automatically.
When there is no verification answer from the master, the SDA line is released.
To read data, the sub-address for the data to be read is written in RECEIVER mode, then the data is read
in TRANSMITTER mode.
The SDA line is released for initial reset, so the bus is not occupied. Also, even if the IC supply voltage falls
to 0V, the bus is not occupied. Nonetheless, please keep within the absolute maximum ratings.
This bus is compatible not only with standard mode (maximum 100kbit/s) but with high speed mode
(maximum 400kbit/s) as well.
– 22 –
CXD2027Q/R
• Specifications
Data write (RECEIVER mode)
7654321
0
1
76543210
1
76543210
1
SLAm
Wm
As
SUBm
As
DATAm
As
Sm
to
to
76543210
1
76543210
1
DATAm
As
DATAm
As
P
Data read (RECEIVER mode & TRANSMITTER mode)
7654321
0
1
76543210
1
SLAm
Wm
As
SUBm
As
Sm
to Srm
to
7654321
0
1
76543210
1
87654321
1
SLAm
Rm
As
DATAs
Am
DATAs
XAm
Symbol
Description
∗m
from master to slave
∗s
from slave to master
S
Start Condition
Sr
Start Condition
P
Stop Condition
SLA
Slave Address
SUB
Sub Address
DATA
Data
W
0 : Write Master → Slave
R
1 : Read Slave → Master
A
Clock pulse for Acknowledgement (SDA: L)
XA
Acknowledgement none (SDA:H)
– 23 –
P
CXD2027Q/R
I2C bus control table
SASL
Slave address
R/W
L
H
D4
D6
Subaddress
MSB
Data
bit7
bit6
bit5
00'H
A1S1
A1S2
A1S3
bit4
01'H
WR
Blanks
( )
(L)
MSB, LSB
bit3
bit2
bit1
A2S1
A2S2
A2S3
DOS1
DOS2
DOS3
bit0
02'H
BUSMT1
BUSMT2
AMUTE
SIG
MTOF0
MTOF1
MTOF2
MTOF3
03'H
OTSTP1
OTSTP2
OTSTP3
OTSTP4
NF1
NF2
TH1
TH2
04'H
DASLC
C1SL
LRSL
IIS
BLFS
FPCC
FPCB
(TEST1)
C2
C10
XPRT
DOMU
05'H
RD
LSB
06'H
(TSB0)
(TSB1)
XEOFF
XINH
PI1
PI2
NR
07'H
RGOF1
RGOF2
RGOF3
RGOF4
OTSL
MFRAM
(TEST2)
(TEST3)
00'H
CC1
CC2
CC3
CC4
CC5
CC6
CC7
CC8
01'H
CC9
CC10
CC11
CC12
CC13
CC14
CC15
CC16
02'H
(L)
(L)
(L)
(L)
RG81
RG82
RG83
RG84
:
:
:
:
Data not related to internal logic.
Data for testing. Fix to the default value.
Low is output.
Data is transmitted with MSB first.
Default data (default value of internal register after master reset)
W
WR
Subaddress
MSB
Data
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
00'H
0
1
0
—
0
1
0
—
01'H
—
—
—
—
0
1
0
—
02'H
0
0
1
0
1
1
1
1
03'H
0
0
0
0
0
1
0
1
04'H
0
0
0
0
1
0
1
(0)
05'H
—
—
—
—
1
1
0
0
06'H
(0)
(0)
1
0
0
0
0
—
07'H
1
1
1
1
0
0
(0)
(0)
( ) : Always fix to the default value.
– 24 –
LSB
CXD2027Q/R
• BUS setting values for audio output selection
Sub-address
00'H
BIT No.
Name
bit7
A1S1
bit6
A1S2
bit5
A1S3
bit3
A2S1
bit2
A2S2
bit1
A2S3
00000000'B
Description
Audio output mode selection when using built-in DF/DAC
Audio output mode selection when using external DF/DAC
A1S1
A1S2
A1S3
A2S1
A2S2
A2S3
DOS1
DOS2
DOS3
TV
0
X
X
independent
1
X
X
X
X
X
main + sub
0
1
X
main
0
0
0
sub
0
0
1
main + sub
1
1
X
main
1
0
0
sub
1
0
1
main + sub
X
1
X
main
X
0
0
sub
X
0
1
TV
main
0
X
X
independent
main
1
X
X
main
X
X
X
Applications
A mode
stereo
B mode
TV
A mode
independent
2ch mono
B mode
1ch mono
A mode
B mode
Sub-address
01'H
BIT No.
Name
bit3
DOS1
bit2
DOS2
bit1
DOS3
00000001'B
Description
Output mode selection when using digital interface
Same setting method as for A1S1, A1S2 and A1S3
– 25 –
CXD2027Q/R
• Muting-related BUS setting values
Sub-address
02'H
BIT No.
Name
bit7
BUSMT1
bit6
00000010'B
H
L
Audio data mute when using built-in DF/DAC
ON
OFF
BUSMT2
Audio data mute when using external DF/DAC
ON
OFF
bit3
MTOF0
Carrier detection mute
ON
OFF
bit2
MTOF1
Non-broadcast flag mute
ON
OFF
bit1
MTOF2
Error occurrence frequency mute
ON
OFF
bit0
MTOF3
External mute (EXMU)
ON
OFF
H
L
Sub-address
03'H
Description
00000011'B
BIT No.
Name
Description
bit7
OTSTP1
Signal suppression for external DF/DAC (AUD, LRCK, BCLK)
NonOperation
operation
bit6
OTSTP2
Signal suppression for external descramble
(CK2M, FRAM, DATO)
NonOperation
operation
bit5
OTSTP3
Control sign output suppression (NSYN, CCUP, CC1)
NonOperation
operation
bit4
OTSTP4
Built-in DF/DAC operation / non-operation selection
NonOperation
operation
bit3
NF1
bit2
NF2
bit1
TH1
bit0
TH2
Error occurrence frequency mute setting (number of frames)
Error occurrence frequency mute setting (threshold value)
bit3
bit2
NF1
NF2
0
0
128
0
1
256
1
0
512
1
1
1024
bit1
bit0
TH1
TH2
MUTE∗1
Cancel∗2
0
0
1/2
1/4
0
1
1/4
1/8
1
0
1/8
1/16
1
1
1/16
1/32
Number of frames
Threshold value
∗1 MUTE when over this value
∗2 MUTE cancel when below this value
– 26 –
CXD2027Q/R
• BUS setting values for chargeable flag mute
Sub-address
BIT No.
07'H
00000111'B
Name
Description
H
L
bit7
RGOF1
Audio 1ch mute
ON
OFF
bit6
RGOF2
Audio 2ch mute
ON
OFF
bit5
RGOF3
Audio 3ch mute
ON
OFF
bit4
RGOF4
Audio 4ch mute
ON
OFF
bit2
MFRAM
Master frame sync processing
OFF
ON
bit1
TEST2
For testing (fix to low)
bit0
TEST3
For testing (fix to low)
H
L
• BUS setting values for external I/F, etc.
Sub-address
BIT No.
bit4
02'H
00000010'B
Name
SIG
Description
Signal polarity selection for external descramble I/F
Corresponding input pins : BITI, DATA, DATB
Corresponding output pins : CK2M, DATO, FRAM
– 27 –
Inverted Positive
CXD2027Q/R
Sub-address
BIT No.
04'H
00000100'B
Name
Description
H
L
bit7
DASLC
External descramble I/F control
Refer to page 20.
bit6
C1SL
CC1 (control sign 1st bit) output polarity inversion
Inverted Positive
bit5
LRSL
LRCK polarity inversion
Inverted Positive
bit4
IIS
bit3
BLFS
bit2
FPCC
bit1
FPCB
Selection of the number of front protection for frame sync protection and master
frame syncprotection selection
bit0
TEST1
For testing (fix to low)
bit4
bit3
IIS
BLFS
1
1
Prohibited
1
0
2) IIS
0
1
3) 64fs
0
0
1) SONY
bit2
bit1
FPCC
FPCB
1
1
3
7
1
0
5
9
0
1
7
11
0
0
9
11
Sub-address
BIT No.
bit3
07'H
Audio output format switching
Format
The number of frame sync The number of master
front protection
frame sync front protection
00000111'B
Name
OTSL
Description
DTUP pin output signal switching
H
L
DED
CCUP
• Digital I/F BUS setting values
Sub-address
BIT No.
05'H
Name
00000101'B
Description
H
L
bit3
C2
Digital copy allowed/prohibited selection
Allowed
Prohibited
bit2
C10
Channel status 10th bit
General
BS
bit1
XPRT
Parity inversion selection for digital interface Transmission error
bit0
DOMU
Mute for digital interface (TX is DC low)
– 28 –
ON
Normal
OFF
CXD2027Q/R
• DF and D/A converter-related BUS setting values
Write register
Sub-address
BIT No.
06'H
00000110'B
Name
Description
H
L
bit7
TSB0
bit6
TSB1
bit5
XEOFF
Digital de-emphasis selection
ON
OFF
bit4
XINH
DC dither selection
ON
OFF
bit3
PI1
DC dither phase control Rch
Inverted Positive
bit2
PI2
DC dither phase control Lch
Inverted Positive
bit1
NR
Modulation NR
For testing (normally set to low regardless of input data)
ON
OFF
• Control sign bit reading after integration correction
Sub-address
BIT No.
00'H
00010000'B
Name
Description
bit7
CC1
Control sign 1st bit
bit6
CC2
Control sign 2nd bit
bit5
CC3
Control sign 3rd bit
bit4
CC4
Control sign 4th bit
bit3
CC5
Control sign 5th bit
bit2
CC6
Control sign 6th bit
Suppression backup
bit1
CC7
Control sign 7th bit
Broadcast identification
bit0
CC8
Control sign 8th bit
Expansion bit
Sub-address
BIT No.
01'H
Mode selection
TV audio
Additional audio
00010001'B
Name
Description
bit7
CC9
Control sign 9th bit
bit6
CC10
Control sign 10th bit
bit5
CC11
Control sign 11th bit
bit4
CC12
Control sign 12th bit
bit3
CC13
Control sign 13th bit
—
bit2
CC14
Control sign 14th bit
Master frame sync flag H: asynchronous, L: synchronous
bit1
CC15
Control sign 15th bit
Data suppression
bit0
CC16
Control sign 16th bit
Audio output suppression
Expansion bits
Video scramble existent/non-existent
– 29 –
CXD2027Q/R
• Range 8th bit read after integration correction
Sub-address
02'H
00010010'B
BIT No.
Name
bit7
—
bit6
—
bit5
—
bit4
—
bit3
RG81
Range 8th bit (chargeable flag) 1ch
bit2
RG82
Range 8th bit (chargeable flag) 2ch
bit1
RG83
Range 8th bit (chargeable flag) 3ch
bit0
RG84
Range 8th bit (chargeable flag) 4ch
Description
Low level fixed output
– 30 –
– 31 –
2
DATO
DATA
DSLA
CK2M
FRAM
CC1
7
6
5
4
3
2
1
SkyPort
1000p
COATEC
SW
10k
D24 + 5V
BPF
47µ/16V
2SA1162
22k
47µ
16V
BITO
BITI
DSLB
DATO
DATB
CK2M
FRAM
0.1µ
Dad + 5V
HVU359TRF
23MHz
8
7
6
5
4
3
2
1
REST
ANALOG
INPUT
4.7k
22k
0.01µ
390p: CH
2.7µ
100k
Aout + 12V
A + 5V
D24 + 5V
D23 + 5V
Dad + 5V
2
Buffer
3
1
5.6k
12p: CH
68
3
1
D24 + 5V
0.01µ
2200p
2SC2712
(hFE ≥ 200)
0.1µ
D23 + 5V
4.7k
12k
12k
5.6k
×5
47µ
16V
22k
1800p: CH
0.047µ/16V
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
HVU359TRF
10p: CH
24MHz 330
100k
5.6k
D24 + 5V
220
×2
4.7k
NSYN
4.7k
100
×5
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
NC10
NC11
VDD5
M23O
M23I
PHAA
ALCO
VSS9
NC12
TST7
RT
NC13
ADIN
ADVD
ADVS
RB
GR
TST0
NC14
NC15
CXD2027R
NC9
VDD4
PHAB
MDKI
MCKO
VSS8
MUTE
TST8
VSS7
SCLK
SDA
VDD3
NSYN
DTUP
F256
BCLK
LRCK
AUD
TST6
NC8
NC0
MRST
VSS0
BITO
BITI
DSLB
DSLA
DATB
DATA
VDD0
CK2M
FRAM
DATO
CC1
TX
TST2
TST3
TST4
TST5
NC1
100
100
×4
8.2k
120p: CH
8.2k
120p: CH
9.1k
9.1k
2
3
2200p: CH
4
8
2
3
2200p: CH
6.8k
4
8
30k
150p:
CH
1
150p: CH
2200p: CH
NJM4580E
15k
6.8k
30k
0.1µ
150p
: CH
30k
2200p: CH
6.8k
1
150p: CH
NJM4580E
15k
6.8k
30k
0.1µ
680
0.01µ
: CH
680
0.01µ
: CH
47µ/16V
7
0.027µ
7
0.027µ
NJM4580E
1500p: CH
6
5
680
680
NJM4580E
1500p: CH
6
5
680
680
47µ/16V
47µ/16V
1
2
3
4
5
F256
BCLK
LRCK
AUD
BITO
TX
Output
L ch
Output
R ch
D_out
I2C
Note 1) Circuit connection and constants are the same for the CXD2027Q.
Note 2) This circuit example shows digital de-emphasis off.
The analog de-emphasis circuit is included in the external circuit connected to the built-in
DAC.
100
47µ/16V
8.2k
120p: CH
8.2k
120p: CH
9.1k
9.1k
0.1µ
47µ/16V
A + 5V
0.1µ
47µ/16V
D24 + 5V
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
0.01µ
NC7
NC6
SASL
VSS6
VSS5
RNO
NC5
VDD2
RPO
VSS4
TST1
VSS3
LPO
VDD1
NC4
LNO
VSS2
VSS1
NC3
NC2
0.1µ
D24 + 5V
0.1µ
Aout + 12V
1
2
3
SCL
SDA
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to the same.
100
×6
5.6k
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Application Circuit
D24 + 5V
CXD2027Q/R
CXD2027Q/R
Package Outline
Unit: mm
CXD2027Q
64PIN QFP(PLASTIC)
23.9 ± 0.4
+ 0.4
20.0 – 0.1
+ 0.1
0.15 – 0.05
51
0.15
64
20
1
16.3
32
+ 0.4
14.0 – 0.1
52
17.9 ± 0.4
33
+ 0.2
0.1 – 0.05
0.8 ± 0.2
19
+ 0.35
2.75 – 0.15
+ 0.15
0.4 – 0.1
1.0
± 0.12 M
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP–64P–L01
LEAD TREATMENT
EIAJ CODE
∗ QFP064–P–1420
LEAD MATERIAL
SOLDER/PALLADIUM
PLATING
COPPER /42 ALLOY
PACKAGE WEIGHT
1.5g
JEDEC CODE
CXD2027R
80PIN LQFP (PLASTIC)
14.0 ± 0.2
∗
12.0 ± 0.1
60
41
40
(13.0)
61
0.5 ± 0.2
A
21
(0.22)
80
1
+ 0.08
0.18 – 0.03
0.5 ± 0.08
20
+ 0.2
1.5 – 0.1
+ 0.05
0.127 – 0.02
0.1
0.5 ± 0.2
0.1 ± 0.1
0° to 10°
NOTE: Dimension “∗” does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY / PHENOL RESIN
SONY CODE
LQFP-80P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
∗QFP080-P-1212-A
LEAD MATERIAL
42 ALLOY
PACKAGE WEIGHT
0.5g
JEDEC CODE
– 32 –