ONSEMI AND8054

AND8054/D
Designing RC Oscillator
Circuits with Low Voltage
Operational Amplifiers and
Comparators for Precision
Sensor Applications
APPLICATION NOTE
Jim Lepkowski
Senior Applications Engineer
Christopher Young
Engineering Intern, Arizona State University
INTRODUCTION
The design of RC operational amplifier oscillators
requires the use of a formal design procedure. In general, the
design equations for these oscillators are not available;
therefore, it is necessary to derive the design equations
symbolically to select the RC components and to determine
the influence of each component on the frequency of
oscillation. A design procedure will be shown for two state
variable oscillator circuits that can be used in precision
capacitive sensor applications. These two oscillators have
an output frequency proportional to the product of two
capacitors (C1*C2) and the ratio of two capacitors (C1/C2).
The state variable oscillators have been built using ON
Semiconductor’s new family of sub–1 volt operational
amplifiers and comparators. The MC33501, MC33503, and
NCS2001 operational amplifiers, and the NCS2200
comparator are the industry’s first and only commercially
available analog components that are specified at a voltage
of 0.9 volts. These components can be powered from a single
NiCd, NiMH or alkaline battery cell. The wide operating
temperature range of –40C to +105C makes these devices
suitable for a wide range of applications.
ON Semiconductor’s family of low voltage operational
amplifiers and comparators help solve the analog limitations
that have resulted from the industry’s movement to low
power supply voltages. The ON Semiconductor family of
 Semiconductor Components Industries, LLC, 2002
February, 2002 – Rev. 1
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analog components provide a solution for the analog I/O
interface circuits that are required for emerging low voltage
DSP and microcontroller ICs.
There are a number of advantages that result from
lowering the power supply voltage such as lower power
consumption and the reduction of multiple power supplies.
Low voltage analog design also results in new challenges for
the designer and care must be taken to transfer existing
higher voltage circuits to the lower voltage levels. For
example, device parameters such as the bandwidth and slew
rate decrease as the voltage is reduced and are modest in
comparison to traditional devices operating at voltages such
as ±10 V. Also, there is a limited voltage swing range
available at low voltages; however, this problem is
minimized by the rail–to–rail single voltage range of both
the input and output signals of the ON Semiconductor
devices.
The MC33501 and MC33503 are designed with a
BiCMOS process, while the NCS2001 and NCS2200 are
implemented with a full CMOS process. The main attributes
of these devices are their low voltage operation and a full
rail–to–rail input and output range. The rail–to–rail
operation is provided by using a unique input stage that is
formed by a folded cascade N–channel depletion mode
differential amplifier. A simplified schematic of the
MC33501 and MC33503 is shown in Figure 1.
1
Publication Order Number:
AND8054/D
AND8054/D
VCC
IN–
IN+
Offset
Voltage
Trim
Out
VCC
VCC
Output
Voltage
Saturation
Detector
VCC
Clamp
Body
Bias
Figure 1. Simplified Schematic of the MC33501/MC33503
ON Semiconductor’s Family of Low Voltage Operational Amplifiers and Comparators
Part
Number
Component
Process
MC33501
MC33503
Operational
Amplifier
BiCMOS
NCS2001
NCS2200
Operational
Amplifier
Comparator
CMOS
CMOS
Features
@ Single Supply Operation of 1.0 V
•
•
Available NOW
Production Release 4Q2000
TSOP–5
Available NOW
Production Release 1Q2001
TSOP–5
Product Preview
Production Release 1Q2002
Open Loop Voltage Gain = 90 dB (typ.)
Gain Bandwidth Product = 1.1 MHz (typ.)
Open Loop Voltage Gain = 90 dB (typ.)
@ Single Supply Operation of 1.0 V
•
•
Availability
TSOP–5
Gain Bandwidth Product = 3 MHz (typ.)
@ Single Supply Operation of 0.9 V
•
•
Package
Propagation Delay 1.1 s (typ.)
Complementary or Open Drain Output
Configuration
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AND8054/D
TRANSDUCER SYSTEM
A wide variety of different circuits can be used to
accurately measure capacitive sensors. The design choices
include switched capacitor circuits, analog multivibrators,
AC bridges, digital logic ICs and RC operational amplifier
oscillators. The requirements for a precision sensor circuit
include high accuracy, reliable start–up, good long–term
stability, low sensitivity to stray capacitance and a minimal
component count. State variable RC operational amplifier
oscillators meet all of the requirements listed above; thus,
they form the basis for this study.
A block diagram of a capacitive sensor system is shown
in Figure 2. The oscillation frequency is found by counting
the number of clock pulses (i.e. MHz) in a time window that
is formed by the square wave oscillator output (i.e. kHz) of
a comparator circuit. The counter circuit can be
implemented with a digital logic counter circuit or by using
the Time Processing Unit (TPU) channel of a
microprocessor. If necessary, temperature correction can be
CMEAS
accomplished by implementing a curve fitting routine with
data obtained by calibrating the sensor over the operating
range. An analog IC sensor can be used to monitor the sensor
temperature or for very precise applications a second
oscillator could be built with a platinum resistive
temperature device (RTD) sensor.
In addition, it is often important for the sensor system to
compute the ratio of two capacitors. Calculating the ratio of
the capacitors reduces the transducer’s sensitivity to
dielectric errors from factors such as temperature. In other
cases, such as in an air data quartz P pressure sensors, the
desired measurement is equal to the ratio of two
capacitances (CMEAS / CREF). Furthermore, dual sensors are
typically designed to double the CMEAS in capacitance,
while CREF may vary less than one percent. Thus, the
transducer’s accuracy is increased if a circuit such as the
ratio state variable oscillator can directly detect the CMEAS
to CREF ratio.
CREF
Clock
RC Op–Amp
Oscillator
Counter
Circuit
Comparator
Temperature
Sensor
Algorithm:
Count the number of clock pulses in a time window set by oscillator pulses.
Micro–Processor
EEPROM:
Temperature
Compensation
Coefficients
Clock
Signal
Oscillator
Signal
Figure 2. Block Diagram of Capacitive Sensor Application
SENSOR APPLICATIONS
RC operational amplifier oscillators can be used to
accurately detect both resistive and capacitive sensors;
however, this paper will only analyze capacitive applications.
The three basic configurations of capacitive sensors and their
attributes are shown in Table 1. The absolute and dual
capacitive sensors will be used with the absolute and ratio
oscillator circuits, respectively. Differential capacitive
sensors typically are not used in precision applications;
therefore, they will not be analyzed in this paper.
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Table 1. Summary of Capacitive Sensors
Sensor Configuration
Absolute
Dual
Differential
CMEAS
Schematic Representation
C1
CMEAS
C2
CREF
Sensor Applications
•
•
•
•
•
•
Absolute Pressure
Humidity
Circuit
Absolute Oscillator
Oil Level
Differential Pressure
Typical Circuit – Multivibrator
freq. C1 C2
exponentially decaying. In contrast, if T(s) has one pole that
lies within the right half plane, the system is unstable
because the corresponding term exponentially increases in
amplitude. An oscillator is on the borderline between a
stable and an unstable system and is formed when a pair of
poles is on the imaginary axis, as shown in Figure 4.
If the magnitude of the loop gain is greater than one and
the phase is zero, the amplitude of oscillation will increase
exponentially until a factor in the system such as the supply
voltage restricts the growth. In contrast, if the magnitude of
the loop gain is less than one, the amplitude of oscillation
will exponentially decrease to zero.
V
A
A
A
T(s) OUT A N(s)
s
VIN
1 A
1 LG
+
A ≡ Amplifier Gain
Proximity
C
freq. MEAS
CREF
OSCILLATOR THEORY
An oscillator is a positive feedback control system which
does not have an external input signal, but will generate an
output signal if certain conditions are met. In practice, a small
input is applied to the feedback system from factors such as
noise pick–up or power supply transients, and this initiates the
feedback process to produce a sustained oscillation. A block
diagram of an oscillator is shown in Figure 3.
The poles of the denominator of the transfer equation T(s),
or equivalently the zeroes of the characteristic equation,
determine the time domain behavior of the system. If T(s)
has all of its poles located within the left plane, the system
is stable because the corresponding terms are all
VIN
Displacement
Oil Quality
Ratio Oscillator
freq. CMEAS
Oscillation Frequency
•
•
Acceleration
VOUT
D(s)
–
where
A LG loop gain
s characteristic equation
If VIN 0, then T(s) when s 0
≡ Feedback Factor
At the oscillation condition of s = 0, referred
to as the Barkhausen stability criterion,
|LG| 1 (magnitude) and LG 0 (phase).
Figure 3. Block Diagram of an Oscillator
Imaginary (jω)
Imaginary (jω)
Real (ω)
Real (ω)
2nd Order Oscillator
3rd Order Oscillator
Figure 4. Pole Locations for a 2nd and 3rd Order Oscillator
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AND8054/D
CIRCUIT DESCRIPTIONS
oscillation. The first integrator stage consists of amplifier
A1, resistor R1 and sensor capacitance C1. The second
integrator consists of amplifier A2, resistor R2 and sensor
capacitance C2. Resistor–capacitor combinations R1 and C1,
and R2 and C2, set the gain of each integrator stage, in
addition to setting the oscillation frequency. The inverter
stage consists of amplifier A3, resistors R3 and R4 and
capacitor C4. Capacitor C4 is not essential for normal
operation; however, it ensures oscillator startup under
extreme ambient temperature conditions.
Absolute State Variable Oscillator
The absolute state variable oscillator is used when the
measurement is proportional to either one or two capacitors
(i.e. freq. α C1*C2). The block diagram and schematic of the
absolute circuit are shown in Figures 5 and 6. This circuit
consists of two integrators and an inverter circuit. Each
integrator has a phase shift of 90, while the inverter adds an
additional 180 phase shift; thus, a total phase shift of 360
is fed into the input of the first integrator to produce the
Limit Circuit
V1
V2
Integrator
Integrator
V3
Inverter
= 90°
= 90°
= 180°
Figure 5. Absolute Oscillator Block Diagram
C4
Limit Circuit
C1
R1
–
+
C2
A1
R2
V1
–
+
R4
A2
R3
V2
–
+
A3
The absolute sensor capacitances C1 and C2 are used by the integration amplifiers.
Figure 6. Absolute Oscillator Schematic
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AND8054/D
Ratio State Variable Oscillator
R5, and the sensor capacitors C3 and C4 form the
differentiator stage which provides a 180 phase shift. The
values of resistors R3, R4 and R5 are selected to set the break
frequencies of the differentiator stage, so that the gain of the
stage is equal to –C3/C4. Resistor R5 provides a DC current
path through capacitor C3 in order to initiate oscillation at
power–up. Because R5 is relatively large (MΩ), it can be
replaced with a three resistor “Tee” network in order to use
readily available resistors, as shown in Figure 9.
The ratio state variable oscillator [6] is used for dual
capacitive sensors when the oscillation frequency is
proportional to the ratio of sensor capacitances C3 and C4 (i.e.
freq. α C3 / C4). The block diagram and schematic of the ratio
circuit are shown in Figures 7 and 8. This circuit consists of
two integrators and a differentiator circuit. The integrators
formed by amplifier A1 and A2 are identical to the integrators
used in the absolute circuit. Amplifier A3, resistors R3, R4 and
Limit Circuit
V1
V2
Integrator
V3
Integrator
Differentiator
θ = 90°
θ = 90°
θ = 180°
Figure 7. Ratio Oscillator Block Diagram
C4
Limit Circuit
C1
C2
R4
C3
R1
–
+
A1
R2
–
+
V1
A2
R3
R5
–
+
V2
A3
V3
The differentiator amplifier is formed by the dual sensor capacitances C3 and C4.
Figure 8. Ratio Oscillator Schematic
C4
C1
C2
C3
R4
R1
A1
–
+
R2
–
+
V1
A2
R3
V2
R5a
R5b
–
+
A3
R5c
V3
A Tee network provides a method to replace a large resistor (i.e. MΩ) with three small resistors (i.e. kΩ).
R5a
R5b
R5c
R5_equivalent
R R
R5_equivalent R5a R5b 5a 5b
R5c
⇔
Figure 9. Ratio Oscillator Schematic with R5 Tee Network
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AND8054/D
Method II: Solve N(jo)REAL = N(jo)IMAGINARY = 0
OSCILLATOR DESIGN PROCEDURE
Listed below is a procedure to design RC active
oscillators:
Step 1: Find LG and ∆s
Step 2: Solve ∆s = 0 for s = jωo using methods I, II or III
Method I: Solve remainder of
The oscillation equation sometimes can be determined
directly from the characteristic equation by substituting
s = jωo into N(s) and arranging N(jωo) into its real and
imaginary parts. This method is usually not feasible for fifth
order and higher oscillators. This procedure is essentially a
subset of the Routh test, because the first two rows of the
Routh array will correspond to N(jωo)REAL and
N(jωo)IMAGINARY. If N(s) = jωo = 0, the poles of the
characteristic equation will be on the imaginary axis at ±jωο
with an oscillation frequency of ωo. A summary of the
oscillation equations for 2nd and 3rd order oscillators
obtained using Method II [13] is shown in Appendix II. The
application of Method II is shown for the 3rd order absolute
oscillator with the inverter capacitor C4.
N(s)
=0
2
2
s o
Method II: Solve N(jωο)REAL = N(jωo)IMAG = 0
Method III: Routh’s stability test
Step 3: Form sub–circuit design equations
Step 4: Verify LG ≥ 1
Step 1: Find LG and ∆s
The oscillation frequency is determined by finding the
poles of the denominator of the transfer equation T(s), or
equivalently the zeroes of the numerator N(s) of the
characteristic equation ∆s. Mason’s Reduction Theorem,
shown in Appendix I, provides a method of determining the
transfer equation from a signal flow diagram. Mason’s
Theorem, listed below, shows that it is not necessary to
obtain the complete T(s) equation. The oscillation frequency
can be determined by analyzing the numerator N(s) of the
∆s. ∆s is found by obtaining the open loop gain (LG) by
breaking the feedback loop and applying a test voltage to the
circuit.
T(s) Method III: Routh Stability Test
The Routh stability criterion [12] provides a method that
determines the zeroes of the characteristic equation directly
from the characteristic polynomial coefficients, without the
necessity of factoring the equation. The Routh test, shown
in Appendix III, is the preferred method to use for fourth
order and higher order oscillators. The Routh test consists of
forming a coefficient array. Next, the procedure substitutes
s = jωo for s, and the summation of the row is set to zero. If
the row equation produces a nontrivial solution for ωo, the
procedure is complete and the frequency of oscillation is
equal to ωo. If the row equation does not yield an equation
that can be solved for ωo, the procedure continues with the
next row in the Routh array. Usually, it is necessary only to
complete the first two or three rows of the Routh array to
produce an equation that can be solved for ωo. Method III
will be demonstrated by analyzing the ratio oscillator.
A
A
A N(s)
(s)
1 LG
D(s)
Step 2: Solve ∆s
The second step in the procedure determines the zeroes of
N(s). Several different control theory techniques such as the
Bode or Nyquist stability tests can be used, or one of the
three methods that are listed below. Examples of the
application of the three different methods listed below will
be provided.
Method I:
Step 3: Sub–circuit Design Equations
The third step in the design procedure is to form the design
equations for the sub–circuits formed by each operational
amplifier. The oscillation equation can be simplified by
selecting the R’s and C’s with the assumptions shown in the
“Design Equation” section. The amplifier gain and
pole/zero locations for the absolute and ratio oscillator are
also shown.
N(s)
s2
2o
An equation is established for the oscillation frequency ωo
when N(s) is divided by s2 + ωο2 (i.e.
N(s)
s 2 2o
) and the
remainder is solved to be equal to zero. Method I is easy to
implement for second and third order systems, but with
higher order systems the algebra can be tedious. Method I is
described in [12] and is based on factoring the characteristic
equation to have a s2 + ωo2 term. For example, when a third
order system can be factored in the form (s + β)(s2 + ωo2),
the pole locations are at s = ± jωo and s = –β. Method I will
be demonstrated by analyzing the absolute oscillator
without the inverter capacitor C4. Although the analysis of
this second order system is trivial because N(s) is already in
the form of s2 + ωo2, this method can be used for higher order
circuits such as the 4th order ratio oscillator.
Step 4: Verify LG ≥ 1
The final step in the procedure verifies that the loop gain
is equal to or greater than one after the R’s and C’s
component values have been chosen. This step is required to
verify that the location and clamping voltage of the limit
circuit will not result in a LG < 1, or that the operational
amplifiers will reach their saturation voltage. The limit
circuit can be located across any of the three amplifiers as
long as the LG ≥ 1.
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AND8054/D
ABSOLUTE OSCILLATOR DESIGN EQUATIONS
C1
R1
–
+
C2
A1
R2
–
+
V1
R4
A2
R3
A3
V3
With C4
R
A3 4
R3
1
sR2C2
–
+
V2
Without C4
A2 C4
A2 1
sR2C2
A3 RR43sR4C14 1
V3
V2
V1
A1 V3
V2
V1
1
sR1C1
A1 1
sR1C1
Figure 10. Absolute Oscillator Signal Flow Diagrams
Absolute Oscillator (without C4)
Step 1: Find LG and s
The loop gain is found by breaking the loop and inserting a “test’’ voltage into the input.
A1 –
1
sR1C1
A2 –
R
A3 – 4
R3
1
sR2C2
VTEST
VOUT
V1
V2
LG VOUT
A1 A2 A 3
VTEST
s N(s)
1 LG 1 – 1
D(s)
sR1C1
V3
– sR21C2– RR43 1 s2R RRR4 C C
1 2 3 1 2
s2R1R2R3C1C2 R4
s2R1R2R3C1C2
N(s) s2R1R2R3C1C2 R4
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s2 R4
R1R2R3C1C2
AND8054/D
Absolute Oscillator (with C4)
Step 1: Find LG and s
The loop gain is found by breaking the loop and inserting a “test’’ voltage into the input.
A1 –
1
sR1C1
A2 –
RR43sR4C14 1
1
sR2C2
A3 –
VTEST
VOUT
V1
LG VOUT
A1 A2 A 3
VTEST
LG –
s V2
V3
A3 R4 || C4
Z4
Z3
R3
– sR21C2– RR43sR4C14 1 – s3R R R R C C CR4 s2R R R C C
1
sR1C1
1 2 3 4 1 2 4
1 2 3 1 2
N(s)
R4
1 LG 1 D(s)
s3R1R2R3R4C1C2C4 s2R1R2R3C1C2
s3R1R2R3R4C1C2C4 s2R1R2R3C1C2 R4
s3R1R2R3R4C1C2C4 s2R1R2R3C1C2
N(s) s3R1R2R3R4C1C2C4 s2R1R2R3C1C2 R4
Absolute Oscillator (without C4)
Step 2: Solve N(s) using Method I
Solve Method I: Solve the remainder of:
N(s)
s 2 2o
N(s) s2R1R2R3C1C2 R4
s2 2o
R1R2R3C1C2
R1R2R3C1C2s2 R4
R1R2R3C1C2s2 2oR1R2R3C1C2
R4 2oR1R2R3C1C2
Set the remainder to equal zero and solve for o: R4 2oR1R2R3C1C2 0
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o R1R2RR34C1C2
AND8054/D
Absolute Oscillator (with C4)
Step 2: Solve N(s) using Method II shown in Appendix II: o aa31 aa20
N(s) a0s3 a1s2 a2s a3 s3R1R2R3R4C1C2C4 s2R1R2R3C1C2 R4
a0 R1R2R3R4C1C2C4
a1 R1R2R3C1C2
a2 0
a3 R4
o aa31 R1R2RR34C1C2
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Absolute Oscillator
Step 3a: Subcircuit Oscillation Design Equations
Absolute Oscillator
Without C4
N(s)
R1R2R3C1C2s2 R4
o
Oscillation Period
2
P
o
With C4
R1R2R3R4C1C2C4s3 R1R2R3C1C2s2 R4
R4
R1R2R3C1C2
R4
R1R2R3C1C2
P 2R C1C2
P 2R C1C2
If R1 = R2 = R and R3 = R4
If R1 = R2 = R and R3 = R4
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AND8054/D
Absolute Oscillator
Step 3b: Subcircuit Amplifier Design Equations
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Absolute Oscillator
Integrator A1 Gain
Pole Location
Integrator A2 Gain
Without C4
With C4
V
A1 1 – 1
1
V3
sR1C1
2fR1C1
1
fp1 2 R1C1
V
A1 1 – 1
1
V3
sR1C1
2fR1C1
1
fp1 2 R1C1
V
A2 2 – 1
1
V1
sR2C2
2fR2C2
V
A2 2 – 1
1
V1
sR2C2
2fR2C2
1
fp2 2 R2C2
Pole Location
Inverter A3 Gain
V
R
A3 3 – 4
V2
R3
Pole Location
NA
1
fp2 2 R2C2
V
R
1
A3 3 – 4
V2
R3 sR4C4 1
1
fp3 2 R4C4
* s Ro s Ro s Ro –s Ro RC Sensitivities*
*Sensitivity is defined as: SY X
1
2
s Co
1
s Co
2
3
4
1
2
Y
d ln(Y)
Y
X
d ln(X)
X
Absolute Oscillator
Step 4: Verify LG 1
Step 4 will be demonstrating using the dual power supply
limit circuit shown in Figure 25. The design equations are
listed below.
Assume:
1.) VPos_Limit VNeg_Limit VLimit
2.) V2 VLimit
(i.e. |A2| VLimit)
3.) |A3| R4R3 1
Check:
1.)
Is |LG| A1 A2 A3 VLimit
2.)
2fR11C1 (VLimit) RR43 VLimit
Using the values shown in Figure 25,
2(16.6 kHz)(391 K ) (240 pF) (VLimit) (1) VLimit
1.02 VLimit VLimit
thus the oscillation will be sustained.
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s Ro s Ro s Ro –s Ro 1
2
s Co
1
s Co
2
3
1
2
4
AND8054/D
RATIO OSCILLATOR DESIGN EQUATIONS
C4
C1
C2
R4
C3
R1
–
+
A1
R2
–
+
V1
A2
R3
R5
–
+
V2
A2 –
1
sR2C2
A3 –
V3
R4(sR5C3 1)
(sR3R5C3 R3 R5)(sR4C4 1)
V3
V2
V1
A1 –
A3
1
sR1C1
Figure 11. Ratio Oscillator Signal Flow Diagrams
Ratio Oscillator
Step 1: Find LG and s
The loop gain is found by breaking the loop and inserting a “test’’ voltage into the input.
A1 –
1
sR1C1
A2 –
1
sR2C2
A3 –
R4(sR5C3 1)
(sR3R5C3 R3 R5)(sR4C4 1)
VTEST
VOUT
V1
LG VOUT
A1 A2 A 3
VTEST
V2
A3 V3
R4 C4
–Z4
Z3
R3 (C3 R5)
5C3 1)
– sR21C2– (sR3R5C3R4(sR
R3 R5)(sR4C4 1)
LG –
1
sR1C1
LG sR4R5C3 R4
4
3
[(
s R1R2R3R4R5C1C2C3C4 s R3R5C3 R3R4C4 R4R5C4)R1R2C1C2] s2(R3 R5)(R1R2C1C2)
s4R1R2R3R4R5C1C2C3C4 s3[(R3R5C3 R3R4C4 R4R5C4)R1R2C1C2]
s s2(R3 R5)(R1R2C1C2) sR4R5C3 R4
N(s)
1 LG D(s)
s4R1R2R3R4R5C1C2C3C4 s3[(R3R5C3 R3R4C4 R4R5C4)R1R2C1C2]
s2(R3 R5)(R1R2C1C2)
N(s) s4R1R2R3R4R5C1C2C3C4 s3[(R3R5C3 R3R4C4 R4R5C4)R1R2C1C2]
s2(R3 R5)(R1R2C1C2) sR4R5C3 R4
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AND8054/D
Ratio Oscillator
Step 2: Solve N(s) using Method III (Routh’s Stability Test) shown in Appendix III
N(s) s4R1R2R3R4R5C1C2C3C4 s3[(R3R5C3 R3R4C4 R4R5C4)R1R2C1C2]
s2(R3 R5)(R1R2C1C2) sR4R5C3 R4
s a0s4
a1s3
a2s2
a0 R1R2R3R4R5C1C2C3C4
a2 (R3 R5)(R1R2C1C2)
a3s a4
a1 [(R3R5C3 R3R4C4 R4R5C4)R1R2C1C2]
a3 R4R5C3
a4 R4
Routh’s Stability Test Array
Row s4 a0 a2 a4
Row s3 a1 a3
R1R2R3R4R5C1C2C3C4
(R3R5C3 R3R4C4 R4R5C4)R1R2C1C2
(R3 R5)R1R2C1C2
R4R5C3
R4
a1s3 a3s s(a1s2 a3) 0
Determine when the row s3 equation is equal to zero.
Let s jo :
a
R4R5C3
2o 3 a1
(R1R2C1C2)(R3R5C3 R3R4C4 R4R5C4)
–j 3oa 1 j oa 3 j o(a 1 2o a 3) 0
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Ratio Oscillator
Step 3a: Subcircuit Oscillation Design Equations
N(s)
o
Oscillation Period
2
P
o
s4R1R2R3R4R5C1C2C3C4 s3[(R3R5C3) (R3R4C4) (R4R5C4)](R1R2C1C2)
s2(R3 R5)(R1R2C1C2) sR4R5C3 R4
R4R5C3
R1R2C1C2(R3R5C3 R3R4C4 R4R5C4)
If R1 R2 R and C1 C2 C
P 2RC
If R5 R3 and R4 R3 then
R3C4 C4 R3
R5C3 C3 R4
P 2RC
C4
C3
Ratio Oscillator
Step 3b: Subcircuit Amplifier Design Equations
Integrator A1
Gain/Pole Location
V
A1 1 – 1
1
V3
sR1C1
2fR1C1
1
fp1 2R1C1
Integrator A2
Gain/Pole Location
V
A2 2 – 1
1
V1
sR2C2
2fR2C2
1
fp2 2R2C2
A3 Differentiator A3 Gain
R4(sR5C3 1)
(R3 R5)(sR3C3 1)(sR4C4 1)
DC Gain Pole/Zero Locations
RC Sensitivities
–R4
R3 R5
1
fp1 2R4C4
Gain at Oscillation 1
fp2 2R3C3
1
fz1 2R5C3
s Ro s Ro s Co s Co s Co s Co –1
2
1
2
1
2
3
4
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13
–C3
C4
AND8054/D
Gain (dB)
Assumptions
1. C3 C4
C
20x log 10 3
C4
2. C3 C4
Fz1 1
2R5C3
3. R3 R4 R5
R
4. R3 R5 and R4 5
10
Oscillation
Range
Frequency (Hz)
0
1
2R4C4
Fp1 20x log 10
Fp2 1
2R3C3
R3 R4 R5
Figure 12. Bode Plot of Differentiator Amplifier A3
Ratio Oscillator
Step 4: Verify LG 1
Step 4 will be demonstrating using the single power supply limit circuit shown in Figure 26.
The design equations are listed below.
Assume:
1.) V2 VMax_Limit
(i.e.|A2| VMax_Limit)
C
2.) |A3| 3
C4
Check:
1.)
Is |LG| A1 A2 A3 VMax_Limit
2.)
2fR11C1 (VMax_Limit) CC34 VMax_Limit
Using the values shown in Figure 26,
2(16.5 kHz)(391 K ) (240 pF) (VMax_Limit) CC34 VMax_Limit
(1.03) (VMax_Limit)
3.)
CC34 VMax_Limit
Oscillation will be sustained if
C3
1
1.03
C4
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AND8054/D
COMPONENT SELECTION
If the integrator offset and bias errors are referenced to the
output, as shown below,
Operation Amplifiers
The selection of an appropriate operational amplifier in a
precision oscillator application is based on analyzing the
errors caused by the amplifiers. Operational amplifier errors
include input offset voltage (VIO) and input bias current (IB),
open loop gain (Ao), and a finite bandwidth and slew rate
(SR). The error contribution of the operational amplifier can
be minimized if a low bias current, wide bandwidth
amplifier is chosen. Also, selecting a low oscillation
frequency minimizes the DC gain and bandwidth errors. In
sensor applications, only the frequency of the signal is
monitored; therefore, the DC amplifier errors of VOS, IB,
and a finite gain will result in output signal distortion, but
will not have a significant effect on the oscillation
frequency. The open loop gain of almost all amplifiers will
be several orders of magnitude larger than the closed loop
gain of an oscillator, which typically is 1 to 2 at each
amplifier. The AC amplifier errors resulting from a finite
slew rate and bandwidth has a minimal effect if the
oscillation frequency is relatively low (i.e. 10 kHz to
20 kHz).
dVOUT(t)
V
I
IO B
dt
RC
C
the following observations can be made:
1. Use small R, large C.
2. VOS ∝ 1 / RC and IB ∝ 1 / C .
3. Use a low leakage current capacitor.
4. IB can be reduced if a resistor equal to the parallel
combination of R and C is connected to the
non–inverting input of the amplifier.
The error due to the operational amplifier’s finite open
loop gain and bandwidth, as shown below:
VOUT(s)
1
VIN(s)
sRC
Rp –
+
VOUT
1 1 Tos 1 1 To Ao Ao AoRpCs AoRpC
1
– 1 s
1
sRC 1 AoRpCs
VOUT(s)
– 1
VIN(s)
sRC
Listed below are the equations for the ideal integrator
circuit formed by a single resistor and a capacitor as shown
in Figure 13.
VIN(t)dt
1
Also, there will be an error due to the amplifier slew rate
and output current limitation. The slew rate error is defined
as:
The ideal integrator equations do not consider the effect
of the amplifiers voltage offset and current bias offset errors.
The effect of the offset errors is shown below [3][11].
dVOUT(t)
|max 2fpEo SR
dt
VIN(t)dt RC1 VIOdt C1 IBdt VIO
where: fP ≡ full power response
Eo ≡ rated output voltage
= ideal offset error bias error
The output current (Io) of the amplifier charges the
integrator feedback capacitor; thus, the integrator may have
a slew rate that is less than the specified amplifier SR. The
maximum rate of change of output voltage is equal to Io/C.
Where VIO and IB are defined as:
VIO
T(Temp)
T
VIO
VIO
Vs(PowerSupply) t(Time)
t
Vs
I
IB IB B T(Temp)
T
RdR
Rd R
If Ao >> 1, the transfer equation can be simplified to:
Figure 13. Ideal Integrator Amplifier
VIO VIO Rd ≡ open loop impedance
To ≡ –3 dB frequency
ω1 ≡ the unity gain bandwidth ≈ Ao / To
R
VOUT(t) – 1
RC
1 1
sRpC
where:
C
VOUT(t) 1
RC
VOUT(s)
– 1
VIN(s)
sRC
1
1Tos
Ao
= ideal (gain bandwidth error)
Integrators
VIN
1 I
IB
Vs(PowerSupply) B t(Time)
t
VS
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AND8054/D
Differentiator
A practical differentiator circuit is shown in Figure 15. For
simplicity, this circuit will neglect the effect of resistor R5.
There will be an error due to the operational amplifier’s
finite open loop gain as shown below:
R
C
VIN
–
+
VOUT
Ao
1
1Ao R3C4
1
s2 s 1 1
R3R4C3C4
R4C4 R3C3
s
VOUT(s)
VIN(s)
Figure 14. Ideal Differentiator
If Ao >> 1, the transfer equation can be simplified to:
Listed below are the equations for the ideal differentiator
circuit shown in Figure 14.
VOUT(s)
VIN(s)
s
dVIN(t)
VOUT(t) RC
dt
VOUT(s)
sRC
VIN(s)
R31C4
s
1
R 3C 3
s R 1C 4 4
sR4C3
sR3C3 1 sR4C4 1
C4
R5
However, the ideal differentiator does not consider the
effect of the amplifier’s voltage offset and current bias
errors, as shown below [3].
R3
VIN(t)
VOUT(t) RC
VIO IBR
dt
R4
C3
VIN
If the output offset and bias errors are referenced to the
input, as shown below,
–
+
Figure 15. Practical Differentiator (Neglect R5)
dVIN(t)
V
I
IO B
dt error
RC
C
The error due to the operational amplifier’s finite open
loop gain and bandwidth is shown graphically in Figure 16.
The oscillator’s amplifier error and bandwidth error terms
are reduced if a higher gain and increased operational
amplifier is selected. The oscillation error can be minimized
by selecting an oscillation frequency that is as low as
practical (i.e. foscillation ≅ 10 KHz).
The Slew Rate (SR) error of a differentiator is identical to
the equation listed for an integrator.
the following observations can be made:
1. Use small R, large C.
2. VIO ∝ 1 / RC and IB ∝ 1 / C .
dVOUT(t)
|
2fpEo SR
dt
max
Gain (dB)
AO
Open Loop Gain
Gain Error
20x log C3
C4
0
R3 R4 R5
20x log
Bandwidth
Error
Frequency (Hz)
To
VOUT
1
FP1 2R4C4
Fp2 1
Fz1 2R4C3
1
2R3C3
Closed Loop Gain
Figure 16. Graphical Error Analysis of Ideal Differentiator
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16
AND8054/D
Voltage Limit Circuits
Automatic Gain Control (AGC) circuits and voltage limit
or bounding circuits are used in oscillators to prevent the
operational amplifiers from saturating and to avoid
amplifier slew rate limitations. Bipolar transistors are
inherently slow in coming out of saturation; therefore, a
limit circuit should be used to prevent a frequency error
when using amplifiers such as the BiCMOS MC33501 or
MC33503. FET transistors do not have the slow recovery
time problem coming out of saturation; however, a limit
circuit should also be used with CMOS operational
amplifiers. The gain of the transistors in a CMOS
operational amplifier such as the NCS2001 will change
when the transistors saturate; thus, a limit circuit is
necessary to prevent an oscillation error.
Limit circuits will also decrease the required time for the
oscillation signal to stabilize at start–up. When an
oscillator’s poles are located exactly on the imaginary axis,
the resulting waveform will be a perfect sinusoidal signal.
To ensure oscillation startup the poles are adjusted to lie
slightly in the right half s–plane causing the signal to grow
exponentially until it is limited by some type of
non–linearity, such as the saturation voltage of the amplifier.
VCC
VIN
+
–
U1
VOUT
R1
VEE
R2
Q1
AGC
Figure 17. FET AGC Circuit
Limit Circuits
Limit circuits are nonlinear circuits, which clamp the
amplitude to a voltage level that is less than the amplifier
power supply voltage. This clamping function will produce
distortion in the oscillator signal. The selection of the
voltage limit circuits is based on the allowable signal
distortion and the simplicity of the circuit. The distortion
level for most sensor oscillator circuits is relatively
unimportant because only the frequency of the signal is
monitored. Also, limit circuits are preferable to AGC
circuits because they require fewer components. Limit
circuits typically consist of a combination of zener diodes,
diodes, and transistors.
AGC Circuits
Automatic Gain Control (AGC) circuits provide a linear
control of the amplifier gain to produce a constant output
voltage regardless of the level of the input signal. AGC
circuits are usually used in applications where the level of
signal distortion needs to be minimized. AGC circuits are
more complex than limit circuits and usually consist of an
operational amplifier and/or FET that are used as a variable
resistor. An example of an AGC circuit is shown in Figure 17.
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17
AND8054/D
Dual Power Supply Limit Circuits
available in voltages of about 1.8 volts, while their forward
voltage drop is typically 0.7; therefore, this circuit is not
useful for voltage limiting applications below 2.5 volts.
The minimum voltage range of the back–to–back zener
diode limit circuit can be reduced by adding two resistors to
the limit circuit as shown in Figure 20 [4]. The clamping
value of this circuit is a function of the zener diode
breakdown voltage multiplied by the ratio of the resistors.
This circuit is solves the low voltage limitation of the
back–to–back zener limit circuit; however, this circuit is not
suitable for the integrator amplifiers of the oscillator when
resistor R2 is replaced by a capacitor.
Figure 18 shows the clamping function of the limit circuit
for a dual power supply application. A simple dual supply
voltage limit circuit can be created by using two
back–to–back zeners as shown in Figure 19. There are
several performance limitations with this circuit that result
from the relative large junction capacitance, leakage current
and temperature coefficient of a zener diode. These
limitations result in a distortion of the output signal and an
error in the oscillation frequency. In addition, this circuit’s
low voltage operation is limited to the value of the zener
diode’s clamping voltage (VZener) plus the forward voltage
drop (Vf) of the second zener diode. Zener diodes are
D1
D2
VIN and VOUT
R2
VIN
VPos_Limit
VCC
VOUT
R1
VIN
–
+
VNeg_Limit
VOUT
VEE
VLimit (VZener Vf)
Figure 19. Back–to–Back Zener Diode Limit Circuit
Figure 18. Dual Power Supply Clamping
D1
R1a
R1b
D2
R2
VIN
VCC
–
+
VOUT
VEE
VLimit (VZener Vf) *
R2
R1b R2
Figure 20. Back–to–Back Zener Diode Limit Circuit
with Voltage Ratio Resistors
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Single Power Supply Circuits
The voltage limit circuit shown in Figure 21 is useful in
dual power supply designs when the integrator capacitance
is relatively small. A combination of two transistors and two
diodes are used to make up the circuit, which limits the
signal at positive and negative voltages. The diodes are used
to reduce the effective capacitance of the bipolar transistors
and they can be removed for low voltage applications.
The operation of the limit circuits formed by the NPN
and/or PNP transistors can be understood by using the
Ebers–Moll transistor model, where a transistor is modeled
as a base–to–emitter and a base–to–collector diode. The
circuit functions by setting the fixed voltage at the
base–to–collector junction to be less than the diode’s
turn–on voltage; therefore, this diode is always “OFF’’.
Next, the emitter of the transistor is connected to the sine
wave output of the amplifier; thus, the base–to–emitter
voltage (VBE) can be either greater than or less than a diode’s
turn–on voltage. When the VBE voltage is above the diode’s
turn–on voltage, the diode is “ON’’ and the transistor is in
the forward–active mode of operation and the circuit clamps
at a level set by the base voltage. However, when the VBE
voltage is below the diode turn–on voltage, the junction is
“OFF’’ and the transistor is in the cut–off mode of operation
and the clamping network is effectively an open circuit.
Figure 22 shows the clamping function of the limit circuit
for a single power supply application [3] [4]. The limit
circuit for low voltage single supply circuits can be formed
by a single NPN or PNP transistor. The PNP circuit shown
in Figure 23 is used to create the maximum voltage limit,
while the NPN circuit shown in Figure 24 is used to form the
minimum voltage limit. Note that in single supply
applications it is not necessary to use both the PNP and NPN
limit circuits. Only one of the limit circuits is required to
prevent the amplifiers from saturating in the state variable
oscillator.
VIN and VOUT
VIN
VOUT
VMax_Limit
VMin_Limit
t
VQ1_Base
Figure 22. Single Power Supply Clamping
D1
Q1
VQ2_Base
D2
VQ1_Base
Q2
Q1
C
C
VCC
VIN
VCC
R
VOUT
–
+
R
VIN
VEE
VCC/2
–
+
VOUT
VEE
VQ1_Base 0 V
VQ2_Base 0 V
VPos_Limit VQ1_base VQ1_base–to–emitter Vf
VMax_Limit VQ1_base VQ1_base–to–emitter
VQ1_base 0.7 V
VQ1_base (2 * 0.7) VQ1_base 1.4 V
VNeg_Limit VQ2_base VQ2_base–to–emitter Vf
Figure 23. Single Supply Maximum Limit Circuit
VQ2_base (2 * 0.7) VQ2_base 1.4 V
Figure 21. Dual Power Supply Limit Circuit
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specification of 200 ppm or ± 0.02 pF, whichever is greater,
for a 2000 hour life test at 200% WVDC and a temperature
of 125C. The major error term of capacitors is due to
temperature hysteresis and is specified as the retrace error.
Precision sensors use temperature compensation, thus a
change of capacitance with temperature can be corrected;
however, it is difficult to correct for hysteresis errors. Other
error sources are a result of the piezoelectric effect (∆C vs.
voltage and pressure), the quality factor (Q), and the
terminal resistance. These errors are relatively small
because the capacitors are designed for microwave
frequencies and are specified at a WVDC well beyond the
normal operating voltage of an op–amp circuit.
VQ1_Base
Q1
C
VCC
R
VIN
VCC/2
–
+
VOUT
VEE
APPLICATION ISSUES
VMin_Limit VQ1_base VQ1_base–to–emitter
Remote Sensing
Often, it is necessary to remotely locate the detection
circuit from the sensor, and connect the sensor to the circuit
with a shielded cable. For example, an oil level sensor for a
gas turbine engine must operate at a temperature of 400°F,
which is well beyond the operating capability of standard
electronic components. In addition, a shielded cable is often
required to limit the noise sensitivity of the measurement.
The capacitance of shielded wire is typically 30 to 50 pF per
foot, while the sensor capacitance is usually less than 100 pF.
Thus, the electronic circuit must be insensitive to the cable
capacitance which will be much larger than the sensor
capacitance.
One approach to minimize the cable capacitance error is
to use a shielded cable and the virtual ground feature of an
operational amplifier when the non–inverting input is
grounded. This feature is inherent in the integrator and
inverter/differentiator circuits used in the state variable
oscillator. Because an operational amplifier has a high open
loop gain and input impedance, the differential voltage
between the inverting and non–inverting inputs is
essentially zero. Thus, the voltage potential at the inverting
input is equal to the ground potential at the non–inverting
terminal. The virtual ground approach forces a constant
voltage to appear across the cable capacitance; therefore, the
cable capacitance does not have to be charged or discharged
by the circuit and the oscillation frequency is not effected.
A constant DC level at the non–inverting input in the single
power supply configuration is equivalent to a virtual ground
because the AC level of the input terminals is equal to zero
volts. The remote sensing ability of the state variable
oscillator will be analyzed in detail in a future application
note.
VQ1_base 0.7 V
Figure 24. Single Supply Minimum Limit Circuit
Resistors and Capacitors
It is critical that the oscillator circuits use precision
resistors and capacitors with a small temperature coefficient
(TC) and low drift rate to minimize temperature and aging
errors. Long term stability is typically specified for resistors
and capacitors by a life test of 2000 hours at the maximum
rated power and ambient temperature. In general these
components have an exponential change in value for the first
500 hours of the test and are essentially stable for the
remainder of the test. Thus, a burn–in, or temperature
cycling procedure will significantly lower the drift error of
the resistors and capacitors.
Three types of precision resistors are available: metal
film, wirewound, and foil. Metal film and wirewound
resistors are available with a TC of ±10 to ±25 ppm/C and
a drift specification of approximately 0.1 to 0.5%. Foil
resistors are available with a TC of ±0.3 ppm/C and a drift
specification of less than 20 ppm. Errors with resistors are
caused by both environmental and manufacturing factors.
The major environmental factors causing changes in
resistance are the operating power and the ambient
temperature. Other environmental factors such as humidity,
the voltage coefficient (∆R vs. voltage), the thermal EMF
(due to the temperature difference between the leads and self
heating), and storage will cause relatively small errors.
Manufacturing induced errors from factors such as
soldering can cause a small change in resistance; however,
this error will not effect the component’s long term stability.
Two of the leading technologies of stable capacitors are
RF/Microwave multilayer porcelain and NPO (COG)
ceramic capacitors. The TC of porcelain capacitors is
specified at +90 ± 20 ppm/C, while NPO ceramic
capacitors are available with a TC of 0 ± 30 ppm/C. The TC
is specified over a temperature range of –55 to 125C;
however, the specification is skewed by the relatively large
changes in capacitance at the extreme hot and cold
temperatures. Both types of capacitors have a drift
Reference Design
The reference design for the absolute oscillator is shown
in Figure 25. The circuit uses the BiCMOS MC33501
operational amplifiers operated at a power supply of ± 2.5V.
In addition the circuit uses the dual supply limit circuit. The
operating voltage of the circuit could be lowered by
removing diodes D1 and D2, and adjusting the base voltages
of transistors Q1 (VPos_Limit) and Q2 (VNeg_Limit). In the
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AND8054/D
The NCS2200 comparator is used by the ratio oscillator
design to convert the oscillator’s sine wave output to a
square ware digital signal. The NCS2200 is available in both
a complementary and an open drain output configuration.
The reference design used the open drain configuration to
form a zero crossing detector.
Table 2 lists the calculated and measured oscillation
frequency for the reference designs. The calculated
frequency was obtained by measuring the R’s and C’s and
using these values with the oscillation equations.
The measured frequency of the absolute and ratio
oscillators was approximately ±1% different than the
calculated frequency. This error between the measure and
predicated oscillation frequency is probably due to the
capacitance of the limit circuits, which is not included in the
frequency equations. The reference designs used standard
NPN, PNP transistors and diodes; selecting high frequency
or RF devices would minimize the oscillation error of the
limiting circuit.
typical application, capacitors C1 and C2 would be the
sensor capacitances.
The reference design for the ratio circuit is shown in
Figure 26. This circuit uses the CMOS NCS2001
operational amplifiers operated at the single power supply
of 0.9V. In addition the circuit uses the single supply limit
circuit. In the typical application, Capacitor C 3 functions as
the CMEAS sensor while C4 serves as the CREF sensor.
The single supply Vcc/2 reference voltage was obtained
by using a resistor divider network. The values of the
resistors R9 and R10 were obtained by finding the input
impedances of the integrator circuits formed at amplifiers
A1 (R1 || C1) and A2 (R2 || C2). The input bias current of the
CMOS amplifier is specified at only 10 pA; therefore, it is
not necessary to balance the impedances at the
non–inverting and inverting terminals of the amplifiers. In
most applications, the non–inverting terminal can be
connected directly to the reference voltage. Figure 27 shows
a voltage follower circuit that could be used to provide a
more stable reference voltage with the additional benefit of
a low output impedance.
MPS2907A
Q1
D1
1N4001
VQ1_Base = 0.5 V
VQ2_Base = –0.5 V
D2
1N4001
Q2
MPS2222A
C2
240 pF
C1
240 pF
R1
39 k
C4
22 pF
R2
39 k
– A1
+
–
+
MC33501
A2
R4
10 k
R3
10 k
MC33501
–
+
A3
MC33501
NOTES:
1. Power Supply Voltages for amplifiers A1, A2, and A3 are VCC = 2.5 V, VEE = 2.5 V
2. VPos_Limit = 1.9 V and VNeg_Limit = –1.9 V
Figure 25. Reference Design – Absolute Circuit
Table 2. Reference Designs Oscillation Frequency
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Circuit
Calculated Oscillation Frequency
Measured Oscillation Frequency
Absolute Oscillator
16.6 kHz
16.4 kHz
Ratio Oscillator
16.5 kHz
16.3 kHz
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MPS2907A
Q1
VCC
R9
39 k
VQ1_Base = 0.1 V
VCC/2
R10
39 k
R1
39 k
VCC/2
– A1
+
NCS2001
C3
47 pF
C2
240 pF
C1
240 pF
R2
39 k
VCC/2
–
+
C4
47 pF
VCC
R4
3 Meg
R3
5k
A2
R5
20 Meg
VCC/2
NCS2001
–
+
A3
NCS2001
R7
100 k
R6
1k
VCC/2
+
–
R8
5k
A4
NCS2200
NOTES:
1. Power Supply Voltages for amplifiers A1, A2, A3, and A4 is VCC = 0.9 V, VEE = 0 V
2. Capacitors C3 and C4 are typically the sensor capacitance; however, for test purposes two 47 pF capacitors were used to verify the
circuit.
3. VMax_Limit = 0.8 V
Figure 26. Reference Design – Ratio Circuit
VCC
R
R
C
+
–
VCC/2
Figure 27. Low Output Impedance Reference Voltage
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AND8054/D
Appendix I: Mason’s Reduction Theorem
oscillator. In contrast, Step 1 of the design procedure only
provides the denominator of T(s) and will not provide the
numerator of the transfer equation. Mason’s equation can
be rewritten in the form listed below:
The oscillation frequency is determined by finding the
poles of the denominator of the transfer equation T(s) or
equivalently the zeroes of the numerator N(s) of the
characteristic equation ∆(s). Mason’s theorem (12.) states
that the transfer function from input X to output Y is
T(s) D(s)
Pisi
The absolute and ratio oscillators only have a single
feedback loop,
therefore,
the
calculation
of
T(s) Y i
s
X
T(s) where the terms are defined as:
to output Y
si is the system determinant.
si 1 if Pi touches all of the loops
Lj
LkLl LmLnLn Lj is the sum of all loops (i.e. loop gains)
LkLl
is the sum of products of pairs of
non–touching loops
LmLnLo
is the sum of products of gains of
non–touching loops taken three at a
time
A1 –
Mason’s Reduction Theorem should be used to determine
the transfer equation if the oscillator has more than one
feedback loop, such as the case for the circuit shown in
Figure 28. Obtaining T(s) also provides the additional
information required to complete a Bode plot of the
–
+
1
– 1
sR1C1
s(R1 R11)C1
Listed below are the calculation of T(s) for the absolute
oscillator with and without capacitor C4 and the ratio
oscillator.
C2
C1
R1
A1
V1
V3
V11
is relatively easy because the path P1 (equivalent to the
amplifier gain A) is defined as the voltage gain from node
V11 to V3 and will be equal to the loop gain LG1. In order to
calculate the transfer equation, the intermediate voltage
node of V11 is created by adding a “small” resistor R11 in
series with resistor R1 to the absolute and ratio circuits as
shown in Figures 29 and 30. Adding R11 and V11 is not
mathematically necessary; however, it greatly simplifies
the algebra in the transfer equations. Note, the numerator of
the transfer equation depends on the definition of the input
and outputs; however, the denominator (i.e. the oscillation
equation) is independent of the definition of T(s). If R1 >>
R11, then the gain of amplifier A1 is a function only of R1
and C1.
Pi is the direct transmittance or path form input X
s 1 A
A
A N(s)
(s)
1 LG
R2
–
+
R4
A2
R3
V2
–
+
A3
R5
Figure 28. Mason’s Theorem Provides a Method to Determine the Transfer Equation T(s) of an
Oscillator when there are Multiple Feedback Loops, as with the Modified Absolute Circuit
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AND8054/D
C4
R1
A1
+
–
V11
R2
+
–
R11
C2
V1
R4
A2
R3
V2
+
–
C1
A3
V3
Figure 29. Schematic of the Absolute Oscillator with Rll that is Used to Obtain T(s),
using Mason’s Reduction Theorem
Absolute Oscillator (without C4)
Assume R1 >> R11, then R1 + R11 R1
P1 LG1 A1 A2 A3 –
s 1 LG1 1 –
– sR21C2– RR43
1
sR1C1
– sR21C2– RR43 1 s2R RRR4 C C
1
sR1C1
1 2 3 1 2
s2R1R2R3C1C2 R4
s2R1R2R3C1C2
R4
s2R1R2R3C1C2
V3
P1
R4
T(s) 2
s
V11
s
R
R
R
2
s R1R2R3C1C2R4
1 2 3C1C2 R4
s2R1R2R3C1C2
Absolute Oscillator (with C4)
Assume R1 >> R11, then R1 + R11 R1
P1 LG A1 A2 A3
P1 LG –
– sR21C2– RR43sR4C14 1 – s3R1R2R3R4C1C2CR4 4 s2R1R2R3C1C2
1
sR1C1
s 1 LG 1 s3R1R2R3R4C1C2C4 s2R1R2R3C1C2 R4
R4
3
2
s R1R2R3R4C1C2C4 s R1R2R3C1C2
s3R1R2R3R4C1C2C4 s2R1R2R3C1C2
R4
R4
s3R1R2R3R4C1C2C4s2R1R2R3C1C2
P
T(s) 1 s
s3R1R2R3R4C1C2C4s2R1R2R3C1C2R4
s3R1R2R3R4C1C2C4 s2R1R2R3C1C2 R4
s3R1R2R3R4C1C2C4s2R1R2R3C1C2
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Ratio Oscillator
C4
C1
C2
R4
C3
+
–
V11
A1
R2
+
–
R1
V1
A2
R3
R5
V2
A3
+
–
R11
V3
Figure 30. Schematic of the Ratio Oscillator with Rll that is Used to Obtain T(s),
using Mason’s Reduction Theorem.
Ratio Circuit
Assume R1 >> R11 , then R1 + R11 R1
P1 LG A1 A2 A3 –
P1 LG1 (sR4R5C3 R4)
s4R1R2R3R4R5C1C2C3C4 s3R3R5C3 R3R4C4 R4R5C4R1R2C1C2 s2R3 R5R1R2C1C2
s 1 LG1 V
P
T(s) 3 1 s
V11
5C3 1)
– sR21C2– (sR3R5C3R4(sR
R3 R5)(sR4C4 1)
1
sR1C1
s4R1R2R3R4R5C1C2C3C4 s3R3R5C3 R3R4C4 R4R5C4R1R2C1C2 s2R3 R5R1R2C1C2 sR4R5C3 R4
s4R1R2R3R4R5C1C2C3C4 s3R3R5C3 R3R4C4 R4R5C4R1R2C1C2 s2R3 R5R1R2C1C2
(sR4R5C3R4)
s4R1R2R3R4R5C1C2C3C4s3R3R5C3R3R4C4R4R5C4R1R2C1C2s2R3R5R1R2C1C2
s4R1R2R3R4R5C1C2C3C4s3R3R5C3R3R4C4R4R5C4R1R2C1C2s2R3R5R1R2C1C2sR4R5C3R4
s4R1R2R3R4R5C1C2C3C4s3R3R5C3R3R4C4R4R5C4R1R2C1C2s2R3R5R1R2C1C2
(sR4R5C3 R4)
4
3
s R1R2R3R4R5C1C2C3C4 s (R3R5C3 R3R4C4 R4R5C4) R1R2C1C2 s2R3 R5R1R2C1C2 sR4R5C3 R4
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AND8054/D
Appendix II: Method II:
Solve N(jωo)REAL = N(jωo)IMAGINARY = 0
Let s = jωο be the frequency at which N2(s) = 0. The
condition for oscillation is meet when the a1 term is set to
zero, and the s–term is removed. The frequency of
oscillation is found from:
The oscillation equation sometimes can be determined
directly from the characteristic equation by substituting
s = jωο into ∆s and arranging the N(jωο) into its real and
imaginary parts. However, this method is usually not
feasible for circuits which are fifth order and higher
oscillators. This procedure is essentially a subset of the
Routh test, because the first two rows of the Routh array will
correspond to N(jωo)REAL and N(jωo)IMAGINARY. If the
characteristic equation N(s) = jωο = 0, the poles of the
characteristic equation will be on the imaginary axis at ±jωο
with an oscillation frequency of ωο. The Method II
procedure is shown below for second and third order
oscillators [13].
Second–Order Circuits
o aa20
Third Order Circuits
N3(s) a0s3 a1s2 a2s a3
Let s = jωο be the frequency at which N3(s) = 0, and arrange
the equation into its real and imaginary parts:
N3(jo) (–a1 2o a3) jo(–a0 2o a2) 0
Thus, the real and imaginary parts equal zero when:
–a1 2o a3 0 and –a0 2o a2 0
a
a
N2(s) a0s2 a1s a2 a0 s2 1 s 2
a0
a0
Solving the above equations for o2 gives:
a
a
2o 3 2
a1
a0
Summary of Method II Equations
Oscillator
Order
N(s)
Oscillation
Condition
2nd
N2(s) a0s2 a1s a2
a1 0
3rd
N3(s) a0s3 a1s2 a2s a3
a1a2 a0a3
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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o
o o a3
a1
a2
a0
a2
a0
AND8054/D
Appendix III: Routh’s Stability Test
where the coefficients b1, b2, b3, etc., are evaluated as
follows:
Routh’s Stability Test [12] can be used to test the
characteristic equation to determine whether any of roots lie
on the imaginary axis. Routh’s test consists of forming a
coefficient array. Next, the procedure substitutes s = jωo for
s, and the summation of the row is set to zero. If the row
equation produces a nontrivial solution for ωo, the procedure
is complete and the frequency of oscillation is equal to ωo.
If the row equation does not yield an equation that can be
solved for ωo, the procedure continues with the next row in
the Routh array. This technique arranges the numerator of
the characteristic equation (i.e. denominator of the transfer
equation) into the array listed below.
T(s) a a a0a3
b1 1 2
a1
a a a0a7
b3 1 6
a1
The evaluation of the b’s is continued until the remaining
terms are equal to zero. The same pattern of cross
multiplying the coefficients of the two previous rows is
followed in evaluating the c’s, d’s, etc...
b a b2a1
c1 1 3
b1
A
A
A (s)
1 LG
N(s)
D(s)
b a b3a1
c2 1 5
b1
N(s) a0sn a1sn 1 a2sn 2 a3sn 3
This process is continued until the n–th row has been
completed. The Routh stability criterion states:
1. A necessary and sufficient condition for stability is
that the first column of the array does not contain
sign changes.
2. The number of sign changes in the entries of the
first column of the array is equal to the number of
roots in the right half s–plane.
3. If the first element in a row is zero, it is replaced by
ε, and the sign changes when ε → 0 are counted
after completing the array.
4. The poles are located in the right half plane or on
the imaginary axis if all the elements in a row are
zero.
... an 1s an
sn
a0
a1
a2
a3
sn–3
.
.
.
b1
c1
.
.
.
b2
c2
.
.
.
s0
f1
sn–1
sn–2
a4
an
a5
an–1
b3
c3
.
.
a a a0a5
b2 1 4
a1
bn–2
cn–3
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BIBLIOGRAPHY
1. Baxter, L., “Capacitive Sensors Offer Numerous
Advantages”, Electronic Design, January 26, 1998.
2. Celma, C., Martinez P., Carlosens, A., “Approach
to the Synthesis of Canonic RC–Active Oscillators
Using CCII”, IEE Proc. Circuits, Devices and
Systems, Vol. 141, No. 6, December 1994, pp.
493–497.
3. Clayton, G. and Winder, Steve, Operational
Amplifiers (4th edition), Newness, Boston, 2000.
4. Graeme, Jerald, Amplifier Applications of Op
Amps, McGraw – Hill, N.Y., 1999
5. Griffith, R., Vyne, R., Dotson, R., and Petty, T,
“A 1–V BiCMOS Rail–to–Rail Amplifier with
n–Channel Depletion Mode Input State,” IEEE
Journal of Solid–State Circuits, Vol. 32, No. 12,
Dec. 1997, pp. 2012 – 2022.
6. Lepkowski, J. and et. al, “Capacitive Pressure
Transducer System”, U.S. Patent No. 4,987,782,
Issued Jan. 29, 1991.
7. Lindquist, C., Active Network Design with Signal
Filtering Applications, Steward and Sons, Long
Beach, 1977.
8. Martinez, P., Aldea C. and Celma, S., “Approach
to the Realization of State Variable Based
Oscillators”, IEEE International Conference on
Electronics Circuits and Systems, Vol. 3, 1998, p.
139–142.
9. Pease, Robert, “Bounding, Clamping Techniques
Improve Circuit Performance,” EDN, Nov. 10,
1983.
10. Sidorowicz, R. “An Abundance of Sinusoidal
RC–Oscillators”, Proc. IEE, Vol. 119, No. 3,
March 1972, pp. 283–293.
11. Stata, Ray, “AN–357: Operational Integrators,”
Analog Devices, Norwood, MA, 1967.
12. Truxal, J. Introductory System Engineering,
McGraw–Hill, N.Y., 1972.
13. Van Valkenburg, M., Analog Filter Design,
Saunders College Publishing, Fort Worth, 1992.
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