CXD3611R
Timing Generator for Progressive Scan CCD Image Sensor
Description
The CXD3611R is a timing generator IC which
generates the timing pulses for performing progressive
scan readout using the ICX414/415/424 CCD image
sensors.
Features
• Base oscillation frequency
24.545451MHz (ICX414, 424)/
29.500000MHz (ICX415)
(When in double speed drive mode:
49.090902/59.000000MHz)
• Electronic shutter function
• Trigger shutter function
• Supports central scanning mode (two types)/
double speed drive mode
• Horizontal driver for CCD image sensor
(However, uses external driver for double speed
drive mode.)
• Vertical driver for CCD image sensor
Applications
Monitoring/image analysis
64 pin LQFP (Plastic)
Absolute Maximum Ratings
• Supply voltage VDD
Vss – 0.3 to +7.0
V
VL
–10.0 to Vss
V
VH
VL – 0.3 to +26.0
V
• Input voltage
VI
Vss – 0.3 to VDD + 0.3 V
• Output voltage VO1
Vss – 0.3 to VDD + 0.3 V
VO2
VL – 0.3 to VSS + 0.3
V
VO3
VL – 0.3 to VH + 0.3
V
• Operating temperature
Topr
–20 to +75
°C
• Storage temperature
Tstg
–55 to +150
°C
Recommended Operating Conditions
• Supply voltage VDDa, VDDb 3.0 to 5.5
VDDc
3.0 to 3.6
VM
0.0
VH
14.5 to 15.5
VL
–7.0 to –8.0
• Operating temperature
Topr
–20 to +75
Structure
Silicon gate CMOS IC
Applicable CCD Image Sensors
• ICX414 (Type 1/2, 330K pixels)
• ICX415 (Type 1/2, 460K pixels)
• ICX424 (Type 1/3, 330K pixels)
V
V
V
V
V
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E02561-PS
CXD3611R
VDD3
XSHD
XRS
15 16 17 18 14
OSCI
XSHP
RG
VDD2
H2
H1
Vss2
Block Diagram
20 21 22
19
32
31
26 ADCLK
23 PBLK
30
1/2
MCKO 29
24 CLPDM
Selector
CKI
Selector
27 VSS3
OSCO
1/2
Pulse Generator
25 OBCLP
41 WEN
SNCSL
Selector
2
Latch
SSI 38
SCK 39
34 RDM
SEN 40
35 TRG
PS 37
36 ESG
HDRS 11
CDSRS 12
CCD
4
MD1
5
MD2
6
MD3
7
SMD1
8
SMD2
Register
52 V1
54 V2
58 V3
V Driver
SSG
9
50 VM
SMD3 10
56 VH
3
43
42
47
46
45
44
SYNC
BLK
HDO
VDO
VDI
HDI
VDD1
Vss1
13 33
VDD4
1 28 48
Vss5
64
Vss4
49
TEST
60 VL
RST
SSGSL
62 SUB
Notes) 1. CKI must always be input below amplitude VDD with a sine wave.
2. The system block diagram above is an example using an oscillator.
–2–
CXD3611R
VSS5
HDO
VDO
VDI
HDI
SYNC
BLK
WEN
SEN
SCK
SSI
PS
ESG
TRG
RDM
VDD4
Pin Configuration
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
54
27 Vss3
NC
55
26 ADCLK
VH
56
25 OBCLP
NC
57
24 CLPDM
V3
58
23 PBLK
NC
59
22 XRS
VL
60
21 XSHD
NC
61
20 XSHP
SUB
62
19 VDD3
NC
63
18 VDD2
TEST
64
17 H2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
H1
V2
VSS2
28 Vss4
RG
53
VDD1
NC
CDSRS
29 MCKO
HDRS
52
SMD3
V1
SMD2
30 CKI
SMD1
51
MD3
NC
MD2
31 OSCO
MD1
50
CCD
VM
SSGSL
32 OSCI
SNCSL
49
VSS1
RST
∗ Groups of pins enclosed in the figure indicate sections for which power supply separation is possible.
–3–
CXD3611R
Pin Description
Pin
No.
Symbol
I/O
Description
1
VSS1
2
SNCSL
I
Control input used to switch sync system
High: CKI sync, Low: MCKO sync.
3
SSGSL
I
Pin used to switch external reset
High: External sync has priority, Low: Internal sync has priority
With pull-down resistor
4
CCD
I
Control input used to switch CCD
High: ICX415, Low: ICX414/424
With pull-down resistor
5
MD1
I
Control input 1 used to switch drive mode
See the section on parallel control
With pull-down resistor
6
MD2
I
Control input 2 used to switch drive mode
See the section on parallel control
With pull-down resistor
7
MD3
I
Control input 3 used to switch drive mode
See the section on parallel control
With pull-down resistor
8
SMD1
I
Control input 1 used to switch exposure time
See the section on parallel control
With pull-down resistor
9
SMD2
I
Control input 2 used to switch exposure time
See the section on parallel control
With pull-down resistor
10
SMD3
I
Control input 3 used to switch exposure time
See the section on parallel control
With pull-down resistor
11
HDRS
I
Control input used to switch H system pulse polarity
H1 and H2 are targeted (Default is positive polarity.)
High: For external Dr, Low: For internal Dr
With pull-down resistor
—
GND
With pull-down resistor
Control input used to switch CDS system pulse polarity
XSHP, XSHD, XRS, OBCLP, CLPDM are targeted.
High: Positive polarity, Low: Negative polarity
With pull-down resistor
12
CDSRS
13
VDD1
—
3.3V power supply. (Power supply for common logic block)
14
RG
O
CCD reset gate pulse output
15
VSS2
—
GND
16
H1
O
CCD horizontal register clock output
17
H2
O
CCD horizontal register clock output
18
VDD2
—
3.3V power supply. (Power supply for H1/H2/RG)
19
VDD3
—
3.3V power supply. (Power supply for CDS)
20
XSHP
O
CCD precharge level sample-and-hold pulse output
21
XSHD
O
CCD data level sample-and-hold pulse output
22
XRS
O
Sample-and-hold pulse output for analog/digital conversion phase alignment
23
PBLK
O
Pulse output for horizontal and vertical blanking period pulse cleaning
24
CLPDM
O
CCD dummy signal clamp pulse output
25
OBCLP
O
CCD optical black signal clamp pulse output
26
ADCLK
O
Clock output for analog/digital conversion IC
Logical phase can be adjusted using serial interface data.
27
VSS3
—
GND
I
–4–
CXD3611R
Pin
No.
Symbol
I/O
Description
28
VSS4
—
GND
29
MCKO
O
System clock output for signal processing IC
30
CKI
I
Inverter input
31
OSCO
O
Inverter output for oscillation; should be open or C grounded when not in use.
32
OSCI
I
Inverter input for oscillation; should be fixed to Low when not in use.
33
VDD4
—
34
RDM
I
Trigger control, normally fixed to VDD.
See the section on trigger shutter function.
With pull-up resistor
35
TRG
I
Trigger control, normally fixed to VDD.
See the section on trigger shutter function.
With pull-up resistor
36
ESG
I
Readout pulse position control, normally fixed to VDD.
See the section on trigger shutter function.
With pull-up resistor
37
PS
I
Control input used to switch serial and parallel
High: Parallel, Low: Serial
With pull-up resistor
38
SSI
I
Serial interface data input for internal mode settings.
Schmitt trigger input
39
SCK
I
Serial interface clock input for internal mode settings.
Schmitt trigger input
40
SEN
I
Serial interface strobe input for internal mode settings.
Schmitt trigger input
41
WEN
O
Memory writing timing pulse output
42
BLK
O
Blank pulse output
43
SYNC
O
SYNC pulse output
44
HDI
I
Horizontal sync reset signal input
With pull-up resistor
45
VDI
I
Vertical sync reset signal input
With pull-up resistor
46
VDO
O
Vertical sync signal output
47
HDO
O
Horizontal sync signal output
48
VSS5
—
GND
49
RST
I
3.3V power supply. (Power supply for common logic block)
Input pin for internal system reset
Normally, apply reset during power-on.
High: Normal operation, Low: Reset control
50
VM
—
GND (Ground for vertical driver)
51
NC
—
No connection
52
VI
O
CCD vertical register clock output
53
NC
—
No connection
54
V2
O
CCD vertical register clock output
55
NC
—
No connection
56
VH
—
15.0V power supply. (Power supply for vertical driver)
57
NC
—
No connection
58
V3
O
CCD vertical register clock output
59
NC
—
No connection
60
VL
—
–7.5V power supply. (Power supply for vertical driver)
–5–
Schmitt trigger input
CXD3611R
Pin
No.
Symbol
I/O
Description
61
NC
—
No connection
62
SUB
O
CCD electronic shutter pulse output
63
NC
—
No connection
64
TEST
I
Pin for IC test, normally fixed GND.
–6–
With pull-down resistor
CXD3611R
Electrical Characteristics
DC Characteristics
Item
Pins
(Within the recommended operating conditions)
Symbol
Conditions
Min.
Typ.
Max.
Unit
Supply
voltage 1
VDD3
VDDa
3.0
3.3
5.5
V
Supply
voltage 2
VDD2
VDDb
3.0
3.3
5.5
V
Supply
voltage 3
VDD1, VDD4
VDDc
3.0
3.3
3.6
V
Input
voltage 1∗1
RST, SSI,
SCK, SEN
Vt+
Input
voltage 2∗2
SNCSL,
SSGSL, TEST, VIH1
CCD, MD1 to 3,
SMD1 to 3,
VIL1
HDRS, CDSRS
Input
voltage 3∗3
RDM, TRG,
ESG, PS,
VDI, HDI
Output
voltage 1
H1, H2
Output
voltage 2
RG
Output
voltage 3
XSHP, XSHD,
PBLK, XRS,
OBCLP,
CLPDM,
ADCLK
Output
voltage 4
MCKO
Output
voltage 5
WEN, BLK,
SYNC, VDO,
HDO
Output
current 1
Output
current 2
V1, V2, V3
SUB
0.8VDDc
V
0.2VDDc
Vt–
0.7VDDC
V
0.3VDDC
VIH2
0.7VDDC
VIL2
Feed current where IOH = –14.0mA VDDb – 0.8
VOL2
Pull-in current where IOL = 9.6mA
VOH3
Feed current where IOH = –3.3mA
VOL3
Pull-in current where IOL = 2.4mA
VOH4
Feed current where IOH = –3.3mA
VOL4
Pull-in current where IOL = 2.4mA
VOH5
Feed current where IOH = –3.3mA
VOL5
Pull-in current where IOL = 2.4mA
VOH6
Feed current where IOH = –2.4mA
VOL6
Pull-in current where IOL = 4.8mA
IOL
V1, V2, V3 = –8.25V
IOM1
V1, V2, V3 = –0.25V
IOM2
V2, V3 = 0.25V
IOH
V2, V3 = 14.75V
IOSL
SUB = –8.25V
IOSH
SUB = 14.75V
∗1 These input pins are Schmitt trigger inputs.
∗2 These input pins are with a pull-down resistor in the IC.
∗3 These input pins are with a pull-up resistor in the IC.
Note) The table above indicates the condition for 3.3V drive.
–7–
V
V
0.3VDDC
VOH2
V
V
V
0.4
VDDb – 0.8
V
V
0.4
VDDa – 0.8
V
V
0.4
V
V
VDDc – 0.8
0.4
VDDc – 0.8
V
V
0.4
10.0
V
mA
–5.0
5.0
mA
mA
–7.2
5.4
mA
mA
–4.0
mA
CXD3611R
Inverter I/O Characteristics for Oscillation
Item
Pins
Logical Vth
OSCI
Input
voltage
OSCI
Output
voltage
OSCO
Feedback
resistor
Oscillation
frequency
(Within the recommended operating conditions)
Symbol
Conditions
Min.
Typ.
Max.
VDDc/2
LVth
VIH
V
0.7VDDc
V
0.3VDDc
VIL
VOH
Feed current where IOH = –3.6mA VDDc – 0.8
VOL
Pull-in current where IOL = 2.4mA
OSCI, OSCO
RFB
VIN = VDDc or VSS
OSCI, OSCO
f
500k
Unit
V
V
2M
20
0.4
V
5M
Ω
50
MHz
Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment
(Within the recommended operating conditions)
Item
Pins
Logical Vth
Input
voltage
Symbol
Conditions
Min.
LVth
Input
amplitude
V
0.3VDDc
0.3
fmax 50MHz sine wave
Unit
V
0.7VDDc
VIL
VIN
Max.
VDDc/2
VIH
CKI
Typ.
V
Vp-p
Note) Input voltage is the input voltage characteristics for direct input from an external source. Input amplitude
is the input amplitude characteristics in the case of input through a capacitor.
Switching Characteristics
Item
Rise time
Fall time
Output noise voltage
(VH = 15.0V, VM = GND, VL = –7.5V)
Symbol
Conditions
Min.
Typ.
Max.
Unit
TTLM
VL to VM
200
350
500
ns
TTMH
VM to VH
200
350
500
ns
TTLH
VL to VH
30
60
90
ns
TTML
VM to VL
200
350
500
ns
TTHM
VH to VM
200
350
500
ns
TTHL
VH to VL
30
60
90
ns
VCLH
1.0
V
VCLL
1.0
V
VCMH
1.0
V
VCML
1.0
V
Notes)
1) The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for
measures to prevent electrostatic discharge.
2) For noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1µF or more)
between each power supply pin (VH, VL) and GND.
3) To protect the CCD image sensor, clamp the SUB pin output at VH before input to the CCD image
sensor.
–8–
CXD3611R
Switching Waveforms
TTMH
TTHM
VH
V3 (V2)
TTLM
90%
90%
10%
10%
TTML
VM
90%
90%
10%
10%
TTML
TTLM
VL
VM
90%
90%
V1
10%
10%
TTLH
TTHL
90%
VL
VH
90%
SUB
10%
10%
VL
Waveform Noise
VM
VCMH
VCML
VCLH
VCLL
VL
–9–
– 10 –
R1
C2
R1
–7.5V
+3.3V
HDI
VDI
C2
C1
C2
C2
C1
C2
C2
+15.0V
Measurement Circuit
R2
C2
C1
C2
C1
C2
C2
C1: 3300pF
R1: 30Ω
R1
C1
C2
C2 C2
C1 C2
R1
C2: 560pF
R2: 10Ω
R1
C2
R1
C3: 820pF
C3
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
21
60
C4: 6pF
C5: 107pF
C6: 10pF
17
64
C5
18
63
C4
19
62
20
22
59
61
23
58
24
25
56
CXD3611R
26
57
27
55
29
52
54
30
51
28
31
50
53
32
49
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
Serial interface data
C5
C6
C6
C6
C6
C6
C6
C6
C6
CKI
CXD3611R
CXD3611R
AC Characteristics
AC characteristics between the serial interface clocks
0.8VDDc
SSI
0.2VDDc
0.8VDDc
0.2VDDc
ts1
SCK
SEN
th1
0.2VDDc
ts3
0.8VDDc
SEN
ts2
(Within the recommended operating conditions)
Symbol
ts1
th1
ts2
ts3
Definition
Min.
Typ.
Max.
Unit
SSI setup time, activated by the rising edge of SCK
20
ns
SSI hold time, activated by the rising edge of SCK
20
ns
SCK setup time, activated by the rising edge of SEN
20
ns
SEN setup time, activated by the rising edge of SCK
20
ns
Serial interface clock internal loading characteristics
Example: Progressive Scan Mode
VDO
HDO
V2
Enlarged view
HDO
0.2VDDc
V2
th1
ts1
SEN
0.8VDDc
0.2VDDc
∗ Be sure to maintain a constantly high SEN logic level near the falling edge of the HDO in the horizontal
period during which V2 and V3 values take the ternary value and during that horizontal period.
(Within the recommended operating conditions)
Symbol
ts1
th1
Definition
Min.
Typ.
Max.
Unit
SEN setup time, activated by the falling edge of HDO
0
ns
SEN hold time, activated by the falling edge of HDO
32
µs
∗ Restrictions in the progressive scan mode when the ICX415 operating frequency is set to 29.5MHz.
– 11 –
CXD3611R
Serial interface clock output variation characteristics
Normally, the serial interface data is loaded to the CXD3611R at the timing shown in the section "Serial
interface clock internal loading characteristics". However, one exception to this is when the data such as
CKMD is loaded to the CXD3611R and controlled at the rising edge of SEN. See "Description of Operation".
SEN
0.8VDDc
Output signal
tpdPULSE
(Within the recommended operating conditions)
Symbol
Definition
Min.
tpdPULSE Output signal delay, activated by the rising edge of SEN
Typ.
5
Max.
Unit
100
ns
RST loading characteristics
RST
0.2VDDc
0.2VDDc
tw1
(Within the recommended operating conditions)
Symbol
tw1
Definition
Min.
RST pulse width
Typ.
Max.
35
Unit
ns
VDI and HDI phase characteristics
VDI
0.2VDDc
0.2VDDc
ts1
th1
HDI
0.2VDDc
(Within the recommended operating conditions)
Symbol
ts1
th1
Definition
Min.
Typ.
Max.
Unit
VDI setup time, activated by the falling edge of HDI
0
ns
VDI hold time, activated by the falling edge of HDI
0
ns
– 12 –
CXD3611R
HDI loading characteristics
HDI
0.2VDDc
0.2VDDc
ts1
th1
0.8VDDc
MCKO
MCKO load capacitance = 10pF
(Within the recommended operating conditions)
Definition
Symbol
ts1
th1
Min.
Typ.
Max.
Unit
HDI setup time, activated by the rising edge of MCKO
16
ns
HDI hold time, activated by the rising edge of MCKO
0
ns
Output variation characteristics
0.8VDDc
MCKO
WEN
tpd1
WEN load capacitance = 10pF
(Within the recommended operating conditions)
Symbol
tpd1
Definition
Min.
Time until the above outputs change after the rise of MCKO
25
– 13 –
Typ.
Max.
Unit
55
ns
CXD3611R
Description of Operation
Pulses output from the CXD3611R are controlled mainly by the RST pin and by the serial interface data. The
Pin Status Table is shown below, and the details of serial interface control are described on the following
pages.
Pin Status Table
Pin
No.
Symbol
CAM
RST
Pin
No.
Symbol
CAM
RST
Pin
No.
Symbol
CAM
RST
23
PBLK
ACT
H
45
VDI
ACT
ACT
1
VSS1
2
SNCSL
ACT
ACT
24
CLPDM
ACT
H
46
VDO
ACT
H
3
SSGSL
ACT
ACT
25
OBCLP
ACT
H
47
HDO
ACT
H
4
CCD
ACT
ACT
26
ADCLK
ACT
ACT
48
VSS5
5
MD1
ACT
ACT
27
VSS3
—
49
RST
6
MD2
ACT
ACT
28
VSS4
—
50
VM
—
7
MD3
ACT
ACT
29
MCKO
ACT
ACT
51
NC
—
8
SMD1
ACT
ACT
30
CKI
ACT
ACT
52
V1
9
SMD2
ACT
ACT
31
OSCO
ACT
ACT
53
NC
10
SMD3
ACT
ACT
32
OSCI
ACT
ACT
54
V2
11
HDRS
ACT
ACT
33
VDD4
55
NC
—
12
CDSRS
ACT
ACT
34
RDM
ACT
ACT
56
VH
—
13
VDD1
35
TRG
ACT
ACT
57
NC
—
14
RG
36
ESG
ACT
ACT
58
V3
15
VSS2
37
PS
ACT
ACT
59
NC
—
16
H1
ACT
ACT
38
SSI
ACT
DIS
60
VL
—
17
H2
ACT
ACT
39
SCK
ACT
DIS
61
NC
—
18
VDD2
—
40
SEN
ACT
DIS
62
SUB
19
VDD3
—
41
WEN
ACT
L
63
NC
—
20
XSHP
ACT
ACT
42
BLK
ACT
L
64
TEST
—
21
XSHD
ACT
ACT
43
SYNC
ACT
L
22
XRS
ACT
ACT
44
HDI
ACT
ACT
—
—
ACT
ACT
—
—
—
L
ACT
VL
ACT
—
VM
ACT
VL
ACT
VL
ACT
Note) CAM means normal operation and RST means a state wherein control is applied by the RST pin
(Pin 49).
ACT means that the circuit is operating, and DIS means that loading is stopped. L indicates a low
output level, and H indicates a high output level in the controlled status.
Also, VH, VM and VL indicate the voltage levels applied to VH (Pin 56), VM (Pin 50) and VL (Pin
60), respectively, in the controlled status.
– 14 –
CXD3611R
Parallel Interface Control
The CXD3611R has several pin control systems. Specifically, they are SNCSL (Pin 2), SSGSL (Pin 3), CCD
(Pin 4), MD1 , MD2 , MD3 (Pins 5 to 7), SMD1 , SMD2 , SMD3 (Pins 8 to 10), HDRS (Pin 11),
CDSRS (Pin 12), RDM (Pin 34), TRG (Pin 35), ESG (Pin 36), PS (Pin 37), HDI (Pin 44), VDI (Pin 45),
and RST (Pin 49).
See "Pin Description" for details regarding: SNCSL , SSGSL , CCD , HDRS , CDSRS , PS , RST .
When parallel control is selected in the PS pin (Pin 37), the control indicated below takes priority over the
serial control, described later. Note that (double) indicates that the base oscillation frequency ratio is doubled
and it has entered a low speed drive. When a double speed drive is entered, it means that drive at a normal
speed can be used.
Also, a single field 1 means only the ODD sided field is repeated so half of the 0.5H is applied to that V
frequency. Single field 2 means only the ODD sided field simultaneously, but has 1H units for that V frequency.
MD2/MD1
MD3
Low/Low
Low/High
High/Low
High/High
Low
Progressive scan
Central scan 1
Single field 1
Interlace
High
Progressive scan (Double)
Central scan 2
Single field 2
Interlace (Double)
∗ See the section relating to serial interface control and drive mode, describe later, for details.
SMD3
SMD2
SMD1
Low
Low
Low
ICX414/424
ICX415
Unit
Progressive scan
Interlace
Progressive scan
Interlace
Low
No SUB
000h
No SUB
000h
No SUB
000h
No SUB
000h
—
Low
High
1/100
16Fh
1/100
068h
1/120
1FEh
1/120
0B5h
s
Low
High
Low
1/250
1CDh
1/250
0C7h
1/250
232h
1/250
0F9h
s
Low
High
High
1/500
1EDh
1/500
0E6h
1/500
251h
1/500
118h
s
High
Low
Low
1/1000
1FCh
1/1000
0F6h
1/1000
260h
1/1000
128h
s
High
Low
High
1/2000
204h
1/2000
0FEh
1/2000
268h
1/2000
130h
s
High
High
Low
1/4000
208h
1/4000
102h
1/4000
26Ch
1/4000
134h
s
High
High
High
All SUB
20Dh
All SUB
106h
All SUB
270h
All SUB
138h
—
∗ Uses progressive scan mode and interlace mode as standards.
Central scan mode and single field mode are not strictly combined.
– 15 –
CXD3611R
TRG , RDM , ESG use the trigger shutter function. The trigger shutter function relates to serial control and
the electronic shutter function, and as such is described later.
The functions for HDI and VDI are switched by SSGSL .
VDI is received as V-reset when the internal SSG priority is set to ( SSGSL = L). However, basically, VDI /
HDI are fixed at high so substantially, it is an internal SSG drive.
VDO is V-Reset by VD1 , when the external sync priority is set to ( SSGSL = H). This IC simply repeats idle
transfers of V when a 1V operation is cut and a longer cycle is applied. Also, H-Reset occurs for HDO by
HDI .
Note that for external sync priority, operations without a VDI / HDI reset input are not guaranteed.
In the interlace system mode, when a falling edge of the VDI input from an external source is detected, it
determines whether it is ODD or EVEN. If ODD, a V-Reset is applied on the falling edge of the HDO and the
midway of the HDO if EVEN, so that the VDO falls. VDI requires a pulse width of over 2H.
Also, in all, an H-Reset is applied when a falling edge of an HDI reset signal is detected and HDO falls with
the falling edge after 9MCKO. The minimum reset pulse width of the HDI is 10MCKO.
V-Reset
VDI
9H
VDO
HDO
H-Reset
MCKO
HDI
HDO
– 16 –
CXD3611R
Field Identification (When VDI is input in the interlace system mode)
1
VDI
2
HDO
tp1
tp3
tp2
fhd (internal pulse)
tp4
Symbol
tp1
tp2
tp3
tp4
tp5
tp5
VDO
1
ODD
VDO
2
EVEN
Definition
ICX414/424 (ck)
ICX415 (ck)
Region to reset to ODD
273
329
Region to reset to EVEN
384
465
Region to reset to ODD
—
—
Prohibited region
4
4
Prohibited region
4
4
∗ There are no particular standards because HDO periods can be any value according to the HDI reset.
∗ Clock unit is MCKO.
– 17 –
CXD3611R
Serial Interface Control
The CXD3611R can be controlled by the serial interface data transmitted in the format below, for controls other
than those that are applied by MD1 , MD2 , MD3 (Pins 5 to 7) and SMD1 , SMD2 , SMD3 (Pins 8 to
10) when serial control or parallel control is selected in the PS (Pin 37).
Serial interface data latches with the rising edge of the SEN for each 1 category and reflects taking in at the
falling edge of the HDO in the readout field. The readout field indicates horizontal period during which V2 and
V3 values take the ternary value.
SSI
00
01
02
03
04
05
06
07
08
31
32
33
34
35
36
37
38
39
SCK
SEN
Note that there are three main categories in serial interface data. Specifically, they are: CXD3611R drive
control data (control data), electronic shutter data (shutter data) and trigger shutter data (trigger data).
The following describes each in detail.
– 18 –
CXD3611R
Control Data
Data
D00
to
D07
Name
CHIP
D08,
CTG
D09
D10,
D11
—
Function
Chip enable
—
MODE
Drive mode switching
D15
CKMD
Base oscillation frequency
division switching∗1
—
OBCLP waveform pattern
switching
D22,
LDAD
D23
ADCLK logic phase switching
D24
FGOB
Vertical direction width OBCLP
generation switching∗2
D25
RGRS
RG pulse inversion switching
D26
to
D39
—
RST
All
0
00 → CTL
0
0
—
—
See the section on drive mode
0
0
All
0
2 frequency division
4 frequency division
0
—
—
All
0
—
D20,
PTOB
D21
Data = 1
10000001 → Enabled
Other values → Disabled
Category switching
D12
to
D14
D16
to
D19
Data = 0
See the section on OBCLP waveform patterns
1
0
See the section on ADCLK logic phase
1
0
ON
OFF
0
Posotive polarity
Negative polarity
0
—
—
All
0
—
∗1 See the section on drive mode
∗2 See the section on wide OBCLP generation
– 19 –
CXD3611R
Shutter Data
Data
D00
to
D07
Name
CHIP
D08,
CTG
D09
D10,
D11
Function
Data = 0
Chip enable
—
Electronic shutter mode
switching∗1
HTSG control switching∗1
RST
10000001 → Enabled
Other values → Disabled
All
0
01 → SHT
0
0
Category switching
—
Data = 1
—
—
0
OFF
ON
0
OFF
ON
0
D12
SMD
D13
HTSG
D14
to
D23
SVT
Electronic shutter vertical period
specification
See the section on electronic shutter
All
0
D24
to
D33
SHT
Electronic shutter horizontal
period specification
See the section on electronic shutter
All
0
D34
to
D39
—
—
—
—
All
0
Data = 0
Data = 1
RST
∗1 See the section on electronic shutter
Trigger Data
Data
D00
to
D07
Name
CHIP
D08,
CTG
D09
D10
to
D23
D24
to
D33
—
TSG
Function
Chip enable
10000001 → Enabled
Other values → Disabled
All
0
10 → TRIG
0
0
Category switching
—
—
Trigger shutter horizontal period
specification
D34
—
D35
TFINT
TSINT function switching∗1
D36
to
D39
TSINT
Trigger shutter fine adjustment
specification
—
See the section on trigger shutter
—
– 20 –
All
0
—
—
0
OFF
ON
0
See the section on trigger shutter
∗1 See the section on trigger shutter
All
0
All
0
CXD3611R
Detailed Description of Each Data
Shared data: D08 to D09 CTG [Category]
Of the data provided to the CXD3611R by the serial interface, the CXD3611R loads D10 and subsequent
data to each data register as shown in the table below according to the combination of D08 and D09 .
D09
D08
Description of operation
0
0
Loading to control data register
0
1
Loading to shutter data register
1
0
Loading to trigger data register
1
1
Test mode
Note that the CXD3611R can apply these categories consecutively within the same vertical period. However,
care should be taken as the data is overwritten if the same category is applied.
Control data: D20 to D21 PTOB [OBCLP waveform pattern]
This indicates the OBCLP waveform pattern. The default is "Normal". See the timing chart for details regarding
decode values.
D21
D20
0
0
0
Waveform pattern
ICX414/424
ICX415
(Normal)
11 to 31
11 to 36
1
(Shifted forward)
9 to 29
9 to 34
1
0
(Shifted rearward)
13 to 33
14 to 39
1
1
(Wide)
9 to 33
9 to 39
Control data: D24 FGOB [Vertical direction wide OBCLP generation]
This controls wide OBCLP generation during the vertical OPB period. When this function is turned ON,
D20 and D21 PTOB specification is disabled for the output. See the Timing Charts for the actual operation.
The default is "ON".
D24
Description of operation
0
Vertical direction wide OBCLP generation ON
1
Vertical direction wide OBCLP generation OFF
Control data: D22 to D23 LDAD [ADCLK logic phase]
This indicates the ADCLK logic phase adjustment data. The default is "90°" relative to MCKO.
D23
D22
Degree of adjustment (°)
0
0
0
0
1
90
1
0
180
1
1
270
– 21 –
CXD3611R
Control data: [Drive mode]
CXD3611R realizes various drive modes using the control data D12 to D14 MODE and CCD pins (Pin 4).
The following gives detailed descriptions. First, the basic drive modes are shown below. This uses of the
control data MODE D12 and D13 .
D13
D12
Description of operation
0
0
Progressive scan mode (default)
0
1
Central scan mode
1
0
Single field mode
1
1
Interlace mode
The progressive scan mode is a drive mode that reads out all of the line data of the CCD image sensor.
The central scan mode is a drive mode that uses the progressive scan mode as a base to read out the central
image in a high frame rate.
The interlace mode is a drive mode for outputting according to TV standards.
The single field mode is a drive mode for reading only single field of the aforementioned interlace mode.
Base on these, it uses MODE D14 to realize the following variations.
D13/D12
D14
0/0
0/1
1/0
1/1
0
Progressive Scan
Central scan 1
Single field 1
Interlace
1
Single field 3
Central scan 2
Single field 2
Single field 4
If D14 is allotted while D12 and D13 are in the central scan mode, it behaves in the following manner.
When D14 is "0", it drives in the pattern called central scan mode 1. When D14 is "1" it drives in the pattern
called central scan mode 2.
Other patterns are variations of the single field mode. To describe the items of the table, single field 1 drives by
repeating the ODD side of the interlace mode. Single field 3 drives by repeating the EVEN side of the interlace
mode. Single field 2 repeats the ODD side of the interlace mode, but if an NTSC standard CCD is used, it
enters a pattern to drive cutting the field applying 262.5H into HD units of 262H. Single field 4, in the same
way, enters a pattern to drive the EVEN side of the interlace mode in 262H units. However, these last two
modes are actually controls for the internal SSG, so when using an external sync, this function is not
guaranteed.
Depending on the pin control CCD, it switches to the ICX414/424 for NTSC (EIA) standard systems and to
ICX415 for PAL (CCIR) standard systems. See the timing chart for details regarding either drive mode.
Finally, as for the double-speed mode, it switches according to the D15 CKMD, but when realizing this drive
mode, set the base oscillation frequency to two times the normal speed. By switching using the parameters
above, normal and double speeds can be dually used. To switch this parameter with the base oscillation
frequency at its normal state, operation is in 1/2 speed drive mode, but the CCD operates outside of its
guarantee.
– 22 –
CXD3611R
Control data/shutter data: [Electronic shutter]
The CXD3611R realizes various electronic shutter functions by using shutter data D12 SMD, D13 HTSG,
D14 to D23 SVT, and D24 to D33 SHT.
These functions are described in detail below.
First, the various modes are shown below. These modes are switched using shutter data D12 SMD.
D12
Description of operation
0
Electronic shutter stopped mode
1
Electronic shutter mode
The electronic shutter data is expressed as shown in the table below using D24 to D35 SHT as an example.
MSB
LSB
D33 D32 D31 D30
0
↓
1
1
1
1
D29 D28 D27 D26
↓
C
0
0
0
0
D25 D24
↓
3
1
1
→ Expressed as IC3h .
[Electronic shutter stopped mode]
During this mode, all shutter data items are invalid.
SUB is not output in this mode, so the shutter speed is the accumulation time for one field.
[Electronic shutter mode]
During this mode, the shutter data items have the following meanings.
Name
Data
Description
SVT
Shutter: D14 to D23
Number of vertical periods specification (000h ≤ SVT ≤ 3FFh)
SHT
Shutter: D24 to D33
Number of horizontal periods specification (000h ≤ SHT ≤ 3FFh)
Note) The bit data definition area is assured in terms of the CXD3611R functions, and does not assure the
CCD characteristics.
The period during which SVT and SHT are specified together is the shutter speed. The exposure time
calculation formula is shown below. In actual operation, the precise exposure time is calculated from the
operating frequency, VD and HD periods, decoding value during the horizontal period, and other factors.
(Exposure time) = SVT × (1V period) + {(number of HD per 1V) – (SHT + 1)} × (1H period)
+ (the distance from SUB falling edge of the readout period to the SG falling edge)
Concretely, when specifying high-speed shutter, SVT is set to "000h". (See the figure.) During low-speed
shutter, or in other words when SVT is set to "001h" or higher, the serial interface data is not loaded until this
period is finished.
The vertical period indicated here corresponds to one field in each drive mode. In addition, the number of
horizontal periods applied to SHT can be considered as (number of SUB pulses – 1). Also, the readout period
is the normal horizontal period during which V2 and V3 values take the ternary value and SG indicates the
readout pulse for the third value.
– 23 –
CXD3611R
VDO
SVT
SHT
V3
SUB
WEN
SMD
1
1
SVT
002h
000h
SHT
10Fh
050h
Exposure time
[HTSG control mode]
This mode controls the V2, V3 ternary values output (readout pulse block) using D13 HTSG.
However, when D12 SMD is in the electronic shutter mode, note that this operation is not guaranteed.
D13
Description of operation
0
Readout pulse (SG) normal operation
1
HTSG control mode
VDO
V3
SUB
WEN
SMD
1
0
1
HTSG
0
1
0
Exposure time
– 24 –
CXD3611R
Trigger data: [Trigger shutter]
The CXD3611R realizes trigger shutter functions by using trigger data D24 TSG, D35 TFINT and D36 to
D39 TSINT and RDM (Pin 34), TRG (Pin 35) and ESG (Pin 36).
These functions are described in detail below.
First, the basic sequences of the trigger shutter function are shown below.
Trigger shutter period
WAIT
Exposure period
Transfer period
RDM
TRG
ESG
VDO
V3
SUB
Exposure time
Initially, it enters a WAIT period from a horizontal period immediately following the falling edge of the RDM to
begin high speed sweeping. At this time, SUB also generates horizontal periods simultaneously.
Next, immediately following the falling edge of TRG, it enters the exposure period from the horizontal period.
High speed sweeping that had been generated up to that point is stopped whereat normal transfers begin.
Simultaneously, SUB also ceases. The final SUB pulse specified is generated immediately following the falling
edge of TRG. At this time, the settings of D36 to D39 TSINT are reflected enabling fine adjustments of the
ultra-high speed shutter exposure time. However, only when D35 TFINT is set to ON, this function enables
the internal counter and allows its use. See the table below for details regarding the adjustment data.
Next, immediately following the falling edge of the ESG, a readout pulse is generated in the horizontal period to
set the exposure time. Then, data transfer occurs in sync to the next VD period, but normal transfers stop up to
that point. Also, the readout pulse position can be specified using serial control. The positions counted as 0, 1,
2, ... from the horizontal period immediately following the falling edge of TRG, while the ESG is fixed to a high
state, are specified using D24 to D33 TSG. However, parallel control has priority, so when executed from
serial to parallel, it is possible to output the readout pulse twice in the same exposure time. However,
operations in this situation are not guaranteed, so be careful of the sequences.
Note that it is presumed that the drive mode specified in the transfer period is either the progressive scan
mode or the central scan mode systems. If the drive mode is set to something else, operations are not
guaranteed. Furthermore, be aware that readout pulse outputs will be aborted. Normal SUB output is accepted
from the transfer period. Also, this IC will not respond even if only TRG is applied. Always combine a sequence
that uses RDM and TRG as a set. In other words, when omitting the high speed sweeping, RDM and TRG
should be applied simultaneously.
– 25 –
CXD3611R
[Trigger shutter fine adjustment data]
0
780 or 944
HDO
SUB
A
B
C
D
E
H
I
J
K
L
[For ICX414/424]
Position D39
D38 D37 D36
Descending position
95∗1
A
0
0
0
0
Ascending position
72∗1
B
0
0
0
1
137
160
C
0
0
1
0
202
225
D
0
0
1
1
267
290
E
0
1
0
0
332
355
F
0
1
0
1
397
420
G
0
1
1
0
462
485
H
0
1
1
1
527
550
I
1
0
0
0
592
615
J
1
0
0
1
657
680
K
1
0
1
0
L
1
0
1
1
722
7 ∗2
745
30∗2
—
Remainder is invalid
—
—
Descending position
122∗1
[For ICX415]
Position D39
D38 D37 D36
A
0
0
0
0
Ascending position
99∗1
B
0
0
0
1
177
200
C
0
0
1
0
255
278
D
0
0
1
1
333
356
E
0
1
0
0
411
434
F
0
1
0
1
489
512
G
0
1
1
0
567
590
H
0
1
1
1
645
668
I
1
0
0
0
723
746
J
1
0
0
1
801
824
K
1
0
1
0
L
1
0
1
1
879
13∗3
902
36∗3
—
Remainder is invalid
—
—
Note) Position data represents the counted values from the falling edge of the HRO to the rising edge of the
MCKO.
∗1 Default timings for each drive mode.
∗2 This timing has a variable point in the 780ck cycle HDO.
∗3 This timing has a variable point in the 944ck cycle HDO.
– 26 –
– 27 –
8
9
10
A
Progressive Scan Mode (Non-interlace)
23
15
1 2 3 4 5 6 7 8 1 2
A
9
10
6
524
0
519
6
518
490
491
492
493
494
1 2 3 4 5 6 7 8 1 2
• ICX414/424
Applicable CCD image sensor
∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
∗ VR in this chart is described in 525H (1H: 780ck) units.
WEN
CLPDM
OBCLP
PBLK
CCD OUT
V3
V2
V1
SUB
HDO
VDO
524
0
1
MODE
516
491
492
493
494
Vertical Direction Timing Chart
1
Chart-1
CXD3611R
– 28 –
C
A
8
9
10
261
0
1
B
Central Scan 1 Mode
MODE
136
137
31
29
23
C
A
• ICX414/424
Applicable CCD image sensor
9
7
261
0
1
16
13
14
∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
∗ VDO in this chart is described in 262H (1H: 780ck) units.
∗ Valid line count in this drive mode: 222 lines
WEN
CLPDM
OBCLP
PBLK
CCD OUT
V3
V2
V1
SUB
HDO
253
254
355
356
357
VDO
Vertical Direction Timing Chart
1
253
356
357
B
15
1
Chart-2
CXD3611R
– 29 –
C
A
B
C
6
130
0
1
9
10
6
129
130
0
1
A
• ICX414/424
∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
∗ VDO in this chart is described in 131H (1H: 780ck) units.
∗ Valid line count in this drive mode: 76 lines
WEN
CLPDM
OBCLP
PBLK
CCD OUT
V3
V2
V1
SUB
HDO
VDO
Central Scan 2 Mode
35
Applicable CCD image sensor
9
MODE
38
209
210
211
Vertical Direction Timing Chart
113
114
282
283
284
15
16
1
113
114
282
283
284
B
15
16
1
Chart-3
CXD3611R
– 30 –
520
8
9
10
D
16
13
2 4 6 8 2 4 6
1 3 5 7 1 3 5
Pixel Add Mode (Interlace)
MODE
270
D
1 3 5 7 1 3 5
2 4 6 8 2 4 6
278
274
264
6
• ICX414/424
Applicable CCD image sensor
∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
∗ VDO in this chart is described in 262H (1H: 780ck) units.
BLK
SYNC
WEN
CLPDM
OBCLP
PBLK
CCD OUT
V3
V2
V1
SUB
HDO
524
0
1
2
489 490
491 492
493 494
VDO
Vertical Direction Timing Chart
262
263
489
490 491
492 493
494
Chart-4
CXD3611R
– 31 –
WEN
CLPDM
Wide OBCLP
OBCLP (4)
OBCLP (3)
OBCLP (2)
OBCLP (1)
PBLK
SUB
V3
V2
V1
H2
H1
MCKO
HDO
Chart-5
4
(780)
0
9
9
11
13
29
33
33
33
31
35
35
35
Horizontal Direction Timing Chart
47
50
59
72
71
78
83
93
95
95
109
107
119
123
120
123 125
120
150
200
• ICX414/424
Progressive Scan Mode
100
Applicable CCD image sensor
MODE
CXD3611R
– 32 –
WEN
CLPDM
OBCLP
PBLK
SUB
V3
V2
V1
H2
H1
MCKO
HDO
Chart-6
#142 (14H)
#215 (20H)
Central Scan 2
Frame Shift
35
35
Central Scan 1
4
(780)
0
50
59
#1
72
71
78
#255 (24H)
#167 (16H)
High Speed Sweep
47
Horizontal Direction Timing Chart
(Frame shift: B)
(High speed sweeping: C)
83
95
95
107
107
100
119
123 125
120
131
#2
143
150
155
MODE
Central Scan 1 Mode, Central Scan 2 Mode
167
179
191
• ICX414/424
#3
203
200
215
Applicable CCD image sensor
CXD3611R
– 33 –
WEN
CLPDM
Wide OBCLP
OBCLP (4)
OBCLP (3)
OBCLP (2)
OBCLP (1)
PBLK
SUB
V3
V2
V1
H2
H1
MCKO
HDO
Chart-7
4
(780)
0
9
9
11
13
29
33
33
33
31
35
35
35
41
Horizontal Direction Timing Chart
47
53
50
59
65
72
71
77
78
83
89
93
95
95
109
101
107
119
123
120
123 125
120
150
200
• ICX414/424
Pixel Add Mode (Interlace Mode)
100
Applicable CCD image sensor
MODE
CXD3611R
V3
V2
V1
HDO
(780)
0
632
582
107
95
83
71
59
47
35
(780)
0
71
59
• ICX414/424
Applicable CCD image sensor
83
MODE
Progressive Scan Mode
95
Horizontal Direction Timing Chart
(Readout: A)
107
Chart-8
CXD3611R
– 34 –
47
35
520
– 35 –
V3
V2
V1
HDO
Even Field
V3
V2
V1
HDO
Odd Field
(780)
0
(780)
0
582
520
35
41
47
53
59
65
71
77
83
89
95
101
107
113
119
125
131
137
MODE
Pixel Add Mode (Interlace)
632
Horizontal Direction Timing Chart
Readout: D
(780)
0
(780)
0
• ICX414/424
Applicable CCD image sensor
35
41
47
53
59
65
71
77
83
89
95
101
107
113
Chart-9
CXD3611R
– 36 –
18
18
18
(780)
0
48
78
78
132
Horizontal Direction Timing Chart
(SSG Pulse)
348
408
408
438
MODE
Pixel Add Mode (Interlace)
738
∗ HSYNC, EQ and VSYNC are combined and output from the SYNC pin. They are not individual pulses output externally.
VSYNC
EQ
HSYNC
BLK
HDO
Chart-10
(780)
0
18
78
78
132
• ICX414/424
Applicable CCD image sensor
CXD3611R
– 37 –
E
28
20
1 2 3 4 5 6 7 8 1 2
E
14
9
10
624
0
611
14
8
9
10
624
0
609
578
579
580
581
582
• ICX415
∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
∗ VDO in this chart is described in 625H (1H: 944ck) units.
WEN
CLPDM
OBCLP
PBLK
CCD OUT
V3
V2
V1
SUB
HDO
VDO
Progressive Scan Mode (Non-Interlace)
1
Applicable CCD image sensor
1 2 3 4 5 6 7 8 1 2
20
MODE
609
581
582
Vertical Direction Timing Chart
28
Chart-11
CXD3611R
– 38 –
G
E
F
G
E
• ICX415
14
8
9
0
1
311
14
8
9
311
0
1
∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
∗ VDO in this chart is described in 312H (1H: 944ck) units.
∗ Valid line count in this drive mode: 264 lines
WEN
CLPDM
OBCLP
PBLK
CCD OUT
V3
V2
V1
SUB
HDO
Central Scan 1 Mode
37
Applicable CCD image sensor
F
37
MODE
40
160
161
162
VDO
303
421
422
423
20
1
303
422
423
20
1
Vertical Direction Timing Chart
40
157
Chart-12
CXD3611R
– 39 –
G
E
F
G
• ICX415
9
6
155
0
1
14
8
9
155
0
1
∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
∗ VDO in this chart is described in 156H (1H: 944ck) units.
∗ Valid line count in this drive mode: 88 lines
WEN
CLPDM
OBCLP
PBLK
CCD OUT
V3
V2
V1
SUB
HDO
Central Scan 2 Mode
46
E
Applicable CCD image sensor
15
MODE
49
248
249
250
VDO
136
333
334
335
20
1
136
137
333
334
335
Vertical Direction Timing Chart
1
Chart-13
CXD3611R
– 40 –
H
17
2 4 6 8 2 4 6
1 3 5 7 1 3 5
21
14
10
8
H
18
• ICX415
Applicable CCD image sensor
1 3 5 7 1 3 5
2 4 6 8 2 4 6
∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
∗ VDO in this chart is described in 3125H (1H: 944ck) units.
BLK
SYNC
WEN
CLPDM
OBCLP
PBLK
CCD OUT
V3
V2
V1
SUB
577 578
579 580
581 582
1 2 3 4 5 6 7 8 9 10 11 12 13 14
314
312
312
313
577
578 579
580 581
582
HDO
320
VDO
624
0
1
2
Pixel Add Mode (Interlace)
327
MODE
331
Vertical Direction Timing Chart
335
Chart-14
CXD3611R
– 41 –
WEN
CLPDM
Wide OBCLP
OBCLP (4)
OBCLP (3)
OBCLP (2)
OBCLP (1)
PBLK
SUB
V3
V2
V1
H2
H1
MCKO
HDO
Chart-15
4
(944)
0
9
9
14
11
34
39
39
39
36
42
42
42
Horizontal Direction Timing Chart
50
58
74
90
99
100
106
102
120
122
122
120
145
144
155
155
150
163
163 166
200
205
• ICX415
Progressive Scan Mode
80
Applicable CCD image sensor
MODE
CXD3611R
– 42 –
WEN
CLPDM
OBCLP
PBLK
SUB
V3
V2
V1
H2
H1
MCKO
HDO
Chart-16
#166 (17H)
#254 (26H)
Central Scan 2
Frame Shift
Central Scan 1
4
(944)
0
50
58
74
#299 (31H)
#197 (20H)
High speed Sweep
42
42
Horizontal Direction Timing Chart
(Frame shift: F)
(High speed sweeping: G)
80
#1
90
99
100
106
102
122
122
120
138
144
154
150
MODE
Central Scan 1 Mode, Central Scan 2 Mode
170
163 166
#2
186
• ICX415
202
200
Applicable CCD image sensor
CXD3611R
– 43 –
WEN
CLPDM
Wide OBCLP
OBCLP (4)
OBCLP (3)
OBCLP (2)
OBCLP (1)
PBLK
SUB
V3
V2
V1
H2
H1
MCKO
HDO
Chart-17
4
(944)
0
9
9
14
11
34
39
39
39
36
42
42
42
Horizontal Direction Timing Chart
50
50
58
66
74
82
90
99
98
100
106
102
114
120
122
130
122
120
145
144
155
155
150
163
163 166
200
205
• ICX415
Pixel Add Mode (Interlace)
80
Applicable CCD image sensor
MODE
CXD3611R
V3
V2
V1
HDO
(944)
0
(944)
0
58
775
701
122
106
90
74
58
42
• ICX415
122
106
Applicable CCD image sensor
74
MODE
Progressive Scan Mode
90
Horizontal Direction Timing Chart
(Readout: E)
138
Chart-18
CXD3611R
– 44 –
42
627
138
– 45 –
V3
V2
V1
HDO
Even Field
V3
V2
V1
HDO
Odd Field
(944)
0
(944)
0
701
627
42
50
58
66
74
82
90
98
106
114
122
130
138
146
154
162
170
178
MODE
Pixel Add Mode (Interlace)
775
Horizontal Direction Timing Chart
(Readout: H)
(944)
0
(944)
0
• ICX415
Applicable CCD image sensor
42
50
58
66
74
82
90
98
106
114
122
130
138
146
Chart-19
CXD3611R
– 46 –
(944)
0
22
22
22
58
95
102
177
Horizontal Direction Timing Chart
(SSG Pulse)
421
494
494
530
MODE
Pixel Add Mode (Interlace)
893
∗ HSYNC, EQ and VSYNC are combined and output from the SYNC pin. They are not individual pulses output externally.
VSYNC
EQ
HSYNC
BLK
HDO
Chart-20
22
22
22
(944)
0
58
95
102
• ICX415
177
Applicable CCD image sensor
CXD3611R
– 47 –
High-Speed Phase Timing Chart
1
MODE
35/42
∗ HDO indicates the logical positional relationship when an H-Reset is applied to CXD3611R by HDI. The actual output requires a delay.
∗ The phase relationship of each pulse shows the logical position relationship. For the actual output, a delay is added to each pulse.
∗ The logical ADCLK can be specified by the serial interface data.
∗ Pin settings are in default.
XRS
XSHD
XSHP
RG
H2
H1
MCKO
ADCLK
CKI
HDO
HDI
Chart-21
107/144
• ICX414/424/415
Applicable CCD image sensor
CXD3611R
CXD3611R
Application Circuit Block Diagram
H2
RG
V1
V2
V3
34 35 36
16
29
17
44
14
45
52
46
54
47
58
42
15V
TG
CXD3611R
43
41
SUB
62
49
2
3
11
12
HDI
VDI
VDO
HDO
BLK
SYNC
WEN
RST
SNCSL
SSGSL
HDRS
CDSRS
SMD1 to 3
MD1 to 3
CCD
PS
SEN
SCK
38 39 40 37 4
SSI
30
CKI∗2
31
OSCO
32
OSCI
∗1 H-Dr is required when actually
using a double speed drive mode.
∗2 Always input CKI using a sine wave
below amplitude VDD.
∗3 The figure shows an application
circuit block diagram corresponding
to the use of an oscillator.
MCKO
Signal Processor Block
H-Dr∗1
64
RDM
TEST
ADCLK
OBCLP
CLPDM
PBLK
XRS
XSHP
20 21 22 23 24 25 26
H1
ESG
Digital OUT
CDS/ADC
CXD3301R
TRG
CCD OUT
XSHD
CCD
ICX414/415/424
Micon
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Notes on Power-on
Of the three –7.5V, +15.0V, +3.3V power supplies, be sure to start up the –7.5V and +15.0V power supplies in
the following order to prevent the SUB pin of the CCD image sensor from going to negative potential.
15.0V
t1
20%
0V
20%
t2
t2 ≥ t1
–7.5V
– 48 –
CXD3611R
Package Outline
Unit: mm
64PIN LQFP (PLASTIC)
12.0 ± 0.2
∗
10.0 ± 0.1
48
33
32
64
17
(0.22)
0.5 ± 0.2
(11.0)
49
A
16
1
0.5
b
0.13 M
+ 0.2
1.5 – 0.1
0.1
0.1 ± 0.1
0.5 ± 0.2
0˚ to 10˚
0.125 ± 0.04
b = 0.18 ± 0.03
DETAIL B: PALLADIUM
DETAIL A
NOTE: Dimension “∗” does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
LQFP-64P-L01
LEAD TREATMENT
PALLADIUM PLATING
EIAJ CODE
P-LQFP64-10x10-0.5
LEAD MATERIAL
COPPER ALLOY
PACKAGE MASS
0.3g
JEDEC CODE
– 49 –
Sony Corporation