CXD2412AQ Timing Generator for LCD Panels Description The CXD2412AQ is a timing signal generator for LCD panel drivers. 100 pin QFP (Plastic) Features • Generates the LCX007 drive pulse. • Supports NTSC/PAL. (With PAL, a video signal on which scanning line conversion has been performed is used.) • Supports WIDE. • Supports HD (20 MHz band). • Supports Muse-NTSC conversion signal (MNDC). • Supports up/down and/or right/left inversion. • Supports three-panel projector. • Generates timing signal of external sample-andhold circuit. • Generates line inversion and field inversion signals. • AC drive for LCD panel during no signal. • AFC circuit supporting static and dynamic fluctuations. Applications LCD projectors Structure Silicon gate CMOS IC Absolute Maximum Ratings (Ta = 25 °C) • • • • • Supply voltage Input voltage Output voltage Operating temperature Storage temperature VDD VSS–0.5 to +7.0 V VI VSS – 0.5 to VDD + 0.5 V VO VSS – 0.5 to VDD + 0.5 V Topr –20 to +75 °C Tstg –55 to +150 °C Recommended Operating Conditions • Supply voltage VDD 5.0 ± 0.5 • Operating temperature Topr –20 to +75 V °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E94Y04-ST CXD2412AQ Block Diagram RPD1 9 7 RPD2 86 RPD3 94 FPD1 FPD3 97 TC1 LOOP FILTER 6 FPD2 83 48 N.C. TC3 98 2 CKI1 12 PWM1 51 N.C. 52 N.C. PLL-COUNTER HSYNC 16 1 8 96 PWM3 5 N.C. 95 PEO3 85 PWM2 PHASE COMPARATOR TC2 82 N.C. PEO1 84 PEO2 H-SYNC DETECTOR H-SKEW DETECTOR 55 N.C. 56 N.C. HALF-H KILLER 57 N.C. 58 N.C. CKI2 89 59 N.C. CKI3 92 60 N.C. CKO1 11 75 SLFR FIELD & LINE CONTROLLER CKO2 88 CKO3 91 47 DWN VSYNC 17 TST6 14 TST1 24 TST2 25 32 RGT 33 XRGT 61 FRP V-SYNC SEPERATER (NOISE SHAPE) 18 HP1 19 HP2 TST3 26 20 HP3 TST4 27 21 HP4 TST5 30 22 HP5 XCLR 31 23 HP6 VP1 49 VP2 50 74 PCGW V-TIMING PULSE GENERATOR 71 SLSH1 VST 46 72 SLSH2 SLAUX 73 VSS0 81 SLSH3 4 99 CP1 VSS1 10 100 CP2 VSS2 13 36 HCK1A H-TIMING PULSE GENERATOR VSS3 15 VSS4 29 37 HCK2A 38 HCK1B VSS5 40 39 HCK2B VSS6 54 34 HSTA VSS7 65 41 HSTB VSS8 79 42 CLR VSS10 87 43 ENB VSS11 90 44 VCK VSS12 93 45 PCG 3 62 XCLP1 VDD1 28 63 XCLP2 VDD2 35 64 PRG VDD3 53 66 SH1 VDD4 70 67 SH2 VDD0 68 SH3 VDD5 78 69 SH4 76 NTPL 77 XWD 80 XHD –2– CXD2412AQ Pin Description Pin No. Input pin for open status Symbol I/O 1 N.C. — Not connected 2 N.C. — Not connected 3 VDD0 — Power supply 4 VSS0 — GND 5 TC1 I FPD1 pin pulse width adjustment 6 FPD1 O Phase comparator output B-1 (for NTSC/PAL) 7 PEO1 O Loop filter integrator output 1 8 PWM1 I Loop filter integrator input 1 9 RPD1 O Phase comparator output A-1 (for NTSC/PAL) 10 VSS1 — GND 11 CKO1 O NTSC/PAL oscillation cell output 12 CKI1 I NTSC/PAL oscillation cell input 13 VSS2 — GND 14 TST6 I Test 15 VSS3 — GND 16 HSYNC I Hsync input (negative polarity) 17 VSYNC I Vsync input (negative polarity) 18 HP1 I Switches for the horizontal display start position L 19 HP2 I Switches for the horizontal display start position L 20 HP3 I Switches for the horizontal display start position L 21 HP4 I Switches for the horizontal display start position L 22 HP5 I Switches for the horizontal display start position L 23 HP6 I Switches for the horizontal display start position H 24 TST1 I Test L 25 TST2 I Test L 26 TST3 I Test L 27 TST4 I Test L 28 VDD1 — Power supply 29 VSS4 — GND 30 TST5 I Test H 31 XCLR I Cleared at 0 V H 32 RGT I Right/left inversion identification signal input H 33 XRGT O Right/left inversion identification signal output 34 HSTA O H start pulse A 35 VDD2 — Power supply 36 HCK1A O H clock pulse 1A 37 HCK2A O H clock pulse 2A Description L –3– CXD2412AQ Input pin for open status Pin No. Symbol I/O 38 HCK1B O H clock pulse 1B 39 HCK2B O H clock pulse 2B 40 VSS5 — GND 41 HSTB O H start pulse B 42 CLR O Clear pulse 43 ENB O Enable pulse 44 VCK O V clock pulse 45 PCG O Precharge pulse 46 VST O V start pulse 47 DWN I Up/down inversion identification signal input 48 N.C. — 49 VP1 I Switches for the vertical display start position L 50 VP2 I Switches for the vertical display start position H 51 N.C. — Not connected 52 N.C. — Not connected 53 VDD3 — Power supply 54 VSS6 — GND 55 N.C. — Not connected 56 N.C. — Not connected 57 N.C. — Not connected 58 N.C. — Not connected 59 N.C. — Not connected 60 N.C. — Not connected 61 FRP O AC drive inversion timing output 62 XCLP1 O Video signal pedestal clamp pulse 1 63 XCLP2 O Video signal pedestal clamp pulse 2 64 PRG O Precharge signal pulse 65 VSS7 — GND 66 SH1 O Sample-and-hold pulse 1 67 SH2 O Sample-and-hold pulse 2 68 SH3 O Sample-and-hold pulse 3 69 SH4 O Resample-and-hold pulse 70 VDD4 — Power supply 71 SLSH1 I Switches SH L 72 SLSH2 I Switches SH L 73 SLAUX I Switches free-running identification line number H 74 PCGW I Switches PCG H Description H Not connected –4– CXD2412AQ Pin No. Symbol I/O Description Input pin for open status 75 SLFR I Switches between H inversion and F inversion (H: H inversion / L: F inversion) H 76 NTPL I Switches mode H 77 XWD I Switches mode H 78 VDD5 — Power supply 79 VSS8 — GND 80 XHD I Switches mode H 81 SLSH3 I Switches SH L 82 TC2 I FPD2 pin pulse width adjustment 83 FPD2 O Phase comparator output B-2 (for WIDE) 84 PEO2 O Loop filter integrator output 2 85 PWM2 I Loop filter integrator input 2 86 RPD2 O Phase comparator output A-2 (for WIDE) 87 VSS10 — GND 88 CKO2 O WIDE oscillation cell output 89 CKI2 I WIDE oscillation cell input 90 VSS11 — GND 91 CKO3 O HD/MNDC oscillation cell output 92 CKI3 I HD/MNDC oscillation cell input 93 VSS12 — GND 94 RPD3 O Phase comparator output A-3 (for HD/MNDC) 95 PEO3 O Loop filter integrator output 3 96 PWM3 I Loop filter integrator input 3 97 FPD3 O Phase comparator output B-3 (for HD/MNDC) 98 TC3 I FPD3 pin pulse width adjustment 99 CP1 I Switches pedestal clamp position H 100 CP2 I Switches pedestal clamp position L –5– CXD2412AQ Electrical Characteristics 1. DC characteristics Item (Temperature = 25°C, Vss = 0V) Symbol Conditions Supply voltage VDD Input voltage VIH TTL input cell Input voltage VIL TTL input cell Input voltage VIH CMOS input cell Input voltage VIL CMOS input cell Output voltage VOH IOH = –4mA (HCKl, SHm) Output voltage VOL IOL = 8mA (HCKl, SHm) Output voltage VOH IOH = –3mA (CKOn, CKIn) Output voltage VOL IOL = 3mA (CKOn, CKIn) Output voltage VOH IOH = –2mA (other than the above) Output voltage VOL IOL = 4mA (other than the above) Input leak current IIL Pull-up resistor connected –40 Input leak current IIH Pull-down resistor connected –40 Output leak current ILZ RPDn, FPDn (at high impedance state) –40 Current consumption IDD Typ. Min. 4.5 Unit 5.5 V V 2.2 0.8 V V 0.7VDD 0.3VDD V V VDD – 0.8 0.4 V V VDD/2 VDD/2 V V VDD – 0.8 0.4 V –100 –240 µA 100 240 µA 40 µA 75 HD mode, VDD = 5.0V (at no load) mA (VDD = 5.0 ± 10%) 2. AC characteristics Item Max. Applicable pins Symbol Conditions Min. Typ. Max. Unit 22 ns Clock input cycle CKIn Cross point time difference HCK1A, HCK2A ∆t CL = 30pF 10 ns Cross point time difference HCK1B, HCK2B ∆t CL = 30pF 10 ns Output rise delay HCKl, SHm tpr CL = 30pF 20 ns Output fall delay HCKl, SHm tpf CL = 30pF 15 ns Output rise delay Other than HCK1 and SHm tpr CL = 30pF 25 ns Output fall delay Other than HCK1 and SHm tpf CL = 30pF 15 ns HCK1, SH1 delay time difference HCK1A, HCK1B, SH1 dt1 CL = 30pF 0.05 0.25 ns HCK1, SH1 delay time difference HCK1A, HCK1B, SH1 dt2 CL = 30pF 1 5 ns HCK2, SH1 delay time difference HCK2A, HCK2B, SH1 dt1 CL = 30pF 0.1 0.5 ns HCK2, SH1 delay time difference HCK2A, HCK2B, SH1 dt2 CL = 30pF 1 5 ns HCK1 Duty HCK1A, HCK1B tH/tH + tL CL = 30pF 45 52 % HCK2 Duty HCK2A, HCK1B tH/tH + tL CL = 30pF 45 52 % Note) l = 1A, 1B, 2A, 2B n = 1, 2, 3 m = 1, 2, 3, 4 –6– CXD2412AQ Timing Definition VDD CK1 0V VDD Output 0V tpr VDD Output 0V tpf VDD HCK1A (HCK2A) 50% 50% 0V VDD HCK1B (HCK2B) 50% 50% 0V ∆t ∆t t t CK1 HCK1A 1B 2A 2B 50% 50% t1 tH SH1 t2 tL 50% dt1 50% 50% dt2 –7– –8– 3 480 3 479 480 4 3 2 1 DL2 DL3 DL4 1 2 46 311 312 313 314 Side Black 356 357 GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW 48 ODD = 135 EVEN = 134 DR2 DR3 DR4 GATE SW GATE SW GATE SW GATE SW DR1 ODD = 13 EVEN = 13 R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R R G B R G B R G B R G B R G B R G B R G B G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R R G B R G B R G B R G B R G B R G B R G B G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R R G B R G B R G B R G B R G B R G B R G B G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R R G B R G B R G B R G B R G B R G B R G B G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R R G B R G B R G B R G B R G B R G B R G B G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R R G B R G B R G B R G B R G B R G B R G B G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R AA AA AA A 47 4:3 Area 45 Side Black 44 ODD = 799 EVEN = 800 ODD = 1069 EVEN = 1068 ODD = 135 EVEN = 134 GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW DL1 ODD = 13 EVEN = 14 ODD = 1094 EVEN = 1095 The structure of LCD panels driven by this IC is shown below. Dot Arrangement (1) (16 : 9 display) The dots are arranged in a delta pattern. The shaded area is used for the dark border around the display. The R corresponds to SIG2, G to SIG1, and B to SIG3, respectively. LCD Panel Structure CXD2412AQ –9– 3 480 3 479 480 4 3 2 1 DL2 DL3 DL4 1 2 46 47 311 312 313 314 Side Black ODD = 135 EVEN = 134 356 357 DR2 DR3 DR4 GATE SW GATE SW GATE SW GATE SW DR1 ODD = 13 EVEN = 13 R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R R G B R G B R G B R G B R G B R G B R G B G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R R G B R G B R G B R G B R G B R G B R G B G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R R G B R G B R G B R G B R G B R G B R G B G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R R G B R G B R G B R G B R G B R G B R G B G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R R G B R G B R G B R G B R G B R G B R G B G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R R G B R G B R G B R G B R G B R G B R G B G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW 48 4:3 Area 45 Side Black 44 ODD = 799 EVEN = 800 ODD = 1069 EVEN = 1068 ODD = 135 EVEN = 134 GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW DL1 ODD = 13 EVEN = 14 ODD = 1094 EVEN = 1095 Dot Arrangement (2) (4 : 3 display) The dots are arranged in a delta pattern. The shaded area is used for the dark border around the display. The R corresponds to SIG2, G to SIG1, and B to SIG3, respectively. CXD2412AQ CXD2412AQ Input Signal Specifications 1. Horizontal sync signal • With NTSC, NTSC WIDE, PAL, PAL+, and MNDC, the standard signal is doubled in speed, and a 1/2 cycle, 1/2 width horizontal sync signal (H.SYNC) is input. • With HD, a signal derived by cutting off the lower part of 3-value sync is input. • Negative polarity input is used. 2. Vertical sync signal • V.sync separated by synchronizing separation circuit and not doubled in speed is input as the vertical sync signal. • Negative polarity input is used. • With this TG, the phase relationship between VSYNC and HSYNC is as follows; (1) NTSC/NTSC WIDE/MNDC Phase reference HSYNC (Double-speed H.sync) VSYNC (2) PAL/PAL+ Phase reference HSYNC (Double-speed H.sync ) VSYNC The video signal has a 487-line effective period due to scanning line conversion. (3) HD ODD FIELD HSYNC VSYNC EVEN FIELD Phase reference HSYNC VSYNC – 10 – CXD2412AQ Mode Selection Mode selection is performed by means of three pins, as shown in the table. NTPL XWD XHD Mode H H H NTSC L H H PAL H L H NTSC WIDE L L H PAL+ L X L HD H X L MNDC – 11 – CXD2412AQ SH Pulse Switching The phase relationship between HCK1A, HCK1B and SH1, SH2, SH3, SH4 is switched by SLSH1, SLSH2, SLSH3. SLSH1 = L SLSH2 = L SLSH3 = L SLSH1 = H SLSH2 = L SLSH3 = L Right scan driver RGT = H HCK1A (HCK1B) SH1 SH2 SH3 SH4 Left scan driver RGT = L HCK1A (HCK1B) SH1 SH2 SH3 SH4 – 12 – SLSH1 = L SLSH2 = H SLSH3 = L SLSH1 = H SLSH2 = H SLSH3 = L CXD2412AQ SLSH1 = L SLSH2 = L SLSH3 = H SLSH1 = H SLSH2 = L SLSH3 = H Right scan driver RGT = H HCK1A (HCK1B) SH1 SH2 SH3 SH4 Left scan driver RGT = L HCK1A (HCK1B) SH1 SH2 SH3 SH4 – 13 – SLSH1 = L SLSH2 = H SLSH3 = H SLSH1 = H SLSH2 = H SLSH3 = H CXD2412AQ Right/Left Inversion and Up/Down Inversion The LCD panel is arranged in a delta pattern, where an identical signal line is 1.5-dot offset for every horizontal line. For this reason, a 1.5-bit offset is made to the horizontal start pulse HST of the LCD between lines. HCK and S/H (sample and hold) are also 1.5-bit offset in a similar manner. When the panel is driven with right/left inversion or up/down inversion, this offset relationship becomes inverted for even and odd lines. Moreover, since the dot arrangement is asymmetrical, the HST position is also offset. Right/left inversion and up/down inversion are supported by the TG as follows. (1) Two types of output pulses for right scan (A output) and left scan (B output) are prepared for HST, HCK to allow right/left inversion present/absent mixed three-panel LCDs to be driven simultaneously. In addition, XRGT (RGT inverse output) is prepared for the left scan panel. SH1 and SH3 connections to the driver are reversed for sample-and-hold. (2) Left scan pulses are output to the A output by setting the right/left inversion input pin RGT to low. Also, XRGT is driven high by setting RGT to low. (3) The A and B outputs output up scan pulses by setting the up/down inversion input pin DWN to low. Right scan Left scan Right/left inversion compatible SH wiring diagram SH1 SH2 H SCANNER SH3 SH1 A output driver SH4 SH2 TG V SCANNER Down scan SH3 SH4 Display area SH1 SH2 Up scan SH3 SH4 The relationship between the output pins and switches is summarized below. TG input pin A output HST, HCK B output HST, HCK (Three-panel LCD auxiliary output) DWN RGT H H For right scan, down scan For left scan, down scan H L For left scan, down scan For right scan, down scan L H For right scan, up scan For left scan, up scan L L For left scan, up scan For right scan, up scan – 14 – B output driver CXD2412AQ Horizontal Output Pulses The HST pulses are offset for each line in accordance with the dot arrangement. Video start MCK –2fh HSTn n = A.B 16 : 9, right, down scan, odd line 16 : 9, left, down scan, odd line 16 : 9, right, up scan, even line 16 : 9, left, up scan, even line –3.5fh 16 : 9, right, down scan, even line 16 : 9, right, up scan, odd line –0.5fh 16 : 9, left, down scan, even line 16 : 9, left, up scan, odd line –5fh 4 : 3, right, down scan, odd line 4 : 3, left, down scan, odd line 4 : 3, right, up scan, even line 4 : 3, left, up scan, even line –6.5fh 4 : 3, right, down scan, even line 4 : 3, right, up scan, odd line –3.5fh 4 : 3, left, down scan, even line 4 : 3, left, up scan, odd line – 15 – CXD2412AQ The phase relationship between the horizontal pulses is shown in the figure below. The display start position can be changed by means of the HP pin while maintaining this relationship. HSYNC HSTn n = A.B VCK FRP 1µs PCG 1.2µs 0.7µs FRP PRG ENB 0.4µs CLR 3.1µs XCLP1 0.55µs 1.2µs XCLP2 0.15µs 2µs – 16 – CXD2412AQ XCLP Pulse Switching The phase relationship between HSYNC and XCLP1, XCLP2 is switched by means of CP1 and CP2. –250ns –650ns HSYNC XCLP1 CP1 = L; CP2 = L Central value CP1 = H; CP2 = L CP1 = L; CP2 = H CP1 = H; CP2 = H XCLP2 CP1 = L; CP2 = L Central value CP1 = H; CP2 = L CP1 = L; CP2 = H CP1 = H; CP2 = H – 17 – 550ns 150ns 1350ns 950ns 2150ns 1750ns 2550ns CXD2412AQ Vertical Output The vertical display position is varied as shown below. VP1 VP2 L L After 2H H L After 1H L H Central value H H 1H before LCD Panel AC Driving for No Signal With no signal, also, provision is made as follows for AC driving of the LCD panel. Horizontal pulses The PLL is set to the free-running state. Therefore, the horizontal pulse frequency depends on the PLL free-running frequency. Vertical pulses The number of lines is counted by an internal counter, and VST and FRP are output in a specific cycle. VST Cycle with No Signal SLAUX = L NTSC NTSC-WIDE MNDC 545H PAL PAL+ 641H HD 577H SLAUX = H All modes 769H Note) This TG determines there to be no signal if there is no VSYNC input during the above cycle. – 18 – – 19 – PRG PCG FRP VCK CLR ENB HSTB HCK2B HCK1B HSTA HCK2A HCK1A SH4 SH3 SH2 SH1 XCLP2 XCLP1 HSYNC MCK NTSC-ODD LINE 885 895 905 915 925 935 945 955 Horizontal Direction Timing Chart 965 0 10 20 30 40 50 60 70 80 90 100 120 130 140 150 160 Note) Input pins in default state. 110 170 CXD2412AQ – 20 – PRG PCG FRP VCK CLR ENB HSTB HCK2B HCK1B HSTA HCK2A HCK1A SH4 SH3 SH2 SH1 XCLP2 XCLP1 HSYNC MCK NTSC-EVEN LINE 885 895 905 915 925 935 945 955 Horizontal Direction Timing Chart 965 0 10 20 30 40 50 60 70 80 90 100 120 130 140 150 160 Note) Input pins in default state. 110 170 CXD2412AQ – 21 – PRG PCG FRP VCK CLR ENB HSTB HCK2B HCK1B HSTA HCK2A HCK1A SH4 SH3 SH2 SH1 XCLP2 XCLP1 HSYNC MCK PAL-ODD LINE 929 939 949 959 969 979 989 0 Horizontal Direction Timing Chart 10 20 30 40 50 60 70 80 90 100 110 120 140 150 160 170 180 Note) Input pins in default state. 130 190 CXD2412AQ – 22 – PRG PCG FRP VCK CLR ENB HSTB HCK2B HCK1B HSTA HCK2A HCK1A SH4 SH3 SH2 SH1 XCLP2 XCLP1 HSYNC MCK PAL-EVEN LINE 929 939 949 959 969 979 989 0 Horizontal Direction Timing Chart 10 20 30 40 50 60 70 80 90 100 110 120 140 150 160 170 180 Note) Input pins in default state. 130 190 CXD2412AQ – 23 – PRG PCG FRP VCK CLR ENB HSTB HCK2B HCK1B HSTA HCK2A HCK1A SH4 SH3 SH2 SH1 XCLP2 XCLP1 HSYNC MCK NT-WIDE-ODD LINE 1205 1215 1225 1235 1245 1255 1265 1275 1285 1295 0 Horizontal Direction Timing Chart 10 20 30 40 50 60 70 80 90 100 120 130 140 150 Note) Input pins in default state. 110 160 CXD2412AQ – 24 – PRG PCG FRP VCK CLR ENB HSTB HCK2B HCK1B HSTA HCK2A HCK1A SH4 SH3 SH2 SH1 XCLP2 XCLP1 HSYNC MCK NT-WIDE-EVEN LINE 1205 1215 1225 1235 1245 1255 1265 1275 1285 1295 0 Horizontal Direction Timing Chart 10 20 30 40 50 60 70 80 90 100 120 130 140 150 Note) Input pins in default state. 110 160 CXD2412AQ – 25 – PRG PCG FRP VCK CLR ENB HSTB HCK2B HCK1B HSTA HCK2A HCK1A SH4 SH3 SH2 SH1 XCLP2 XCLP1 HSYNC MCK PAL+ -ODD LINE 1235 1245 1255 1265 1275 1285 1295 1305 1315 1325 0 Horizontal Direction Timing Chart 10 20 30 40 50 60 70 80 90 110 120 130 140 150 Note) Input pins in default state. 100 160 CXD2412AQ – 26 – PRG PCG FRP VCK CLR ENB HSTB HCK2B HCK1B HSTA HCK2A HCK1A SH4 SH3 SH2 SH1 XCLP2 XCLP1 HSYNC MCK PAL+ -EVEN LINE 1235 1245 1255 1265 1275 1285 1295 1305 1315 1325 0 Horizontal Direction Timing Chart 10 20 30 40 50 60 70 80 90 100 120 130 140 150 Note) Input pins in default state. 110 160 CXD2412AQ – 27 – PRG PCG FRP VCK CLR ENB HSTB HCK2B HCK1B HSTA HCK2A HCK1A SH4 SH3 SH2 SH1 XCLP2 XCLP1 HSYNC MCK HD-ODD LINE 1280 1290 1300 1310 0 10 20 Horizontal Direction Timing Chart 30 40 50 60 70 80 90 100 110 120 130 140 150 170 180 190 200 210 Note) Input pins in default state. 160 220 CXD2412AQ – 28 – PRG PCG FRP VCK CLR ENB HSTB HCK2B HCK1B HSTA HCK2A HCK1A SH4 SH3 SH2 SH1 XCLP2 XCLP1 HSYNC MCK HD-EVEN LINE 1280 1290 1300 1310 0 10 20 30 Horizontal Direction Timing Chart 40 50 60 70 80 90 100 110 120 130 140 150 170 180 190 200 210 Note) Input pins in default state. 160 220 CXD2412AQ – 29 – PRG PCG FRP VCK CLR ENB HSTB HCK2B HCK1B HSTA HCK2A HCK1A SH4 SH3 SH2 SH1 XCLP2 XCLP1 HSYNC MCK MNDC-ODD LINE 1277 1287 1297 1307 1317 1327 1337 1347 1357 1367 0 Horizontal Direction Timing Chart 10 20 30 40 50 60 70 80 90 110 120 130 140 150 Note) Input pins in default state. 100 160 CXD2412AQ – 30 – PRG PCG FRP VCK CLR ENB HSTB HCK2B HCK1B HSTA HCK2A HCK1A SH4 SH3 SH2 SH1 XCLP2 XCLP1 HSYNC MCK MNDC-EVEN LINE 1277 1287 1297 1307 1317 1327 1337 1347 1357 1367 0 Horizontal Direction Timing Chart 10 20 30 40 50 60 70 80 90 110 120 130 140 150 Note) Input pins in default state. 100 160 CXD2412AQ – 31 – Vres (Internal pulse) ENB HST FRP (H inversion) FRP (F inversion) VCK VST XCLP BLK HSYNC (Double-speed sync) VSYNC NTSC/NTSC WIDE/MNDC 482 483' Vertical Direction Timing Chart 21H 1 2 3 4 5 1st display line 1 2' 3 4' 5 6' 7 8' Start of display CXD2412AQ – 32 – Vres (Internal pulse) ENB HST FRP (H inversion) FRP (F inversion) VCK VST XCLP BLK VSYNC HSYNC PAL/PAL+ Vertical Direction Timing Chart 20H 1 2 3 4 5 1st display line 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Start of display CXD2412AQ – 33 – Vres (Internal pulse) ENB HST FRP (F inversion) FRP (H inversion) VCK VST XCLP BLK VSYNC HSYNC HD-ODD FIELD 1035 Vertical Direction Timing Chart 45H 1 2 3 4 5 1st display line 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Start of display CXD2412AQ – 34 – Vres (Internal pulse) ENB HST FRP (F inversion) FRP (H inversion) VCK VST XCLP BLK VSYNC HSYNC HD-EVEN FIELD 517 Vertical Direction Timing Chart 518 523 528 538 1st display line 1 2 3 4 5 533 Start of display CXD2412AQ – 35 – 33µ 25V +5.0V 0.01µ Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 100p 100p 100p 0.01µ 50k 0.01µ 10k 33k 50k 1k 3.3µ 33µ 25V 33k 0.1µ 33k 10k 50k +13.0V 0.01µ 33k 5.1k 0.01µ +13.0V 10k 33µ 25V 1000p 50k 0.01µ 33k 33k 0.5µ 50k 3.3µ 10k 1k 5.1k 0.1µ 20p 0.01µ 1000p 0.5µ 20p XHD CKI2 VSS CKO3 CKI3 VSS RPD3 PEO3 PWM3 FPD3 TC3 10k 1k 1 3.3µ 2 3 XWID 33k 4 5 33k 10k 50k +13.0V 0.01µ 33k 5.1k 0.1µ 0.01µ CP1 CP2 L H L H NTPL SLFR 47µ 16V 0.01µ L H L H PCGW L H SLAUX L H SLSH2 L H SLSH1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SLSH3 TC2 FPD2 PEO2 PWM2 RPD2 VSS CKO2 33µ 25V 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 47µ 16V +5.0V 0.01µ L H 47µ 16V 0.01µ SLSH3 6 9 1µ 8 0.01µ 1000p 7 20p C HP3 S1030 1 2 4 5 TOP VIEW 10k 10k 10k 10k 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0.01µ L HP2 H 32 33 34 35 36 37 38 39 40 41 42 31 43 44 45 46 47 48 49 50 47µ 16V VP2 XCLR VP2 VP1 N.C. DWN VST PCG VCK L H ENB CLR HSTB VSS HCK2B HCK1B HCK2A HCK1A VDD HSTA XRGT RGT XHD VSS VDD XWID NTPL SLFR PCGW SLAUX SLSH2 SLSH1 VDD SH4 SH3 SH2 SH1 VSS PRG XCLP2 XCLP1 FRP N.C. N.C. N.C. N.C. N.C. N.C. VSS VDD N.C. N.C. N.C. N.C. VDD VSS TC1 FPD1 PEO1 PWM1 RPD1 VSS CKO1 CKI1 VSS TST6 VSS HSYNC VSYNC HP1 HP2 HP3 HP4 HP5 HP6 TST1 TST2 TST3 TST4 VDD VSS TST5 VP1 L HP1 H 47µ 16V +5.0V 0.01µ 47µ 16V 0.01µ L H DWN L CP1 H L H RGT L CP2 H +5.0V L H L H +5.0V CXD2412AQ Application Circuit CXD2412AQ Package Outline Unit: mm 100PIN QFP (PLASTIC) + 0.4 14.0 – 0.01 17.9 ± 0.4 15.8 ± 0.4 + 0.1 0.15 – 0.05 23.9 ± 0.4 + 0.4 20.0 – 0.1 A 0.65 + 0.35 2.75 – 0.15 ±0.12 M 0° to 15° DETAIL A 0.8 ± 0.2 (16.3) 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE QFP-100P-L01 LEAD TREATMENT SOLDER PLATING EIAJ CODE ∗QFP100-P-1420-A LEAD MATERIAL COPPER / 42 ALLOY PACKAGE WEIGHT 1.4g JEDEC CODE – 36 –