High Efficiency Switch Mode Li-Ion Battery Charger ADP3808 FEATURES GENERAL DESCRIPTION Selectable 3-cell or 4-cell operation Adjustable 4.0 V to 4.5 V per cell High end-of-charge voltage accuracy ±0.4% @ 25°C ±0.6% @ 5°C to 55°C ±0.8% @ 0°C to 100°C Programmable charge current, including trickle charge Bootstrapped synchronous drive for external N-channel MOSFETs Programmable oscillator frequency The ADP3808 is a complete Li-Ion battery charging controller for 3- or 4-cell battery packs. The device combines accurate final battery charge voltage control with constant current control to simplify the implementation of constant-current, constant-voltage (CCCV) chargers. The final battery charge voltage is programmable between 4.0 V to 4.5 V per cell, allowing the charging of various cell types. The charge current is programmable over a wide range from trickle charging to full charging. The system current sense amplifier includes an ac adapter detection output to signal that the adapter is connected. The bootstrapped synchronous driver controls two N-channel MOSFET transistors for high efficiency charging at a low system cost. APPLICATIONS Portable computers Portable equipment The ADP3808 is specified over the extended commercial temperature range of 0°C to 100°C and is available in a 24-lead LFCSP package. FUNCTIONAL BLOCK DIAGRAM VCC 22 EN LOW-SIDE DRIVE REGULATOR UVLO AND BIAS 8 DRVREG EN REFERENCE IN AGND 10 RT CELLSEL 12 BAT 11 REFIN 6 BATADJ 7 COMP 9 3-/4CELL 20 DRVH 21 SW 18 DRVLSD OSCILLATOR BST DRVREG CONTROL LOGIC 5 19 DRVREG 17 DRVL 16 PGND 15 CSP 14 CSM 13 CSADJ 4 EXTPWR VTH BATTERY VOLTAGE ADJUST gm gm SYSM 23 SYSP 24 CMP CHARGE CURRENT SETPOINT 1V CMP SYS+ CMP 18.25V 2 3 06632-001 1 ISYS LIMSET LIMIT Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. ADP3808 TABLE OF CONTENTS Features .............................................................................................. 1 LIMIT........................................................................................... 13 Applications....................................................................................... 1 AC Adaptor Detection............................................................... 13 General Description ......................................................................... 1 EN................................................................................................. 13 Functional Block Diagram .............................................................. 1 UVLO........................................................................................... 13 Revision History ............................................................................... 2 Loop Feed Forward .................................................................... 13 Specifications..................................................................................... 3 Application Information................................................................ 14 Absolute Maximum Ratings............................................................ 5 Design Procedure ....................................................................... 14 ESD Caution.................................................................................. 5 Battery Voltage Settings............................................................. 14 Pin Configuration and Function Descriptions............................. 6 Inductor Selection.................................................................. 14 Typical Performance Characteristics ............................................. 7 Output Capacitor Selection .................................................. 14 Theory of Operation ...................................................................... 10 Input Capacitor Ripple .......................................................... 14 Setting the Charge Current ....................................................... 10 Decoupling the VCC Pin ...................................................... 14 Final Battery Voltage Control ................................................... 11 Current Sense Filtering.......................................................... 14 Oscillator and PWM .................................................................. 11 MOSFET Selection................................................................. 14 5.25 V Bootstrap Regulator....................................................... 12 Outline Dimensions ....................................................................... 15 Bootstrapped Synchronous Driver........................................... 12 Ordering Guide .......................................................................... 15 System Current Sense ................................................................ 12 REVISION HISTORY 6/07—Revision 0: Initial Version Rev. 0 | Page 2 of 16 ADP3808 SPECIFICATIONS VCC = 20 V, EN = 5 V, REFIN = 3 V, TA = 0°C to 100°C, unless otherwise noted. 1 Table 1. Parameter BATTERY VOLTAGE SENSING Accuracy Input Resistance Shutdown Leakage Current Overvoltage Threshold Overvoltage Response Time BATTERY VOLTAGE ADJUST BATADJ Input Range REFIN Input Range 3-Cell Voltage Low 3-Cell Voltage High 4-Cell Voltage Low 4-Cell Voltage High BATTERY CURRENT SENSE AMPLIFIER Accuracy 2 Input Common Mode Range Input Bias Current—Operating Input Bias Current—Shutdown Input Bias Current—CSM Gain CSADJ Bias Current Overcurrent Threshold2 Overcurrent Response Time DRVL Shutdown Threshold SYSTEM CURRENT SENSE AMPLIFIER Input Common Mode Range Input Bias Current, SYSP Input Bias Current, SYSM Voltage Gain ISYS Output Current LIMIT Threshold LIMSET Input Range LIMIT Output Voltage Low LIMIT Propagation Delay Time EXTPWR Current Threshold Symbol Conditions Min ΔVBAT TA = 25°C, 13 V ≤ VCC ≤ 21 V, BATADJ = 0 V or BATADJ = REFIN 5°C ≤ TA ≤ 55°C, 13 V ≤ VCC ≤ 21 V, BATADJ = 0 V or BATADJ = REFIN 13 V ≤ VCC ≤ 21 V, BATADJ = 0 V or BATADJ = REFIN RBAT IBAT(SD) VBAT(OV) tBAT(OV) VBATADJ VREFIN VBAT VBAT VBAT VBAT VCM(SYS) IB(SYSP) IB( SYSM) VTH(LIMIT) VLIMSET VOL(LIMIT) tpdl(LIMIT) Unit −0.4 +0.4 % −0.6 +0.6 % −0.8 +0.8 % 120 VBAT(OV) to COMP < 1 V 170 0.2 135 1 0 2.0 BATADJ = 0 V, CELLSEL = 3.3 V BATADJ = REFIN, CELLSEL = 3.3 V BATADJ = 0 V, CELLSEL = 0 V BATADJ = REFIN, CELLSEL = 0 V CSADJ = REFIN, 3.9 V ≤ VCS(CM) ≤ 21 V CSADJ = 0.2 × REFIN, 3.9 V ≤ VCS(CM) ≤ 21 V VCM(CS) IB(CSP) IB(CSP,SD) IB(CSM) AV(CS) IB(CSADJ) VCS(OC) tDC VCS(DRVLSD) Max EN = 0 V Typ REFIN 3.5 12.0 13.5 16.0 18.0 −8 −20 0 EN = 0 V 90 VOC > 130 mV to COMP < 1 V SYSP and SYSM to AGND VSYS(CM) = 19 V VSYS(CM) = 19 V VISYS/(VSYSP − VSYSM) VISYS = 2.5 V SYSP to SYSM, LIMSET = 2.5 V 1.0 +8 +30 VCC 40 0.1 0.1 31.25 1 100 1 32 10 1 2 2 110 V V V V V % % V μA μA μA V/V μA mV μs mV 27.5 V μA μA V/V μA mV V mV μs mV 18.25 18.5 V IEXTPWR = −100 μA 5 50 mV SYSP Rising > 18.5 V to EXTPWR going low 1 49.5 48 0 300 0.1 50 5 53 VTH(EXTPWR) ILIMIT = −100 μA (SYSP) – (SYSM) rising > 55 mV to LIMIT going low SYSP to SYSM 17.5 30 1 22.5 EXTPWR Voltage Threshold VTH(EXTPWR) SYSP to AGND 18.0 EXTPWR Output Voltage Low VTH(EXTPWR) EXTPWR Propagation Delay Time tdpl(EXTPWR ) Rev. 0 | Page 3 of 16 22 400 1 51.5 kΩ μA % μs 58 3.5 75 μs ADP3808 Parameter OSCILLATOR Maximum Frequency Frequency Variation RT Output Voltage Zero Duty Cycle Threshold Maximum Duty Cycle Threshold LOGIC INPUTS (EN, CELLSEL) Input Voltage High Input Voltage Low Input Current HIGH-SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Output Resistance, Unbiased Transition Time Propagation Delay Time LOW-SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Output Resistance, Unbiased Transition Time Propagation Delay Time 3 Timeout Delay 4 SUPPLY VCC Supply Voltage Range Supply Current Normal Mode Shutdown Mode Undervoltage Lockout Threshold Undervoltage Lockout Hysteresis DRV Regulator Output Voltage DRV Regulator Output Current Symbol Conditions Min fOSC ΔfOSC VRT RT = 150 kΩ 250 1.9 Measured at COMP Measured at COMP VIH VIL IIN Inputs = 0 V or 5 V trDRVH, tfDRVH tpdhDRVH BST to SW = 5 V BST to SW = 5 V BST to SW = 0 V BST to SW = 5 V, CLOAD = 1 nF BST to SW = 5 V, CLOAD = 1 nF trDRVL, tfDRVL tpdhDRVL Typ 1 290 2 1 2 Max 340 2.1 2.0 VCC = PGND CLOAD = 1 nF CLOAD = 1 nF SW = 5 V SW = PGND VCC 0.8 +1 –1 25 3 3 10 20 60 150 150 3.8 1.5 10 20 15 300 300 10 IVCC IVCC(SD) VUVLO EN = 5 V EN = 0 V VCC rising VDRVREG IDRVREG CL = 100 nF All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods. Measured between CSP and CSM. (VCSP − VCSM) = 96 mV × CSADJ/REFIN. 3 For propagation delays, tpdh refers to the specified signal going high, and tpdl refers to it going low. 4 The turn-on of DRVL is initiated after DRVH turns off by either SW crossing a ~1 V threshold or by expiration of the timeout delay. 1 2 Rev. 0 | Page 4 of 16 9 5.0 10 9.8 5 9.5 600 5.25 8 8 40 85 8 8 40 35 Unit MHz kHz V V V V V μA Ω Ω kΩ ns ns Ω Ω kΩ ns ns ns ns 22 V 12 10 10 mA μA V mV V mA 5.5 ADP3808 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VCC PGND BST BST to SW SW DRVH DRVL SYSP, SYSM to AGND BAT, CSP, CSM to AGND SYSP to SYSM CSP to CSM All Other Inputs and Outputs θJA 2-Layer Board 4-Layer Board Operating Ambient Temperature Range Junction Temperature Range Storage Temperature Range Lead Temperature Soldering (10 sec) Vapor Phase (60 sec) Infrared (15 sec) Rating −0.3 V to +25 V −0.3 V to +0.3 V −0.3 V to +30 V −0.3 V to +6 V −4 V to +25 V SW − 0.3 V to BST + 0.3 V PGND − 0.3 V to DRVREG + 0.3 V −25 V to +25 V −0.3 V to VCC + 0.3 V −5 V to +5 V −5 V to +5 V −0.3 V to +6 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 125°C/W 83°C/W 0°C to 100°C 0°C to 150°C −65°C to +150°C 300°C 215°C 220°C Rev. 0 | Page 5 of 16 ADP3808 19 BST 20 DRVH 21 SW 22 VCC 23 SYSM 24 SYSP PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ISYS 1 18 DRVREG LIMSET 2 17 DRVL ADP3808 LIMIT 3 16 PGND TOP VIEW (Not to Scale) EXTPWR 4 15 CSP RT 5 14 CSM 06632-002 CELLSEL 12 BAT 11 AGND 10 COMP 9 EN 8 13 CSADJ BATADJ 7 REFIN 6 Figure 2. LFCSP Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 2 3 4 Mnemonic ISYS LIMSET LIMIT EXTPWR 5 RT 6 7 REFIN BATADJ 8 EN 9 10 11 12 13 COMP AGND BAT CELLSEL CSADJ 14 15 16 17 18 CSM CSP PGND DRVL DRVREG 19 BST 20 21 DRVH SW 22 23 24 VCC SYSM SYSP 25 Paddle Description Output for System Current Sense Amplifier. System Current Limit Set Point Input. System Current Limit Output. This is an open-drain pin and requires a pull-up resistor to a maximum of 6 V. External Adapter Sense Open-Drain Output. This pin pulls low when the ac adapter voltage is present. A pull-up resistor is required to a maximum of 6 V. Frequency Setting Resistor Input. An external resistor connected between this pin and AGND sets the oscillator frequency of the device. Reference Input for BATADJ and CSADJ. Battery Voltage Adjust Input. This pin uses an analog voltage referenced to REFIN to program voltage from 4.0 V to 4.5 V per cell. Charger Enable Input. Pulling this pin to AGND disables the DRVH and DRVL outputs and puts the circuitry powered by VCC into a low power state. The system amplifier and EXTPWR are still active. Output of Error Amplifiers and Compensation Point. Analog Ground. Reference point for the battery sense and all analog functions. Battery Sense Input. Battery Cell Selection Input. Pulling this pin high selects 3-cell operation; pulling it low selects 4-cell operation. Charge Current Programming Input. This pin uses an analog voltage referenced to REFIN to program the battery charge current. (VCSP − VCSM) = 96 mV x CSADJ/REFIN. Negative Current Sense Input. This pin connects to the battery side of the battery current sense resistor. Positive Current Sense Input. This pin connects to the inductor side of the battery current sense resistor. Power Ground. This pin should closely connect to the source of the lower MOSFET. Synchronous Rectifier Drive. Output drive for the lower MOSFET. Driver Supply Output. A bypass capacitor should be connected from this pin to PGND to provide filtering for the low-side supply. Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this bootstrapped voltage for the high-side MOSFET as it is switched. Main Switch Drive. Output drive for the upper MOSFET. Switch Node Input. This pin is connected to the buck-switching node, close to the source of the upper MOSFET, and is the floating return for the upper MOSFET drive signal. Input Supply. This pin does not power the SYS amplifier section. Negative System Current Sense Input. This pin connects to the battery side of the system current sense resistor. Positive System Current Sense Input. This pin connects to the adapter side of the system current sense resistor. This pin also provides power to the system amplifier section. This pin should be connected to AGND. Rev. 0 | Page 6 of 16 ADP3808 TYPICAL PERFORMANCE CHARACTERISTICS 12 30 VCC = 16V TA = 25°C NO LOADS TA = 0°C 11 ON SUPPLY CURRENT (mA) 20 15 10 TA = 25°C 10 9 TA = 100°C 8 5 0 –0.5 06632-003 7 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 6 12 0.5 06632-008 NUMBER OF PARTS 25 13 14 15 VBAT ACCURACY (%) Figure 3. VBAT Accuracy Distribution 16 VCC (V) 17 18 19 20 Figure 6. On Supply Current vs. VCC 0.15 126 VCC = 16V 0.1 TA = 100°C 106 OFF SUPPLY CURRENT (nA) VBAT ACCURACY (%) 0.05 0 –0.05 –0.1 –0.15 –0.2 86 TA = 25°C 66 46 TA = 0°C –0.3 0 10 20 30 40 50 60 70 TEMPERATURE (°C) 80 90 6 12 100 Figure 4. VBAT Accuracy vs. Temperature 14 15 16 VCC (V) 17 18 19 20 20 TA = 25°C 0.06 VCC = 16V TA = 25°C fOSC = 300kHz 18 0.05 SUPPLY CURRENT (mA) 0.04 0.03 0.02 0.01 0 –0.01 –0.02 16 14 12 –0.03 14 15 16 17 VCC (V) 18 19 20 06632-009 10 06632-005 VBAT ACCURACY (%) 13 Figure 7. Off Supply Current vs. VCC 0.07 –0.04 13 06632-021 06632-004 26 –0.25 0 0 500 1000 1500 2000 2500 DRIVER LOAD CAPACITANCE (pF) 3000 Figure 8. Supply Current vs. Driver Load Capacitance Figure 5. VBAT Accuracy vs. VCC Rev. 0 | Page 7 of 16 3500 ADP3808 4.5 VCC = 16V DRIVER ON RESISTANCE (Ω) 4 300 250 200 90 110 130 150 170 190 SOURCE 3.5 3 2.5 2 SINK 1.5 06632-020 350 06632-011 OSCILLATOR FREQUENCY (kHz) 400 1 210 0 RT (kΩ) 20 Figure 9. Oscillator Frequency vs. RT 40 60 TEMPERATURE (°C) 80 100 Figure 12. DRVL On Resistance vs. Temperature 6 ISYS RISING ISYS FALLING VCC = 16V TA = 25°C DRVH 5V/DIV 5 VLIMIT (V) 4 3 DRVL 5V/DIV 0 06632-012 1 0 0.5 1 1.5 VISYS (V) 2 2.5 200ns/DIV 3.0 Figure 13. Driver Waveforms Figure 10. VLIMIT vs. VISYS 100 3.3 VCC = 16V CONVERSION EFFICIENCY (%) SINK SOURCE 2.8 2.7 20 40 60 TEMPERATURE (°C) 80 90 85 80 75 70 65 60 100 06632-015 2.9 06632-013 DRIVER ON RESISTANCE (Ω) 3.1 0 VCC = 19V VBAT = 12.4V TA = 25°C 95 3.2 3.0 06632-014 2 0 0.5 1.0 1.5 2.0 2.5 CHARGE CURRENT (A) Figure 14. Conversion Efficiency vs. Charge Current Figure 11. DRVH On Resistance vs. Temperature Rev. 0 | Page 8 of 16 3.0 ADP3808 97 ICHARGE = 2A 95 ICHARGE = 3A 94 93 92 91 90 VCC = 19V TA = 25°C 89 88 3 4 5 6 7 8 9 10 11 12 06632-016 CONVERSION EFFICIENCY (%) 96 13 VBAT (V) Figure 15. Conversion Efficiency vs. Battery Voltage Rev. 0 | Page 9 of 16 ADP3808 THEORY OF OPERATION The ADP3808 combines a bootstrapped synchronous switching driver with programmable current control and accurate final battery voltage control in a constant-current, constant-voltage (CCCV) Li-Ion battery charger. High accuracy voltage control is needed to safely charge Li-Ion batteries, which are typically specified at 4.2 V ± 1% per cell. For a typical notebook computer battery pack, three or four cells are in series, giving a total voltage of 12.6 V or 16.8 V. The ADP3808 allows the final battery voltage to be programmed. The programmable range is 4.0 V to 4.5 V per cell. The total number of cells to be charged can be set to either 3 or 4 via a control pin. strapped high-side driver, the ADP3808 drives two external power NMOS transistors for a simple, lower cost power stage. Another requirement for safely charging Li-Ion batteries is accurate control of the charge current. The actual charge current depends on the number of cells in parallel within the battery pack. Typically, this is in the range of 2 A to 3 A. The ADP3808 provides flexibility in programming the charge current over a wide range. An external resistor is used to sense the charge current. The charge current can be set by programming the sense resistor voltage drop. The voltage drop can be set to a maximum of 96 mV. This programmability allows the current to be changed during charging. For example, the charge current can be reduced for trickle charging. SETTING THE CHARGE CURRENT The synchronous driver provides high efficiency when charging at high currents. Efficiency is important mainly to reduce the amount of heat generated in the charger, but also to stay within the power limits of the ac adapter. With the addition of a boot- The ADP3808 also provides an uncommitted current sense amplifier. This amplifier provides an analog output pin for monitoring the current through an external sense resistor. The amplifier can be used anywhere in the system that high-side current sensing is needed. The sense amplifier output is compared to a programmable voltage limit. If the limit is exceeded, the LIMIT pin is asserted. The system sense amplifier is also used to detect the presence of an ac adaptor. If the adaptor is detected, the ADP3808 asserts a logic pin to signal the detection. The charge current is measured across an external sense resistor, RCS, between the CSP and CSM pins. The input common-mode range is from ground to VCC, allowing current control in short-circuit and low dropout conditions. The voltage between CSP and CSM is programmed by a ratio of the voltages at CSADJ and REFIN according to Equation 1. VCSP − VCSM = 96 mV CSADJ REFIN For example, using a 20 mΩ sense resistor gives a range from 150 mA with CSADJ = REFIN/32 to 4.8 A maximum when CSADJ = REFIN. The power dissipation in RCS should be kept below 500 mW. Components R4 and C13 provide high frequency filtering for the current sense signal. Rev. 0 | Page 10 of 16 (1) ADP3808 RSS 10mΩ C15 22µF C14 2.2µF + – 1/2 Q1 FD56990A 22µH + C16 – 22µF C13 22µF C9 VCC BST 100nF DRV R2 510Ω R4 510Ω SW PGND DRVL BOOTSTRAPPED SYNCHRONOUS DRIVER EN IN DRVLSD CSM CSP BATTERY 12.6V/16.8V C1 2.2µF SYSP 3.3V ISYS SYSM LIMIT 3.3V + – AMP1 – R13 10Ω SYSTEM DC/DC RCS 20mΩ L1 + VIN 1/2 Q1 FD56990A AMP2 – DRVLSD R9 + LIMSET – + – VTH – R10 + EXTPWR gm1 + + – EN 1V LOGIC CONTROL SYSP – BAT + CSADJ CHARGE CURRENT SETPOINT OSCILLATOR – + RT 150kΩ 3.3V 3-/4-CELL SELECTION gm2 ADP3808 AGND BAT BATTERY VOLTAGE ADJUST R11 REFIN BATADJ COMP C8 0.22µF R12 CELLSEL R8 56Ω 06632-018 DRVREG 7.0V C10 0.1µF VREF + VREG UVLO BIAS C11 Figure 16. Typical Application Circuit FINAL BATTERY VOLTAGE CONTROL As the battery approaches its final voltage, the ADP3808 switches from CC mode to CV mode. The change is achieved by the common output node of gm1 and gm2. Only one of the two outputs controls the voltage at the COMP pin. Both amplifiers can only pull down on COMP, such that when either amplifier has a positive differential input voltage, its output is not active. For example, when the battery voltage, VBAT, is low, gm2 does not control VCOMP. When the battery voltage reaches the desired final voltage, gm2 takes control of the loop, and the charge current is reduced. Amplifier gm2 compares the battery voltage to a programmable level set by pins BATADJ and REFIN. The target battery voltage is dependent on the state of the CELLSEL pin as CELLSEL sets the number of cells to be charged. Pulling CELLSEL high sets the ADP3808 to charge three cells. When CELLSEL is tied to ground, four cells are selected. CELLSEL has a 2 μA pull-up current as a fail-safe to select three cells when it is left open. and is ratioed to the REFIN pin. The battery voltage VBAT is set according to Equation 2 and Equation 3. For CELLSEL > 2 V: VBAT = 12 V + 1.5 V BATADJ REFIN (2) For CELLSEL < 0.8 V: VBAT = 16 V + 2 V BATADJ REFIN (3) OSCILLATOR AND PWM The oscillator generates a triangle waveform between 1 V and 2 V, which is compared to the voltage at the COMP pin, setting the duty cycle of the driver stage. When VCOMP is below 1.0 V, the duty cycle is zero. Above 2.0 V, the duty cycle reaches its maximum. The oscillator frequency is set by the external resistor at the RT pin, ROSC, and is given by Equation 4. The final battery voltage is programmable from 4.0 V to 4.5 V per cell. The programming voltage is applied to the BATADJ pin Rev. 0 | Page 11 of 16 f OSC = 41 × 10 9 ROSC (4) ADP3808 DRVREG ADP3808 BOOTSTRAPPED SYNCHRONOUS DRIVER BST CMP3 CBST MIN OFF TIME IN DRVH Q1 EN SW DELAY 1V – CMP2 + 1V DRVL – CMP1 + Q2 PGND DELAY 06632-019 DRVLSD Figure 17. Bootstrapped Synchronous Driver 5.25 V BOOTSTRAP REGULATOR The driver stage is powered by the internal 5.25 V bootstrap regulator, which is available at the DRVREG pin. Because the switching currents are supplied by this regulator, decoupling must be added. A 0.1 μF capacitor should be placed close to the ADP3808, with the ground side connected close to the power ground pin, PGND. This supply is not recommended for use externally due to high switching noise. BOOTSTRAPPED SYNCHRONOUS DRIVER The PWM comparator controls the state of the synchronous driver shown in Figure 17. A high output from the PWM comparator forces DRVH on and DRVL off. The drivers have an on resistance of less than 4 Ω for fast rise and fall times when driving external MOSFETs. Furthermore, the bootstrapped drive allows an external NMOS transistor for the main switch instead of a PMOS. A boost capacitor of 0.1 μF must be added externally between BST and SW. The DRVL pin switches between DRVREG and PGND. The 5.25 V output of DRVREG drives the external NMOS with high VGS to lower the on resistance. PGND should be connected close to the source pin of the external synchronous NMOS. When DRVL is high, this turns on the lower NMOS and pulls the SW node to ground. At this point, the boost capacitor is charged up through the internal boost diode. When the PWM switches high, DRVL is turned off and DRVH turns on. DRVH switches between BST and SW. When DRVH is on, the SW pin is pulled up to the input supply (typically 16 V), and BST rises above this voltage by approximately 4.75 V. Overlap protection is included in the driver to ensure that both external MOSFETs are not on at the same time. When DRVH turns off the upper MOSFET, the SW node goes low due to the inductor current. The ADP3808 monitors the SW voltage, and DRVL goes high to turn on the lower MOSFET when SW goes below 1 V. When DRVL turns off, an internal timer adds a delay of 50 ns before turning DRVH on. When the charge current is low, the DRVLSD comparator signals the driver to turn off the low-side MOSFET and DRVL is held low. The DRVLSD threshold is set to 0.8 V corresponding to a 32 mV differential between the CS pins. The driver stage monitors the voltage across the BST capacitor with CMP3. When this voltage is less than 4 V, CMP3 forces a minimum off time of 200 ns. This ensures that the BST capacitor is charged even during DRVLSD. However, because a minimum off time is only forced when needed, the maximum duty cycle is greater than 99%. SYSTEM CURRENT SENSE An uncommitted differential amplifier is provided for additional high-side current sensing. This amplifier, AMP2, has a fixed gain of 50 V/V from the SYSP and SYSM pins to the analog output at ISYS. ISYS has a 100 μA source capability to drive an external load. The common-mode range of the input pins is from 10 V to 22 V. This amplifier is the only part of the ADP3808 that remains active during shutdown. The power to this block is derived from the bias current on the SYSP and SYSM pins. Rev. 0 | Page 12 of 16 ADP3808 LIMIT UVLO The LIMIT pin is an open-drain output that signals when the voltage at ISYS exceeds the voltage at LIMSET. The internal comparator produces the function shown in Figure 10. This is a graph of VLIMIT vs. VISYS where LIMSET is set to 1.5 V. The LIMIT pin should be pulled up to a maximum of 6 V through a resistor. When ISYS is below LIMSET, the LIMIT pin has high output impedance. The open-drain output is capable of sinking 700 μA when the threshold is exceeded. This comparator is turned off during shutdown to conserve power. Undervoltage lock-out, UVLO, is included in the ADP3808 to ensure proper startup. As VCC rises above 1 V, the regulator tracks VCC until it reaches its final voltage. However, the rest of the circuitry is held off by the UVLO comparator. The UVLO comparator monitors the regulator to ensure that it is above 5 V before turning on the main charger circuitry. This occurs when VCC reaches 9.5 V. Monitoring the regulator outputs makes sure that the charger circuitry and driver stage have sufficient voltage to operate normally. The UVLO comparator includes 600 mV of hysteresis to prevent oscillations near the threshold. AC ADAPTOR DETECTION The EXTPWR pin on the ADP3808 is an open-drain active low output used to signal that an ac adaptor is connected. If the ISYS voltage level is greater than 1 V or the SYSP sense pin voltage is greater then 18.25 V, the EXTPWR pin is driven low. A pull-up resistor must be connected when this function is required. The maximum pull-up voltage is 6 V. EN A high impedance CMOS logic input is provided to turn off the ADP3808. When the voltage on EN is less than 0.8 V, the ADP3808 is placed in low power shutdown. With the exception of the system current sense amplifier, AMP2, all other circuitry is turned off. The reference and regulators are pulled to ground during shutdown and all switching is stopped. During this state, the supply current is less than 5 A. In addition, the BAT, CSP, CSM, and SW pins go to high impedance to minimize current drain from the battery. LOOP FEED FORWARD As the startup sequence discussion shows, the response time at COMP is slowed by the large compensation capacitor. To speed up the response, two comparators can quickly feed forward around the normal control loop and pull the COMP node down to limit any overshoot in either short-circuit or overvoltage conditions. The overvoltage comparator has a trip point set to 35% higher than the final battery voltage. The overcurrent comparator threshold is set to 100 mV across the CS pins. When these comparators are tripped, a normal soft start sequence is initiated. The overvoltage comparator is valuable when the battery is removed during charging. In this case, the current in the inductor causes the output voltage to spike up, and the comparator limits the maximum voltage. Neither of these comparators affects the loop under normal charging conditions. Rev. 0 | Page 13 of 16 ADP3808 APPLICATION INFORMATION DESIGN PROCEDURE Refer to Figure 16, the typical application circuit, for the following description. The design follows that of a buck converter. With Li-Ion cells it is important to have a regulator with accurate output voltage control. BATTERY VOLTAGE SETTINGS Usually the inductor is chosen based on the assumption that the inductor ripple current is ±15% of the maximum output dc current at maximum input voltage. As long as the inductor used has a value close to this, the system should work fine. The final choice affects the trade-offs between cost, size, and efficiency. For example, the lower the inductance, the size is smaller but ripple current is higher. This situation, if taken too far, leads to higher ac losses in the core and the windings. Conversely, a higher inductance results in lower ripple current and smaller output filter capacitors, but the transient response will be slower. With these considerations, the required inductance can be calculated using Equation 6. L1 = ΔI × D MIN × TS (6) where the maximum input voltage VIN, MAX is used with the minimum duty ratio DMIN. The duty ratio is defined as the ratio of the output voltage to the input voltage, VBAT/VIN. The ripple current is calculated using Equation 7. ΔI = 0.3 × IBAT, MAX (7) The maximum peak-to-peak ripple is 30%, that is 0.3, and maximum battery current, IBAT, MAX, is used. For example, with VIN, MAX = 19 V, VBAT = 12.6 V, IBAT, MAX = 3A, and TS = 4 μs, the value of L1 is calculated as 18.9 μH. Choosing the closest standard value gives L1 = 22 μH. Output Capacitor Selection An output capacitor is needed in the charger circuit to absorb the switching frequency ripple current and smooth the output voltage. The rms value of the output ripple current is given by I rms = VIN , MAX fL1 12 D (1 − D ) (8) VIN , MAX fL1 PBAT η × D VIN × D(1 − D) D (10) This is a worst-case calculation and, depending on total charge time, the calculated number could be relaxed. Consult the capacitor manufacturer for further technical information. Decoupling the VCC Pin It is a good idea to use an RC filter (R13 and C14) from the input voltage to the IC both to filter out switching noise and to supply bypass to the chip. During layout, this capacitor should be placed as close to the IC as possible. Values between 0.1 μF and 2.2 μF are recommended. Current Sense Filtering During normal circuit operation, the current sense signals can have high frequency transients that need filtering to ensure proper operation. In the case of the CSP and CSM inputs, Resistor R4 is set to 510 Ω and the filter capacitor C13 is 22 nF. For the system current sense filter on SYSP, SYSM, R2 is set to 510 Ω, C1 is 2.2 μF, and C2 is 470 nF. MOSFET Selection One of the features of the ADP3808 is that it allows use of a high-side NMOS switch instead of a more costly PMOS device. The converter also uses synchronous rectification for optimal efficiency. To use a high-side NMOS, an internal bootstrap regulator automatically generates a 5.25 V supply across C9. Maximum output current determines the RDS(ON) requirement for the two power MOSFETs. When the ADP3808 is operating in continuous mode, the simplifying assumption can be made that one of the two MOSFETs is always conducting the load current. The power dissipation for each MOSFET is given by Upper MOSFET: PDISS = RDS(ON) × (IBAT × √D)2 + VIN × IBAT × √D × TSW × f (11) Lower MOSFET: The maximum value occurs when the duty cycle is 0.5. Thus, I rms _ MAX = 0.072 I rms = where η is the estimated converter efficiency (approximately 90%, 0.9) and PBAT is the maximum battery power consumed. Inductor Selection VIN , MAX − VBAT input capacitor has to absorb this current ripple, it must have an appropriate rms current rating. The maximum input rms current is given by PDISS = RDS(ON) × (IBAT × √D)2 + VIN × (IBAT × √1 − D)2 × tSW × f (12) (9) where f is the switching frequency and tSW is the switch transition time, usually 10 ns. For an input voltage of 19 V and a 22 μH inductance, the maximum rms current is 0.26 A. A typical 10 μF or 22 μF ceramic capacitor is a good choice to absorb this current. Input Capacitor Ripple As is the case with a normal buck converter, the pulse current at the input has a high rms component. Therefore, because the The first term accounts for conduction losses while the second term estimates switching losses. Using these equations and the manufacturer’s data sheets, the proper device can be selected. Rev. 0 | Page 14 of 16 ADP3808 OUTLINE DIMENSIONS 0.60 MAX 4.00 BSC SQ PIN 1 INDICATOR 0.60 MAX TOP VIEW 0.50 BSC 3.75 BSC SQ 0.50 0.40 0.30 1.00 0.85 0.80 12° MAX SEATING PLANE 0.80 MAX 0.65 TYP 0.30 0.23 0.18 PIN 1 INDICATOR 24 1 19 18 2.25 2.10 SQ 1.95 EXPOSED PAD (BOTTOM VIEW) 13 12 7 6 0.25 MIN 2.50 REF 0.05 MAX 0.02 NOM 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2 Figure 20. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-24-1) Dimensions shown in millimeters ORDERING GUIDE Model ADP3808JCPZ 1 ADP3808JCPZ-RL1 1 Temperature Range 0°C to 100°C 0°C to 100°C Package Description 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Z = RoHS Compliant Part. Rev. 0 | Page 15 of 16 Package Option CP-24-1 CP-24-1 Ordering Quantity 5000 ADP3808 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06632-0-6/07(0) Rev. 0 | Page 16 of 16