CXD2930BR GPS LSI with Built-in 32-bit RISC CPU Description The CXD2930BR is a dedicated LSI for the GPS (Global Positioning System) satellite-based position measurement system. This LSI contains a 32-bit RISC CPU, RAM, UART, timer, etc. This LSI, used together with an external ROM and RF LSI (CXA1951AQ), enables the configuration of a 3-chip system capable of measuring its position anywhere on the globe. 144 pin LQFP (Plastic) Features • 16-channel GPS receiver capable of simultaneously receiving 16 satellites • Supports DARC system FM multiplexed differential GPS • All-in-view measurement • 2-satellite measurement • Timer supporting GPS time • High performance 32-bit RISC CPU • 32K-byte RAM • 3-channel UART • Baud rate generator • Supports 1.2K, 2.4K, 4.8K, 9.6K, 19.2K and 38.4K baud • Supports 1/2/4-byte buffer mode • 23-bit general-purpose I/O port capable of defining input/output independently for each bit Structure Silicon gate CMOS IC Recommended Operating Conditions • Supply voltage VDD 3.0 to 3.6 • Operating temperature Topr –40 to +85 V °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E98307A96-PS CXD2930BR Performance • Reception frequency 1575.42MHz (L1 band, CA code) • Reception sensitivity (using the CXA1951AQ in the RF block) Antenna –130dBm or less • Time to first fix∗ (time until initial measurement after power-on) CXA1951AQ Cold start (without ephemeris and almanac) RF Converter 35 to 60s Warm start (without ephemeris with almanac) 0V 0V 34 to 50s TCXO IF Hot start (with ephemeris and almanac) TXD 6 to 20s CXD2930BR Reacquisition time (interrupt recovery time) 16ch GPS Processor RXD Less than 5 minutes: < 3 to 6s 5 minutes or more: < 6 to 10s • Positioning accuracy Flash ROM Stand alone (GPS unit only) 2M bit 1σ : < 30m 3σ : < 90m GPS Receiver System Diagram Using the CXD2930BR DGPS (differential GPS) 1σ : < 6m 3σ : < 18m • Measurement data update time Every 1s • Communication method Sony standard serial communication Supports NMEA ∗ The noted values may be exceeded depending on the operating environment and other conditions. The above performance values are as of February 1998. Sony reserves the right to change performance without prior notice. Accordingly, the above performance values should be used only as reference data. –2– CXD2930BR XCS0 DWR DRD DB (0:7) DADR (0:15) DCS0 to 5/PORT (16:21) IWR IRD IB (0:15) ICS0, 1 IADR (0:18) Block Diagram TEST0 to 1 BIU PORT (0:15) RUN COSEL HOLD MCKI NMI 32 bit RISC PMI MCKO INBKOR CLKOUT HOLDA EXRS SINT/PORT (22) PWRST 32K Byte SRAM TXD0 to 2 VDD × 10 VSS × 10 UART (Baud Rate Generator) × 3 RXD0 to 2 TIMER × 3 AVD 8bit ADC 16ch GPS DSP AVS VRT –3– AVIN TCXO XTCXO OTCXO INLW INHI CCKI CCKO IF0 IF0O IF1 VRB CXD2930BR IB9 IB10 VDD IB11 IB12 IB13 IB14 IB15 DRD DWR XCS0 DADR0 DADR1 VSS DADR2 DADR3 DADR4 DADR5 DADR6 DADR7 DADR8 DADR9 VDD DADR10 DADR11 DADR12 DADR13 DADR14 DADR15 DB0 DB1 VSS DB2 DB3 DB4 DB5 Pin Configuration 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 DB6 109 72 IB8 DB7 110 71 IB7 SINT/PORT22 111 70 VSS DCS0/PORT21 112 69 IB6 VDD 113 68 IB5 DCS1/PORT20 114 67 IB4 DCS2/PORT19 115 66 IB3 DCS3/PORT18 116 65 IB2 DCS4/PORT17 117 64 IB1 DCS5/PORT16 118 63 VDD PORT15 119 62 IB0 PORT14 120 61 IADR18 VSS 121 60 IADR17 PORT13 122 59 IADR16 PORT12 123 58 IADR15 PORT11 124 57 IADR14 PORT10 125 56 IADR13 PORT9 126 55 VSS PORT8 127 54 IADR12 PORT7 128 53 IADR11 VDD 129 52 IADR10 PORT6 130 51 IADR9 PORT5 131 50 IADR8 PORT4 132 49 IADR7 PORT3 133 48 IADR6 PORT2 134 47 VDD PORT1 135 46 IADR5 PORT0 136 45 IADR4 VSS 137 44 IADR3 TXD2 138 43 IADR2 RXD2 139 42 IADR1 TXD1 140 41 IADR0 RXD1 141 40 ICS1 TXD0 142 39 VSS RXD0 143 38 ICS0 VDD 144 IWR RUN VDD CLKOUT COSEL MCKO MCKI VSS PWRST EXRS INBKOR VDD HOLDA XTCXO PMI TCXO NMI VSS HOLD AVS VDD VRB IF1 VRT –4– IF0O AVD IF0 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 INLW 8 INHI 7 VSS 6 CCKO 5 CCKI 4 TEST1 3 TEST0 2 OTCXO 1 AVIN 37 IRD CXD2930BR Pin Configuration Pin No. Symbol Description I/O 1 AVD — 2 AVIN I 3 VRT I 4 VRB I 5 AVS — 6 VSS I 7 TCXO I 8 XTCXO O 9 VDD — Power supply. 10 OTCXO O TCXO clock output. 11 TEST0 I 12 TEST1 I 13 CCKI I 14 CCKO O 15 VSS — 16 INHI I Fixed to low level. 17 INLW I Fixed to low level. 18 IF0 I 19 IF0O O 20 IF1 I 21 VDD — 22 HOLD I Hold input signal. Hold when high level. 23 NMI I Non maskable interrupt. 24 PMI I Power management interrupt. 25 HOLDA O Hold acknowledge signal. 26 INBKOR O Break signal for debugging. 27 EXRS I Reset input signal. 28 PWRST I Connect to main power supply. Leave open during backup. 29 VSS 30 MCK I 31 MCKO O 32 COSEL I CPU clock select signal. Selects TCXO clock when low level; MCK clock when high level. 33 CLKOUT O CPU clock output. — A/D converter power supply. Analog input. Reference input. A/D converter GND. GND TCXO binary conversion circuit/crystal oscillator. Test. Fixed to low level. Timer oscillation circuit. (32.768kHz ± 100ppm) GND IF signal binary conversion circuit. IF signal input 1. Input the binary-converted input signal. Power supply. GND CPU clock oscillation circuit. –5– CXD2930BR Pin No. Symbol Description I/O 34 VDD — Power supply. 35 RUN O Signal output indicating CPU operating status. 36 IWR O Write signal output for instruction ROM. 37 IRD O Read signal for instruction ROM. 38 ICS0 O Chip select 0 for instruction ROM. 39 VSS — GND 40 ICS1 O Chip select 1 for instruction ROM. 41 IADR0 O (LSB) 42 IADR1 O 43 IADR2 O 44 IADR3 O 45 IADR4 O 46 IADR5 O 47 VDD — 48 IADR6 O 49 IADR7 O 50 IADR8 O 51 IADR9 O 52 IADR10 O 53 IADR11 O 54 IADR12 O 55 VSS — 56 IADR13 O 57 IADR14 O 58 IADR15 O 59 IADR16 O 60 IADR17 O 61 IADR18 O (MSB) 62 IB0 O (LSB) Data bus I/O for instruction ROM. 63 VDD — Power supply. 64 IB1 I/O 65 IB2 I/O 66 IB3 I/O 67 IB4 I/O 68 IB5 I/O 69 IB6 I/O Address signal for instruction ROM. Power supply. Address signal for instruction ROM. GND Address signal for instruction ROM. Data bus I/O for instruction ROM. –6– CXD2930BR Pin No. Symbol Description I/O 70 VSS — 71 IB7 I/O 72 IB8 I/O 73 IB9 I/O 74 IB10 I/O 75 VDD — 76 IB11 I/O 77 IB12 I/O 78 IB13 I/O 79 IB14 I/O 80 IB15 I/O (MSB) 81 DRD O Read signal for external expansion data memory. 82 DWR O Write signal for external expansion data memory. 83 XCS0 O Chip select signal for external expansion data memory. 84 DADR0 I/O 85 DADR1 I/O (LSB) Address I/O for external expansion data memory. 86 VSS — GND 87 DADR2 I/O 88 DADR3 I/O 89 DADR4 I/O 90 DADR5 I/O 91 DADR6 I/O 92 DADR7 I/O 93 DADR8 I/O 94 DADR9 I/O 95 VDD — 96 DADR10 I/O 97 DADR11 I/O 98 DADR12 I/O 99 DADR13 I/O 100 DADR14 I/O 101 DADR15 I/O 102 DB0 I/O 103 DB1 I/O (MSB) 104 VSS — GND GND Data bus I/O for instruction ROM. Power supply. Data bus I/O for instruction ROM. Address I/O for external expansion data memory. Power supply. Address I/O for external expansion data memory. –7– CXD2930BR Pin No. Symbol Description I/O 105 DB2 I/O 106 DB3 I/O 107 DB4 I/O 108 DB5 I/O 109 DB6 I/O 110 DB7 I/O (MSB) 111 SINT/PORT22 I/O External interrupt input signal/general-purpose I/O port. This pin can be used as a general-purpose I/O port according to the internal registers. 112 DCS0/PORT21 I/O Chip select for external expansion data memory/general-purpose I/O port. This pin can be used as a general-purpose I/O port according to the internal registers. 113 VDD Power supply. 114 DCS1/PORT20 I/O 115 DCS2/PORT19 I/O 116 DCS3/PORT18 I/O 117 DCS4/PORT17 I/O 118 DCS5/PORT16 I/O 119 PORT15 I/O 120 PORT14 I/O 121 VSS — 122 PORT13 I/O 123 PORT12 I/O 124 PORT11 I/O 125 PORT10 I/O 126 PORT9 I/O 127 PORT8 I/O 128 PORT7 I/O 129 VDD — 130 PORT6 I/O 131 PORT5 I/O 132 PORT4 I/O 133 PORT3 I/O 134 PORT2 I/O 135 PORT1 I/O 136 PORT0 I/O — (LSB) Data bus I/O for external expansion data memory. Chip select for external expansion data memory/general-purpose I/O port. These pins can be used as general-purpose I/O ports according to the internal registers. General-purpose I/O port. GND General-purpose I/O port. Power supply. General-purpose I/O port. –8– CXD2930BR Pin No. Symbol Description I/O 137 VSS — GND 138 TXD2 O UART transmission data output (channel 2). 139 RXD2 I UART reception data input (channel 2). 140 TXD1 O UART transmission data output (channel 1). 141 RXD1 I UART reception data input (channel 1). 142 TXD0 O UART transmission data output (channel 0). 143 RXD0 I UART reception data input (channel 0). 144 VDD — Power supply. –9– CXD2930BR Absolute Maximum Ratings • Supply voltage VDD VSS – 0.5 to 4.6 • Input voltage VI VSS – 0.5 to VDD + 5 • Output voltage VO VSS – 0.5 to VDD + 0.5 • Operating temperature Topr –40 to +85 • Storage temperature Tstg –55 to +150 V V V °C °C I/O Pin Capacitance • Input capacitance • Output capacitance • I/O capacitance pF pF pF CIN COUT CI/O 9 (Max.) 11 (Max.) 11 (Max.) Electrical Characteristics (VDD = 3.0 to 3.6V, Topr = –40 to +85°C) Symbol Item Conditions Min. Input voltage (1) (CMOS level) High level VIH (1) Low level VIL (1) Input voltage (2) (5V interface) High level VIH (2) Low level VIL (2) High level VOH (1) IOH = –4.0mA Low level VOL (1) IOL = 4.0mA High level VOH (2) IOH = –8.0mA Low level VOL (2) IOL = 8.0mA High level VOH (3) IOH = –12.0mA VDD – 0.4 Low level VOL (3) IOL = 12.0mA Output voltage (1) Output voltage (2) Output voltage (3) Current consumption in standby mode ISTB Supply current IDD Typ. 0.7VDD 0.7VDD Max. Unit VDD V 0.2VDD V 5.5 V 0.2VDD V VDD – 0.4 V 0.4 VDD – 0.4 V V 0.4 V V 0.4 VDD = 3V 20 70 VDD = 1.5V 4 50 f = 18.414MHz 55 V Applicable pins ∗1 ∗2 ∗3 ∗4 ∗5 µA mA Applicable pins ∗1 Pins 11, 12, 16, 17, 20, 22, 23, 24, 32 ∗2 Pins 62, 64 to 69, 72 to 74, 76 to 80, 84, 85, 87 to 94, 96 to 103, 105 to 112, 114 to 120, 122 to 128, 130 to 136, 139, 141, 143 ∗3 Pins 10, 25, 26, 33, 35, 41 to 46, 48 to 54, 56 to 61, 81 to 83, 138, 140, 142 ∗4 Pins 38, 40, 62, 64 to 69, 71 to 74, 76 to 80, 84, 85, 87 to 94, 96 to 103, 105 to 112, 114 to 120, 122 to 128, 130 to 136 ∗5 Pins 36, 37 – 10 – CXD2930BR Electrical Characteristics (IF and TCXO binary conversion pins) (VDD = 3.0 to 3.6V, Topr = –40 to +85°C) Item Symbol Logical Vth LVth Input amplitude VIN Conditions f = 50MHz, sin wave Symbol Input voltage Output voltage Max. Unit V 0.8 Vp-p Applicable pins Pins 7, 18 (VDD = 3.0 to 3.6V, Topr = –40 to +85°C) Conditions Min. LVth Logical Vth Typ. VDD/2 Electrical Characteristics (Crystal oscillator) Item Min. Typ. Max. VDD/2 High level VIH Low level VIL High level VOH IOH = –3mA Low level VOL IOL = 3mA Applicable pins V 0.7VDD V 0.2VDD – 11 – Unit VDD/2 V V VDD/2 Pin 30 V Pin 31 CXD2930BR AC Characteristics (1) When inputting a pulse to the TCXO pin (VDD = 3.0 to 3.6V, Topr = –40 to +85°C) When inputting a binary-converted signal 1/fTCK tTH tTL TCXO Item Symbol TCXO clock frequency fTCK TCXO clock pulse width tTH, tTL Min. Typ. Max. Unit Typ. – 3ppm 18.414 Typ. + 3ppm MHz 29.9 ns 24.5 When performing binary conversion with the TCXO and XTCXO pins (Pins 7 and 8) 0.01µF 0.8Vp-p or more VDD/2 7 1MΩ 8 (2) When performing self-oscillation with the CCKI and CCKO pins (VDD = 3.0 to 3.6V, Topr = –40 to +85°C) 220pF 13 10MΩ 220pF 32.768kHz ± 100ppm – 12 – 14 CXD2930BR (3) IF signal input (VDD = 3.0 to 3.6V, Topr = –40 to +85°C) 0.01µF 0.8Vp-p or more 18 VDD/2 1MΩ 19 (4) When performing self-oscillation with the MCKI and MCKO pins (VDD = 3.0 to 3.6V, Topr = –40 to +85°C) 15pF 30 Crystal 1MΩ 15pF 31 – 13 – CXD2930BR Battery Backup Mode The battery backup mode is activated when the power for the GPS receiver is turned off and power-on reset goes to low level. The timer clock continues to operate even when power-on reset goes low, but all other clocks are fixed high and the LSI is set to the low power consumption mode. At this time, the RAM data is held and the registers are initialized. Battery backup mode is canceled by setting power-on reset to high. 10 clocks Power-on reset EXRS PWRST 100ms or more Timer clock CCKI, CCKO Other clocks TCXO, XTCXO, MCKI, MCKO Normal outputs TXD0 to 2, OTCXO, OSO1 to 2, HOLDA Fixed low Tri-state outputs INBKOR, RUN, CLKOUT Fixed low Tri-state outputs ICS0, ICS1, IADR [18:0], IRD, IWR, DRD, DWR, XCS0 Hi-Z Bidirectional (Input) (Output) SINT, IB [15:0], DCS0 to 5, DADR [15:0] DB [7:0], PORT [15:0] Fixed low Hi-Z Inputs RXD0 to 2, ITCXO, IF0 to 2, OSI1, HOLD, NMI, PMI, DREADY Fixed low – 14 – CXD2930BR CXD2930BR Startup and Initialization The CXD2930BR operation is started by setting the reset input signal EXRS (Pin 30) to high level. The timing should satisfy the conditions noted below. 1. During power-on (power-on reset) VDD = 3.0 to 3.6V, Topr = –40 to +85°C VDD VDD [V] Power supply, PWRST (Pin 28) EXRS (Pin 27) 100ms or more VDD/2 GND The PWRST (Pin 28) signal should rise simultaneously with the power supply. The EXRS (Pin 27) signal should rise 100ms or more after the power supply and the PWRST signal have risen. Note that the PWRST signal should be left open during battery backup. 2. Initialization during operation VDD = 3.0 to 3.6V, Topr = –40 to +85°C Power supply, PWRST (Pin 28) VDD EXRS (Pin 27) VDD [V] 100µs or more VDD/2 GND The internal registers can be initialized during operation by setting the EXRS (Pin 27) signal to low level for 100µs or more. Keep the PWRST (Pin 28) signal at high level at this time. – 15 – CXD2930BR External Command Fetch Timing CLKOUT (a) (b) IADR (c) (d) ICS0, ICS1 (e) (f) IRD (g) (16) IB No. (h) Item Min. Typ. Max. Unit (a) Read cycle time (Fex: @9.207MHz) — 108 — ns (b) Address delay time — — 5 ns (c) Chip select fall delay time 2 — 10 ns (d) Chip select rise delay time 2 — 9 ns (e) Read signal fall delay time 1 — 3 ns (f) Read signal rise delay time 1 — 5 ns (g) Read data setup time 8 — — ns (h) Read data hold time 0 — — ns – 16 – CXD2930BR External Data Access Timing (ICS0, ISC1) (1) Read (half-word access) CLKOUT (a) (b) IADR (c) (d) (e) (f) ICS0, ICS1 IRD (g) (16) IB (h) (2) Write (half-word access) CLKOUT (a) (b) IADR (c) (d) ICS0, ICS1 (i) (j) IWR (k) (16) IB (l) No. Item Min. Typ. Max. Unit (a) Read/write cycle time (Fex: @9.207MHz) — 108 — ns (b) Address delay time — — 5 ns (c) Chip select fall delay time 2 — 10 ns (d) Chip select rise delay time 2 — 9 ns (e) Read signal fall delay time 1 — 3 ns (f) Read signal rise delay time 1 — 5 ns (g) Read data setup time 8 — — ns (h) Read data hold time 0 — — ns (i) Write signal fall delay time 0 — 1 ns (j) Write signal rise delay time 0 — 2 ns (k) Write data established time — — 5 ns (l) Write data hold time 5 — — ns – 17 – CXD2930BR (3) Read (word access) CLKOUT IADR ICS0, ICS1 IRD IB L (16) H (16) (4) Write (word access) CLKOUT IADR ICS0, ICS1 IWR IB L (16) – 18 – H (16) CXD2930BR External Data Access Timing (XCS0, DCS0 to 5, no data wait) (1) Read (byte access, no data wait) CLKOUT (a) (b) DADR (c) (d) XCS0, DCS0 to 5 (e) (f) DRD (g) (8) DB (h) (2) Write (byte access, no data wait) CLKOUT (a) (b) DADR (c) (d) XCS0, DCS0 to 5 (i) (j) DWR (k) (8) DB (l) Item No. Min. Typ. Max. Unit (a) Read/write cycle time (Fex: @9.207MHz) — 108 — ns (b) Address delay time — — 9 ns (c) Chip select fall delay time 4 — 13 ns (d) Chip select rise delay time 4 — 13 ns (e) Read signal fall delay time 2 — 8 ns (f) Read signal rise delay time 3 — 10 ns (g) Read data setup time 16 — — ns (h) Read data hold time 0 — — ns (i) Write signal fall delay time 0 — 1 ns (j) Write signal rise delay time 0 — 2 ns (k) Write data established time — — 7 ns (l) Write data hold time 5 — — ns – 19 – CXD2930BR (3) Read (half-word access, no data wait) CLKOUT DADR XCS0, DCS0 to 5 DRD DB H (8) H (8) L (8) H (8) (4) Write (half-word access, no data wait) CLKOUT DADR XCS0, DCS0 to 5 DWR DB (5) Read (word access, no data wait) CLKOUT DADR XCS0, DCS0 to 5 DRD DB HH (8) HL (8) LH (8) LL (8) LH (8) HL (8) HH (8) (6) Write (word access, no data wait) CLKOUT DADR XCS0, DCS0 to 5 DWR DB LL (8) – 20 – CXD2930BR External Data Access Timing (XCS0, DCS0 to 5, with data wait) (1) Read (byte access, with data wait) CLKOUT DADR XCS0, DCS0 to 5 DRD DB (8) (2) Write (byte access, with data wait) CLKOUT DADR XCS0, DCS0 to 5 DWR DB (8) (3) Read (half-word access, with data wait) CLKOUT DADR XCS0, DCS0 to 5 DRD DB H (8) L (8) (4) Write (half-word access, with data wait) CLKOUT DADR XCS0, DCS0 to 5 DWR DB L (8) H (8) – 21 – CXD2930BR (5) Read (word access, with data wait) CLKOUT DADR XCS0, DCS0 to 5 DRD DB HH (8) HL (8) LH (8) LL (8) (6) Write (word access, with data wait) CLKOUT DADR XCS0, DCS0 to 5 DWR DB LL (8) LH (8) – 22 – HL (8) HH (8) CXD2930BR Description of Application Circuit See the Application Circuit when using the CXD2930BR to configure a GPS receiver. Points for caution are as follows. 1. Unused pins Software processing is performed to prevent undesired current from flowing to unused pins in the circuit diagram, so leave these pins open. 2. TCXO input The TCXO frequency is 18.414MHz ± 3ppm. Signals that have not been binary-converted should be input with an amplitude of 0.8Vp-p or more via a DC filter capacitor (C19 in the circuit diagram). Input binaryconverted signals directly to Pin 7 (TCXO) without passing through C19 or R1 in the circuit diagram. Make sure the input level at this time satisfies the Electrical Characteristics. 3. IF input The CXD2930BR interface is 1.023MHz, and does not accept other frequencies. Signals that have not been binary-converted should be input with an amplitude of 0.8Vp-p or more via a DC filter capacitor (C20). Input binary-converted signals directly to Pin 18 (IF0) without passing through C20 or R3 in the circuit diagram. Make sure the input level at this time satisfies the Electrical Characteristics. 4. TXD (SIO output) The TXD amplitude low level is 0.4V or less, and the high level is VDD – 0.4V (VDD = 3.0 to 3.6V) or more. When the LSI, etc., connected to TXD operates at 5V and has a CMOS input level, perform 3 to 5V conversion before inputting the signal. 5. Real-time clock The current software version uses an external real-time clock. Consult your Sony representative beforehand when using the internal real-time clock. When using an external real-time clock, connect Pin 13 (CCKI) to GND. 6. External program ROM Use a 2M- or 4M-bit external program ROM (IC2) with an access time of 100ns or less and which is capable of 16-bit read. – 23 – 4 5 6 7 IF (1.023MHz) RESET GND IF RESET TCXO VSS VDD C11 3.3 D2 RB400D-T146 VDD BT1 3.0V 1 ∗ Input 3.6V in consideration of voltage step-down by diode (D2). 3 RXD 2 TXD TCXO (18.414MHz) 1 CN1 3.6V∗ RXD0 TXD0 D1 RB400D-T146 2 3 4 5 VOUT NC VIN NC GND VSS C13 0.1 X1 5 32.768k C6 6 10p 7 C9 8 10p VSS 4 VDD CE 1 OSCI SCL 2 OSCO SIO 3 INT IC4 RS5C313 C10 0.1 C5 0.1 C2 0.1 IB9 IB14 IB15 DADR5 DADR6 DADR7 DADR1 DADR2 DADR3 DADR8 DADR9 VDD DADR10 DADR11 DADR12 DADR13 DADR14 DADR15 DB0 DB1 VSS AVS DB2 DB3 IB7 71 IB8 72 3 VRT 4 5 6 7 C19 0.01 C14 0.1 When using the internal timer C15 C16 220p 220p R2 10M X2 32.768k C20 0.01 R3 1M C17 0.1 C18 0.1 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 R1 1M 8 ICS0 38 IRD 37 VSS 39 ICS1 40 IADR0 41 IADR1 42 IADR2 43 IADR3 44 IADR4 45 IADR5 46 VDD 47 IADR6 48 IADR7 49 IADR8 50 IADR9 51 IADR10 52 IADR11 53 IADR12 54 VSS 55 VDD IADR2 IADR1 IADR16 IADR15 IB1 IB9 IB2 IB10 IB3 IADR10 IADR9 IADR8 IADR7 IADR6 VSS VDD IADR1 IADR2 IADR3 IADR4 IADR5 IB8 IADR11 IB11 IB0 IADR12 IADR13 IADR14 IADR3 IADR4 IADR5 IADR17 IADR18 C7 0.1 IADR7 IB1 IB0 IADR8 IB2 IADR6 IADR18 C4 0.1 VSS IB3 IB4 IB5 IB6 IB7 IB8 VCC 23 DQ4 24 DQ12 25 DQ5 26 DQ13 27 DQ6 28 DQ14 29 DQ7 30 DQ15 31 GND 32 BYTE 33 A16 34 A15 35 A14 36 A13 37 A12 38 A11 39 A10 40 A9 41 A8 42 WE 43 RESET 44 IADR (18:1) 22 DQ11 21 DQ3 20 DQ10 19 DQ2 18 DQ9 17 DQ1 16 DQ8 15 DQ0 14 OE 13 GND 12 CE 11 A0 10 A1 9 A2 8 A3 7 A4 6 A5 5 A6 4 A7 3 A17 2 RY/BY 1 NC IC2 29LV400T-90 IB (15:0) VDD VSS C8 0.1 IB4 IB12 IB5 IB13 IB6 IB14 IB7 IB15 IADR17 IADR16 IADR15 IADR14 IADR13 IADR12 IADR11 IADR10 IADR9 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 2 1 143 RXD0 144 VDD 142 TXD0 141 RXD1 140 TXD1 139 RXD2 138 TXD2 137 VSS 136 PORT0 135 PORT1 134 PORT2 133 PORT3 132 PORT4 131 PORT5 130 PORT6 129 VDD 128 PORT7 127 PORT8 126 PORT9 IADR13 56 VRB 125 PORT10 VSS IADR14 57 TCXO 124 PORT11 XTCXO IADR15 58 VDD 123 PORT12 OTCXO IADR16 59 TEST0 IADR17 60 TEST1 122 PORT13 CCKI 121 VSS CCKO IADR18 61 VSS 120 PORT14 INHI IB0 62 INLW 119 PORT15 IF0 VDD 63 IF0O 118 DCS5/PORT16 VDD IB1 64 HOLD 117 DCS4/PORT17 PMI IB2 65 HOLDA 116 DCS3/PORT18 INBKOR IB3 66 EXRS 115 DCS2/PORT19 PWRST IB4 67 VSS 114 DCS1/PORT20 IC1 CXD2930BR VSS NMI IB5 68 XCS0 IB6 69 DADR0 113 VDD DWR 112 DCS0/PORT21 DRD VSS 70 IB15 111 SINT/PORT22 MCKI 109 DB6 110 DB7 IB14 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 C1 0.1 DADR4 IF1 C3 0.1 VDD IB13 IB13 MCKO VSS IB12 IB12 COSEL DB5 AVD When using an external timer VSS IB11 IB11 CLKOUT DB4 AVIN IC3 5812185G VDD IB10 IB10 RUN Recommended components IC1: CXD2930BR IC2: Flash memory Made by Fujitsu and INTEL, 2M- or 4M-bit, access time of 100ns or less (3V and 5V operation) IC3: Real-time clock Made by RICOH (RS5C313) IC4: Voltage regulator (for step-down transformation) Made by SEIKO INSTRUMENTS (S81218SG, steps down 3V to 1.8V) TCXO: Made by Tokyo Denpa Oscillator frequency: 18.414MHz ± 3ppm VDD VDD VDD IB9 IWR – 24 – VSS Application Circuit CXD2930BR CXD2930BR Package Outline Unit: mm 144PIN LQFP (PLASTIC) 22.0 ± 0.2 1.7 MAX 20.0 ± 0.1 1.4 ± 0.1 73 108 109 72 B A 37 144 1 36 0.5 0.22 ± 0.05 0.08 M 0.1 S S 0.1 ± 0.05 DETAIL A DETAIL B 0.145 ± 0.03 (0.2) (0.125) 0° to 10° 0.5 ± 0.15 (21.0) 0.22 ± 0.05 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING SONY CODE LQFP-144P-L01 LEAD TREATMENT EIAJ CODE LQFP144-P-2020 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 1.3 g JEDEC CODE – 25 – S