INTEGRATED CIRCUITS DATA SHEET SAA6750H Encoder for MPEG2 image recording (EMPIRE) Product specification Supersedes data of 1998 Sep 07 File under Integrated Circuits, IC02 2000 May 03 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) CONTENTS 1 FEATURES 2 GENERAL DESCRIPTION 2.1 2.2 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 General Function Application fields General Video editing (PC applications) Camera signal transmission Video recording for surveillance Digital VCR 3 QUICK REFERENCE DATA 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING 7 FUNCTIONAL DESCRIPTION 7.1 7.1.1 7.1.2 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.3 7.3.1 7.3.2 7.3.3 7.4 7.4.1 7.4.2 7.5 7.5.1 7.5.2 7.6 7.6.1 7.6.2 7.6.3 7.7 Global architecture description General Architecture structure Start-up and operating modes Start-up requirements Reset processing Description of operating modes Pin behaviour Video front-end and formatter General Data input format Functional description Macroblock processor General Functional description Bitstream assembly General Pre-packer and packer Data output port General Data output format Functional description Application Specific Instruction-set Processor (ASIP) General 7.7.1 2000 May 03 7.8 7.8.1 7.9 7.9.1 7.9.2 7.9.3 7.9.4 7.9.5 7.10 7.10.1 7.10.2 7.10.3 7.11 7.12 7.13 7.14 7.14.1 7.14.2 7.14.3 Global controller General I2C-bus interface and controller General Special considerations I2C-bus data transfer modes I2C-bus memories and registers I2C-bus initialization DRAM interface General Application hints Functional description FIFO memories Clock distribution Input/output levels Boundary scan test General Initialization of boundary scan circuit Device identification codes 8 LIMITING VALUES 9 THERMAL CHARACTERISTICS 10 CHARACTERISTICS 11 APPLICATION INFORMATION 12 PACKAGE OUTLINE 13 SOLDERING 13.1 Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods 13.2 13.3 13.4 13.5 2 SAA6750H 14 DATA SHEET STATUS 15 DEFINITIONS 16 DISCLAIMERS 17 PURCHASE OF PHILIPS I2C COMPONENTS Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) 1 SAA6750H FEATURES • Digital YUV input according to “ITU-T 601” and “ITU-T 656” • NTSC and PAL (720 pixels × 480 lines at 60 Hz and 720 pixels × 576 lines at 50 Hz) • Integrated colour conversion 4 : 2 : 2 to 4 : 2 : 0 • The patented, motion-compensated temporal noise filtering which was developed by Philips for professional equipment reduces noise in the input video before compression is performed. This technique gives visible improvements in picture quality, especially in the field of home recordings with noisy signal sources where this has proved to be of significant benefit. • Integrated format conversion to SIF format (optional) • Real time MPEG2 Simple Profile at Main Level (SP@ML) encoding • IP frame or I frame only encoding supported • Programmable Group Of Pictures (GOP) size • Integrated motion estimation, half pixel accuracy Internally the SAA6750H uses a hardware solution for data compression and a specially developed high performance processor for control purposes. • Motion compensated noise reduction • Elementary stream data output compliant to MPEG2 standard (“ISO 13818-2”) 2.2 • Bitstream output compatible to 16-bit parallel interface with Motorola (68xxx like) protocol style The SAA6750H is a stand-alone single chip video encoder performing real time MPEG2 compression of digital video data. • No external host processor required • 4 × 4 Mbit external DRAM required The video data input of the SAA6750H accepts a digital YUV video data stream in ITU-T 601 format. PAL standard at 50 Hz and 720 pixels by 576 lines, as well as NTSC at 60 Hz and 720 pixels by 480 lines, are covered. The video synchronization may either follow ITU-T 656 recommendation or can also be supplied by external signals. The external reference clock of 27 MHz to pin VCLK has to be synchronized to the video data. The product family SAA7111 of Philips Semiconductors provides a suitable video data stream and reference clock. Other sources are also supported by the flexible I2C-bus controlled data input interface of the SAA6750H. See Section 7.3 for detailed information. • I2C-bus controlled • Single external video clock 27 MHz • Power supply voltage 3.3 V • Digital inputs 5 V tolerant • Boundary Scan Test (BST) supported. 2 2.1 GENERAL DESCRIPTION General The SAA6750H is a new approach towards a stand-alone MPEG2 video encoder IC. It combines high quality SP@ML compliant real time encoding with cost-effectiveness, allowing for the first time the use of an MPEG2 encoder IC in applications and markets with a high cost pressure. This has been achieved by means of a number of innovations in architecture and algorithms developed by the Philips Research Laboratories, e.g.: An internal 4 : 2 : 2 to 4 : 2 : 0 colour format conversion is performed. Optionally, a ITU-T 601 to SIF format conversion may be activated by the I2C-bus control settings. The real time data encoding part of the SAA6750H combines high-compression rates with high quality picture performance. This is achieved by the integration of Philips unique motion estimation algorithm and a patented motion-compensated noise filtering. The compression algorithm uses I or IP mode encoding. Normally it selects automatically the suitable mode but may also be forced to I mode operating only by the I2C-bus control settings. • The unique motion estimation algorithm supports highly efficient encoding by using only I frame and IP frame mode. B frames need not be used. This leads to a significantly smaller internal circuitry and also reduces DRAM memory requirements from at least 4 to 2 Mbyte. In addition, the absence of B frames simplifies editing of the compressed data stream. 2000 May 03 Function 3 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) SAA6750H 2.3.2 In contrast to the encoding part which is designed in dedicated hardware, control functions and data stream handling tasks such as e.g. header generation and bit-rate control are carried out by a dedicated control processor, the so-called Application Specific Instruction-set Processor (ASIP). The ASIP’s microcode is contained in an internal RAM and is loaded via the I2C-bus before start of operation. For video editing the SAA6750H can be interfaced gluelessly to a video input processor with ITU-T 656 compliant digital video output. In order to link the SAA6750H to the PC, the use of the PCI bridge SAA7146 is recommended. By this bridge the MPEG2 video ES can be transmitted via the PCI-bus to a HardDisc (HD). Furthermore all the I2C-bus settings can be send from the PC via the bridge to the I2C-bus components on the encoder board. The SAA7146 supports Pulse Code Modulation (PCM) audio capturing. Multiplexing with an audio stream or audio encoding can be done by the CPU of the PC. A block diagram is shown in Fig.18. The ASIP is able to communicate with the outside world via the I2C-bus. The SAA6750H generates an MPEG2 Elementary Stream (ES) in accordance with the MPEG2 standard (“ISO 13818-2”). The 16-bit data output interface supports Motorola (68xxx like) protocol style. 2.3.3 Data processing and control functions are managed by loosely coupled processes. FIFO memories are used to connect these processes. In addition to these internal storages the SAA6750H needs 4 × 4 Mbit of external DRAM memory (tRAC = 60 ns). A block diagram is shown in Fig.1. 2.3.1 2.3.4 VIDEO RECORDING FOR SURVEILLANCE For surveillance systems VCRs with a huge amount of storage capacity are required. A high picture resolution is very important when there is action in the captured picture. The SAA6750H can control the encoded bit-rate by motion detection by its integrated motion estimation algorithm. Doing so the bit-rate can vary from 0.5 to 10 Mbit/s. VCRs with a storage space of 6 month are possible. Application fields GENERAL The SAA6750H can be applied within the following application domains: 2.3.5 DIGITAL VCR In stand-alone VCRs the SAA6750H works together with an audio encoder and a multiplexer. The SAA6750H is clocked by the video clock of the video input processor (SAA7111 or derivatives). A master clock is derived from the frame pulse. The video clock and master clock domain are de-coupled by a FIFO. The audio clock can be derived from the master clock. The video Packetized Elementary Stream (PES) packetizer has to take care of the fullness of the output buffer of the SAA6750H. • Video editing (PC applications) • Camera signal transmission • Digital Versatile Disc (DVD) recording • Video recording for surveillance • Digital VCR. All those systems have to compress video data in order to manage the storage or transmission of digitized video data. The SAA6750H can be handled for most of the applications as a stand-alone device. That means at start-up a microcode and a couple of the I2C-bus settings are loaded and the SAA6750H is started. If needed, settings such as GOP size or bit-rate are changed on-the-fly via the I2C-bus. 2000 May 03 CAMERA SIGNAL TRANSMISSION In this application the SAA6750H will be located inside a camera to compress the received digital video data for transmission. Selectable I2C-bus addresses and a special reset mode affecting the output pin behaviour allow the use of two SAA6750H devices in one application. 2.3 VIDEO EDITING (PC APPLICATIONS) 4 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) 3 SAA6750H QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT VDD digital supply voltage 3.0 3.3 3.6 V IDD(tot) total digital supply current − 0.22 0.56 A Ptot total power dissipation − 0.73 2.0 W fVCLK video clock frequency 25.6 27.0 28.6 MHz fSCL I2C-bus clock frequency 100 − 400 kHz B output bit-rate 1.5 − 40 Mbit/s VIH HIGH-level input voltage 2.0 − 5.5 V VIL LOW-level input voltage −0.5 − +0.8 V VOH HIGH-level output voltage 2.4 − VDD V VOL LOW-level output voltage − − 0.4 V Tamb ambient temperature 0 − 70 °C 4 ORDERING INFORMATION TYPE NUMBER SAA6750H 2000 May 03 PACKAGE NAME SQFP208 DESCRIPTION plastic shrink quad flat package; 208 leads (lead length 1.3 mm); body 28 × 28 × 3.4 mm; high stand-off height 5 VERSION SOT316-1 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 65 67 ADR8 to ADR0 OEN 68 69 9 DATA63 to DATA0 64, 62 to 59, 57 to 54 52 to 49, 47 to 44, 42 to 39, 37 to 34, 32 to 29, 20 to 17, 15 to 12, 10 to 7, 5 to 2, 208 to 205, 203 to 200, 198 to 195, 193 to 190, 188 to 185, 175 to 172, 170 to 167 64 101 DRAM INTERFACE 125 124 YUV7 to YUV0 FID HSYNC VSYNC 6 VCLK (27 MHz) 87 to 84, 74 to 71 138 143 148 153 MEM_ST CSN I_MN to 141, to 146, to 151, to 156 VSS 8 AD15 to AD0 16 89 LINE BASED PROCESSING 90 MACROBLOCK BASED PROCESSING BITSTREAM BASED PROCESSING DATA OUTPUT PORT 123 135 91 136 93 CLOCK GENERATION DTACK_RDY AS_ALE DS_RDN VDD VDD 1.8 kΩ 1.8 kΩ 121 27 MHz LRQN 122 Philips Semiconductors 22, 24, 26, 76, 78, 80, 82, 126, 128, 130, 132, 134, 162, 178, 180, 182 WEN Encoder for MPEG2 image recording (EMPIRE) +3.3 V 6, 16, 28, 38, 48, 16 58, 66, 88, 94, 100, 110, 120, 142, 152, 166, 176, 194, 204 RASN BLOCK DIAGRAM +3.3 V CASN 5 18 VDDCO andbook, full pagewidth 2000 May 03 VDD URQN 106 GPIO0 107 GPIO1 RESETN SAA6750H 96 119 to 116, 114 to 111, 109, 108 GLOBAL CONTROLLER start MAD SDA SCL ASIP GPIO11 to GPIO2 10 VDD 97 1.8 kΩ I2C-BUS TRANSCEIVER 98 99 104 103 102 1, 11, 21, 33, 43, 53, 63, 70, 92, 95, 105, 115, 137, 147, 157, 171, 189, 199 16 23, 25, 27, 75, 77, 79, 81, 83, 127, 129, 131, 133, 177, 179, 181, 183 159 160 161 163 164 165 184 MHB661 VSS VSSCO TRST TCK TMS Fig.1 Block diagram. TDI CS_TEST TEST n.c. FAD_RWN VSS TDO SAA6750H 18 158 FAD_EN Product specification TEST CONTROL BLOCK FOR BOUNDARY SCAN TEST AND SCAN TEST FAD_RDYN Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) 6 SAA6750H PINNING SYMBOL PIN INPUT/OUTPUT(1) Imax (mA) DESCRIPTION VSS 1 ground − ground for pad ring DATA28 2 input/output 3 DRAM data interface bit 28 DATA29 3 input/output 3 DRAM data interface bit 29 DATA30 4 input/output 3 DRAM data interface bit 30 DATA31 5 input/output 3 DRAM data interface bit 31 VDD 6 supply − supply voltage for pad ring DATA32 7 input/output 3 DRAM data interface bit 32 DATA33 8 input/output 3 DRAM data interface bit 33 DATA34 9 input/output 3 DRAM data interface bit 34 DATA35 10 input/output 3 DRAM data interface bit 35 VSS 11 ground − ground for pad ring DATA36 12 input/output 3 DRAM data interface bit 36 DATA37 13 input/output 3 DRAM data interface bit 37 DATA38 14 input/output 3 DRAM data interface bit 38 DATA39 15 input/output 3 DRAM data interface bit 39 VDD 16 supply − supply voltage for pad ring DATA40 17 input/output 3 DRAM data interface bit 40 DATA41 18 input/output 3 DRAM data interface bit 41 DATA42 19 input/output 3 DRAM data interface bit 42 DATA43 20 input/output 3 DRAM data interface bit 43 VSS 21 ground − ground for pad ring VDDCO 22 supply − supply voltage for core logic VSSCO 23 ground − ground for core logic VDDCO 24 supply − supply voltage for core logic VSSCO 25 ground − ground for core logic VDDCO 26 supply − supply voltage for core logic VSSCO 27 ground − ground for core logic VDD 28 supply − supply voltage for pad ring DATA44 29 input/output 3 DRAM data interface bit 44 DATA45 30 input/output 3 DRAM data interface bit 45 DATA46 31 input/output 3 DRAM data interface bit 46 DATA47 32 input/output 3 DRAM data interface bit 47 VSS 33 ground − ground for pad ring DATA48 34 input/output 3 DRAM data interface bit 48 DATA49 35 input/output 3 DRAM data interface bit 49 DATA50 36 input/output 3 DRAM data interface bit 50 DATA51 37 input/output 3 DRAM data interface bit 51 VDD 38 supply − supply voltage for pad ring DATA52 39 input/output 3 DRAM data interface bit 52 2000 May 03 7 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) SYMBOL PIN INPUT/OUTPUT(1) SAA6750H Imax (mA) DESCRIPTION DATA53 40 input/output 3 DRAM data interface bit 53 DATA54 41 input/output 3 DRAM data interface bit 54 DATA55 42 input/output 3 DRAM data interface bit 55 VSS 43 ground − ground for pad ring DATA56 44 input/output 3 DRAM data interface bit 56 DATA57 45 input/output 3 DRAM data interface bit 57 DATA58 46 input/output 3 DRAM data interface bit 58 DATA59 47 input/output 3 DRAM data interface bit 59 VDD 48 supply − supply voltage for pad ring DATA60 49 input/output 3 DRAM data interface bit 60 DATA61 50 input/output 3 DRAM data interface bit 61 DATA62 51 input/output 3 DRAM data interface bit 62 DATA63 52 input/output 3 DRAM data interface bit 63 (MSB) VSS 53 ground − ground for pad ring ADR0 54 output/3-state 3 DRAM address interface bit 0 (LSB) ADR1 55 output/3-state 3 DRAM address interface bit 1 ADR2 56 output/3-state 3 DRAM address interface bit 2 ADR3 57 output/3-state 3 DRAM address interface bit 3 VDD 58 supply − supply voltage for pad ring ADR4 59 output/3-state 3 DRAM address interface bit 4 ADR5 60 output/3-state 3 DRAM address interface bit 5 ADR6 61 output/3-state 3 DRAM address interface bit 6 ADR7 62 output/3-state 3 DRAM address interface bit 7 VSS 63 ground − ground for pad ring ADR8 64 output/3-state 3 DRAM address interface bit 8 (MSB) CASN 65 output/3-state 6 DRAM column address strobe (active LOW) VDD 66 supply − supply voltage for pad ring RASN 67 output/3-state 3 DRAM row address strobe (active LOW) WEN 68 output/3-state 3 DRAM write enable (active LOW) OEN 69 output/3-state 3 DRAM chip select (active LOW) VSS 70 ground − ground for pad ring YUV0 71 input − video input signal bit 0 (LSB) YUV1 72 input − video input signal bit 1 YUV2 73 input − video input signal bit 2 YUV3 74 input − video input signal bit 3 VSSCO 75 ground − ground for core logic VDDCO 76 supply − supply voltage for core logic VSSCO 77 ground − ground for core logic VDDCO 78 supply − supply voltage for core logic VSSCO 79 ground − ground for core logic 2000 May 03 8 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) SYMBOL PIN INPUT/OUTPUT(1) SAA6750H Imax (mA) DESCRIPTION VDDCO 80 supply − supply voltage for core logic VSSCO 81 ground − ground for core logic VDDCO 82 supply − supply voltage for core logic VSSCO 83 ground − ground for core logic YUV4 84 input − video input signal bit 4 YUV5 85 input − video input signal bit 5 YUV6 86 input − video input signal bit 6 YUV7 87 input − video input signal bit 7 (MSB) VDD 88 supply − supply voltage for pad ring FID 89 input − odd/even field identification HSYNC 90 input − horizontal reference signal VSYNC 91 input − vertical reference signal VSS 92 ground − ground for pad ring VCLK 93 input − video clock input (27 MHz) VDD 94 supply − supply voltage for pad ring VSS 95 ground − ground for pad ring RESETN 96 input − hard reset input (active LOW) MAD 97 input − module address (I2C-bus) SDA 98 input/open-drain output 6 serial data input/output (I2C-bus) SCL 99 input/open-drain output − serial clock input (I2C-bus) VDD 100 supply − supply voltage for pad ring MEM_ST 101 output/3-state 3 do not use in the application (reserved) FAD_RWN 102 input − ASIP port data read/write FAD_EN 103 input − ASIP port data enable FAD_RDYN 104 open-drain output 3 ASIP port data ready (active LOW) VSS 105 ground − ground for pad ring GPIO0 106 input/output 3 ASIP port data bit 0 (LSB) GPIO1 107 input/output 3 ASIP port data bit 1 GPIO2 108 input/output 3 ASIP port data bit 2; note 2 GPIO3 109 input/output 3 ASIP port data bit 3; note 2 VDD 110 supply − supply voltage for pad ring GPIO4 111 input/output 3 ASIP port data bit 4; note 2 GPIO5 112 input/output 3 ASIP port data bit 5; note 2 GPIO6 113 input/output 3 ASIP port data bit 6; note 2 GPIO7 114 input/output 3 ASIP port data bit 7; note 2 VSS 115 ground − ground for pad ring GPIO8 116 input/output 3 ASIP port data bit 8; note 2 GPIO9 117 input/output 3 ASIP port data bit 9; note 2 GPIO10 118 input/output 3 ASIP port data bit 10; note 2 GPIO11 119 input/output 3 ASIP port data bit 11 (MSB); note 2 2000 May 03 9 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) SYMBOL PIN INPUT/OUTPUT(1) SAA6750H Imax (mA) DESCRIPTION VDD 120 supply − supply voltage for pad ring LRQN 121 open-drain output 3 output port lower watermark interrupt request (active LOW) URQN 122 open-drain output 3 output port upper watermark interrupt request (active LOW) DTACK_RDY 123 open-drain output 3 output port data transfer acknowledge/ready/request I_MN 124 input − output port reserved mode/Motorola bus style selection input (active LOW); with internal pull-up resistor CSN 125 input − output port chip select for external address mode (active LOW); with internal pull-up resistor VDDCO 126 supply − supply voltage for core logic VSSCO 127 ground − ground for core logic VDDCO 128 supply − supply voltage for core logic VSSCO 129 ground − ground for core logic VDDCO 130 supply − supply voltage for core logic VSSCO 131 ground − ground for core logic VDDCO 132 supply − supply voltage for core logic VSSCO 133 ground − ground for core logic VDDCO 134 supply − supply voltage for core logic AS_ALE 135 input − output port address strobe/address latch enable DS_RDN 136 input − output port data strobe/read VSS 137 ground − ground for pad ring AD15 138 input/output 3 output port multiplexed address/data line bit 15 (MSB) AD14 139 input/output 3 output port multiplexed address/data line bit 14 AD13 140 input/output 3 output port multiplexed address/data line bit 13 AD12 141 input/output 3 output port multiplexed address/data line bit 12 VDD 142 supply − supply voltage for pad ring AD11 143 input/output 3 output port multiplexed address/data line bit 11 AD10 144 input/output 3 output port multiplexed address/data line bit 10 AD9 145 input/output 3 output port multiplexed address/data line bit 9 AD8 146 input/output 3 output port multiplexed address/data line bit 8 VSS 147 ground − ground for pad ring AD7 148 input/output 3 output port multiplexed address/data line bit 7/data bus bit 7 (MSB) AD6 149 input/output 3 output port multiplexed address/data line bit 6/data bus bit 6 AD5 150 input/output 3 output port multiplexed address/data line bit 5/data bus bit 5 AD4 151 input/output 3 output port multiplexed address/data line bit 4/data bus bit 4 VDD 152 supply − supply voltage for pad ring AD3 153 input/output 3 output port multiplexed address/data line bit 3/data bus bit 3 AD2 154 input/output 3 output port multiplexed address/data line bit 2/data bus bit 2 AD1 155 input/output 3 output port multiplexed address/data line bit 1/data bus bit 1 AD0 156 input/output 3 output port multiplexed address/data line bit 0 (LSB)/data bus bit 0 (LSB) 2000 May 03 10 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) SYMBOL INPUT/OUTPUT(1) PIN SAA6750H Imax (mA) DESCRIPTION VSS 157 ground − ground for pad ring TDO 158 output 3 boundary scan test data output; pin not active during normal operating; with 3-state output; note 3 TRST 159 input − boundary scan test reset; pin must be set to LOW for normal operating; with internal pull-up resistor; notes 3 and 4 TCK 160 input − boundary scan test clock; pin must be set to LOW during normal operating; with internal pull-up resistor; note 3 TMS 161 input − boundary scan test mode select; pin must float or set to HIGH during normal operating; with internal pull-up resistor; note 3 VDDCO 162 supply − supply voltage for core logic TDI 163 input − boundary scan test data input; pin must float or set to HIGH during normal operating; with internal pull-up resistor; note 3 CS_TEST 164 input − test mode for the internal RAMs; pin must be set to LOW during normal operating TEST 165 input − test mode; pin must be set to LOW during normal operating VDD 166 supply − supply voltage for pad ring DATA0 167 input/output 3 DRAM data interface bit 0 (LSB) DATA1 168 input/output 3 DRAM data interface bit 1 DATA2 169 input/output 3 DRAM data interface bit 2 DATA3 170 input/output 3 DRAM data interface bit 3 VSS 171 ground − ground for pad ring DATA4 172 input/output 3 DRAM data interface bit 4 DATA5 173 input/output 3 DRAM data interface bit 5 DATA6 174 input/output 3 DRAM data interface bit 6 DATA7 175 input/output 3 DRAM data interface bit 7 VDD 176 supply − supply voltage for pad ring VSSCO 177 ground − ground for core logic VDDCO 178 supply − supply voltage for core logic VSSCO 179 ground − ground for core logic VDDCO 180 supply − supply voltage for core logic VSSCO 181 ground − ground for core logic VDDCO 182 supply − supply voltage for core logic VSSCO 183 ground − ground for core logic n.c. 184 − − reserved pin; do not connect DATA8 185 input/output 3 DRAM data interface bit 8 DATA9 186 input/output 3 DRAM data interface bit 9 DATA10 187 input/output 3 DRAM data interface bit 10 DATA11 188 input/output 3 DRAM data interface bit 11 VSS 189 ground − ground for pad ring DATA12 190 input/output 3 DRAM data interface bit 12 DATA13 191 input/output 3 DRAM data interface bit 13 2000 May 03 11 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) SYMBOL PIN INPUT/OUTPUT(1) SAA6750H Imax (mA) DESCRIPTION DATA14 192 input/output 3 DRAM data interface bit 14 DATA15 193 input/output 3 DRAM data interface bit 15 VDD 194 supply − supply voltage for pad ring DATA16 195 input/output 3 DRAM data interface bit 16 DATA17 196 input/output 3 DRAM data interface bit 17 DATA18 197 input/output 3 DRAM data interface bit 18 DATA19 198 input/output 3 DRAM data interface bit 19 VSS 199 ground − ground for pad ring DATA20 200 input/output 3 DRAM data interface bit 20 DATA21 201 input/output 3 DRAM data interface bit 21 DATA22 202 input/output 3 DRAM data interface bit 22 DATA23 203 input/output 3 DRAM data interface bit 23 VDD 204 supply − supply voltage for pad ring DATA24 205 input/output 3 DRAM data interface bit 24 DATA25 206 input/output 3 DRAM data interface bit 25 DATA26 207 input/output 3 DRAM data interface bit 26 DATA27 208 input/output 3 DRAM data interface bit 27 Notes 1. All input pins, input/output pins (in input mode), output pins (in 3-state mode) and open-drain output pins are 5.0 V tolerant. 2. This pin is recommended to be set to ground or to the supply voltage VDD via a resistor. 3. In accordance with the “IEEE 1149.1” standard. 4. Special function of pin TRST: a) For board designs without boundary scan implementation, pin TRST must be connected to ground. b) Pin TRST provides easy initialization of the internal BST circuit. By applying a LOW it can be used to force the internal Test Access Port (TAP) controller to the Test-Logic-Reset state (normal operating) at once. The 208 pins are divided in following groups: Others (14 pins): Video input port (11 pins): 1 video clock input pin 8 data pins and 3 control pins. 3 pins related to the I2C-bus 1 pin for reset control Data output port (23 pins): 7 pins for test purposes 16 data pins and 7 control pins. 1 pin not connected GPIO port (15 pins): 1 pin for internal test purposes. 12 data pins and 3 control pins. Supply (68 pins): DRAM (77 pins): 16 core supply pins 64 data pins 18 I/O cell supply pins 9 address pins 16 core ground pins 4 control pins. 18 I/O cell ground pins. 2000 May 03 12 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) handbook, halfpage 157 208 SAA6750H 156 1 SAA6750H 104 105 53 52 MBK768 Fig.2 Pin configuration. 7 FUNCTIONAL DESCRIPTION 7.1 7.1.1 Line based processing: Global architecture description Video front-end and formatter (see Section 7.3) including: 1. 4 : 2 : 2 to 4 : 2 : 0 pre-filter GENERAL The SAA6750H has a multi-processor architecture. The different processing and control modules are not locked to each other but run independently within the limits of the global scheduling. The data transfer between the processing units is carried out via FIFO memories or the external DRAM (see Fig.1). 2. Optional SIF subsampling. The set of functions of the SAA6750H is determined to a high extent by the microcode of the internal Application Specific Instruction-set Processor (ASIP). Detailed information is given in the software specification. 1. Discrete Cosine Transformation/Inverse Discrete Cosine Transformation (DCT/IDCT) Global settings and selection of the operating modes are carried out via the I2C-bus (see Sections 7.2 and 7.9). 3. Motion Estimation/Motion Compensation (ME/MC) 7.1.2 The video front-end processes the incoming video data and writes it to the external DRAM. Macroblock based processing: MacroBlock Processor (MBP) (see Section 7.4) including: 2. Variable Length Encoding/Run Length Encoding (VLE/RLE) 4. Motion Compensation Noise Reduction (MCNR) 5. Quantization/Inverse Quantization (Q/IQ) ARCHITECTURE STRUCTURE 6. Frame/Field (FF) reshuffling and ZigZag (ZZ) scan. The architecture consist of a data processing, a control and a memory part. 7.1.2.1 The MBP gets the pre-processed video data from the external DRAM and performs the data compression. Data processing part The data processing flow can be split-up as follows: 2000 May 03 13 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) SAA6750H After power-on and the related internal reset the initialization via the I2C-bus has to be carried out (see Section 7.9.5). It should be noted that a delay of at least 0.5 ms between the end of RESETN LOW state and start of the I2C-bus initialization sequence is required. See Table 1 for information about the operating modes. Bitstream based processing: Bitstream assembly (see Section 7.5) (Pre-packer, Packer, Stuffing unit and output buffer) and Data output port (see Section 7.6). The bitstream processing part gets the compressed data from the MBP and the header information from the control part. It provides an MPEG2 compliant Elementary Stream (ES) at the output. 7.1.2.2 7.2.2 The SAA6750H has internally an asynchronous and a synchronous reset processing. Control part The asynchronous reset is directly derived from the external reset signal RESETN and gets active as soon as RESETN becomes LOW. It is not depending on the external clock signal. The asynchronous reset forces the SAA6750H into reset mode which does directly affect the behaviour of the output and I/O pins (see Table 2). This does guarantee a defined state of the pins even if no clock signal is available. In addition it initiates the internal synchronous reset which gets active as soon as the VCLK signal is available. The control part consists of three modules: 1. Application Specific Instruction-set Processor (ASIP) (see Section 7.7): controls the MBP, generates motion vectors, headers and stuffing information 2. The global controller (see Section 7.8): generates the global scheduling information for the MBP, the DRAM interface and the ASIP 3. The I2C-bus interface and controller (see Section 7.9): download of ASIP microcode, tables and constants as well as MBP quantizer table, used for external control settings, allows communication between ASIP and application environment. 7.1.2.3 The internal synchronous reset is controlled by RESETN and the settings of control bits E_ST and E_SP. For proper operating the external clock signal VCLK has to be stable within the specified limits. Memory part The internal synchronous reset gets active if RESETN is LOW or by setting the control bits E_ST and E_SP to soft reset mode (see Table 1). It does affect all internal modules except the I2C-bus controller and therefore also the output and I/O pins (see Table 2). In addition, but only if combined with an external reset RESETN, it does reset the I2C-bus control register. It does not affect the contents of the embedded microcode and constant memories (see Section 7.9.4). The control and data processing modules exchange data via internal FIFOs and the external DRAM: 1. DRAM interface (see Section 7.10); provides access to the external DRAM memory 2. FIFO memories (see Section 7.11); a number of FIFOs of different size is used to connect internal processing units. 7.2 7.2.1 Start-up and operating modes See Table 2 for detailed information about the impact of external and internal reset signals as well as control bit settings on the behaviour of internal modules and output pins. START-UP REQUIREMENTS Simultaneously with power-on, the SAA6750H requires a LOW level at pin RESETN. This external reset has to be kept active until the external video clock signal VCLK has been running stable within the specified limits for at least 10 clock cycles (see Chapter “Quick reference data”). A suitable combination of RESETN and clock signal is e.g. provided by Philips product family SAA7111A. For proper reset behaviour and operation pin TRST has to be LOW. 2000 May 03 RESET PROCESSING After release of the external reset or setting back bits E_ST and E_SP to operating mode, the internal synchronous reset remains active for 7562 clock cycles (approximately 260 µs). During this time the DRAM initialization sequence is carried out (see Section 7.10.3.2). All other internal modules except the I2C-bus control register stay in reset mode for this time. The external DRAM will not be refreshed during internal synchronous reset. 14 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) 7.2.3 SAA6750H DESCRIPTION OF OPERATING MODES are forced to a certain behaviour even if no clock VCLK is available. Reset mode overrules all other internal pin settings. During soft reset mode all output and I/O pins that could create driver conflicts with other devices are forced to 3-state or input mode. The internal reset is active during a period of 7562 clock cycles after reset mode and soft reset mode. The status of pins is determined by the reset behaviour of the internal modules. The internal reset behaviour applies also for the init mode because init mode always follows internal reset. Depending on the reset processing and the setting of the I2C-bus control bits E_ST and E_SP (see Tables 22 and 23) the SAA6750H can be set to different operating modes. Purpose and behaviour are described in Table 1. After an external reset pulse at RESETN, the init mode will be active because control bits E_ST and E_SP are set to LOW. 7.2.4 PIN BEHAVIOUR In operation mode the status of the pins is depending on the function of the SAA6750H. The behaviour of I/O and output pins is depending on the operation mode of the SAA6750H. In reset mode the pins Table 1 SAA6750H operating modes ACTIVATED BY MODE DESCRIPTION RESETN E_ST E_SP Reset mode 0 X X In reset mode all I/O and output pins are forced to a defined state with RESETN = LOW (refer to Table 2). After VCLK is available, also the internal reset becomes active, which puts the internal modules in reset state. The I2C-bus control register is cleared in this mode. After setting RESETN back to HIGH, the internal reset will remain active for 7562 clock cycles. The DRAM initialization sequence will run during this time (see Section 7.10.3.2). Init mode 1 0 0 In init mode the device initialization via the I2C-bus has to be performed. The external DRAM is not refreshed. See Table 2 for behaviour of pins during init mode. This mode will be active after external reset due to reset of E_ST and E_SP. Remark: Do not switch from operating mode to init mode directly. Always use the soft reset or reset mode as intermediate step. Soft reset mode 1 0 1 Activates the internal synchronous reset. All internal modules except the I2C-bus control register are in reset mode. This mode allows e.g. operation of a second device SAA6750H. Therefore output and I/O pins are in input or 3-state mode (see Table 2). The external DRAM will not be refreshed. After setting E_SP back to LOW, the internal reset will remain active for 7562 clock cycles. The DRAM initialization sequence will run during this time (see Section 7.10.3.2). Operating mode 1 1 0 Normal operating. − 1 1 1 Internal use only. 2000 May 03 15 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) Table 2 SAA6750H Behaviour of output and I/O pins PIN STATUS PIN NAME DESCRIPTION RESET MODE INIT MODE AND INTERNAL RESET SOFT RESET MODE DATA0 to DATA63 DRAM data input/output input input input ADR0 to ADR8 DRAM address output 3-state output 3-state CASN DRAM column address strobe output 3-state output 3-state RASN DRAM row address strobe output 3-state output 3-state WEN DRAM write enable output 3-state output 3-state OEN DRAM chip select output 3-state output 3-state SDA I2C-bus data input/open-drain output input normal operating normal operating SCL I2C-bus clock input/output input normal operating normal operating MEM_ST reserved output 3-state output 3-state FAD_RDYN ASIP data port; data ready output open-drain; note 1 open-drain open-drain GPIO0 to GPIO11 ASIP data port; input/output input input LRQN output port lower watermark interrupt open-drain request input on open-drain URQN output port upper watermark interrupt open-drain request on open-drain DTACK_RDY output port data transfer acknowledge/ready/request on open-drain AD0 to AD15 output port address/data input/output input input input open-drain Note 1. Only defined if external clock is available. 7.3 7.3.1 7.3.2 Video front-end and formatter GENERAL The 8-bit video input data has to be transferred at a rate of 27 Mwords/s (13.5 MHz for luminance and 6.25 MHz for both chrominance components) i.e. one data word per clock cycle has to be sent. The elements of a data stream have the following order: CB, Y, CR, Y, CB, Y, CR, Y, etc. The byte combinations 00H and FFH are reserved for synchronization purposes, so that only a subset of 254 of all possible 28 = 256 combinations are used. See Section 7.3.3 for detailed information about the synchronization signals. The video front-end and formatter module consists of an 8-bit data input interface, a formatter sub-module and a luminance and a chrominance address processing unit. The interface is designed for use with Philips SAA7111 video decoder family or similar products. The input interface accepts a digital video input stream according to “ITU-T 601”. PAL standard at 50 Hz and 720 pixels by 576 lines as well as NTSC at 60 Hz and 720 pixels by 480 lines are covered. The video synchronization may either follow “ITU-T 656” recommendation or can also be supplied by external signals (HSYNC, VSYNC and FID). The formatter module performs a colour conversion from 4 : 2 : 2 to 4 : 2 : 0 format. Optionally, also an SIF down-scaling may be activated for PAL as well as NTSC standard signals. The luminance and chrominance processing units do generate the addresses for storing the front-end output data in the external DRAM memory. 2000 May 03 DATA INPUT FORMAT The external reference clock VCLK has to be synchronized to the video input data. 16 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) 7.3.3 SAA6750H FUNCTIONAL DESCRIPTION 7.3.3.1 3. The luminance and chrominance submodules generate the addresses in the external DRAM memory where the output data of the video front-end and formatter module is stored. General The video front-end and formatter module consists of four submodules: The video front-end and formatter module offers various operating modes. The appropriate setting can be selected in the I2C-bus control register (see Tables 3 and 22). 1. The 8-bit data interface and the related control signals connect the SAA6750H to external data sources such as e.g. Philips SAA711x product family It should be noted that changes of video standard or synchronization settings are only allowed in init mode or soft reset mode. See Section 7.2.3 for information of the operating modes. 2. The formatter submodule covers two main functions: the processing of the synchronization information (sync processing) and the processing of the picture contents (line based processing) Table 3 Video front-end and formatter mode selection CONTROL BITS(1) MODE FUNCTION STD SS SMOD 0 0 X NTSC NTSC input signal processing (60 Hz and 720 pixels by 480 lines) 1 0 X PAL PAL input signal processing (50 Hz and 720 pixels by 576 lines) 0 1 X NTSC-SIF NTSC input signal processing (60 Hz and 720 pixels by 480 lines); SIF down-scaling active 1 1 X PAL-SIF PAL input signal processing (50 Hz and 720 pixels by 576 lines); SIF down-scaling active X X 0 ITU-T 656 ITU-T 656 mode sync processing mode; sync information is embedded in the video data input stream X X 1 external sync external sync processing mode; sync information is provided via pins FID, HSYNC and VSYNC Note 1. X = don’t care. 2000 May 03 17 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) 7.3.3.2 SAA6750H Interface definition The data input interface uses in total 11 pins. Pins YUV0 to YUV7 carry video and synchronization data and 3 pins are reserved for control purposes (see Table 4). Table 4 List of pins data input port PIN NAME PIN TYPE DESCRIPTION YUV0 to YUV7 input video input signal (synchronous to VCLK) FID input odd/even field identification signal; note 1 HSYNC input horizontal synchronization signal; note 1 VSYNC input vertical synchronization signal; note 1 Note 1. In ITU-T 656 mode sync signals are embedded in the video data input stream. The external sync signals are not used. 7.3.3.3 Line based processing The line based processing works the same way for PAL and NTSC signals. Each of the three components of the video signals Y, U and V are filtered horizontally. The filter is symmetrical and has seven taps. The seven taps are weighted with three programmable parameters a1, a2 and a3 as shown in Table 5. Table 5 Horizontal filtering TAP Horizontal filtering f(a1, a2 and a3) −3 −2 −1 0 +1 +2 +3 a3 a2 a1 1 − 2(a1 + a2 + a3) a1 a2 a3 The three parameters must be loaded by setting the I2C-bus control register words A1, A2 and A3. The valid range is 0 to 255. Reset state is 0. To convert the video signal from 4 : 2 : 2 to 4 : 2 : 0 format, vertical filtering and subsampling of the chrominance components has to be performed. The vertical filter has six taps. The filter coefficients are given in Table 6. Table 6 Vertical filtering TAP 1 2 3 4 5 6 Vertical filtering top fields −3 +13 +30 +24 +4 −4 Vertical filtering bottom fields −4 +4 +24 +30 +13 −3 As mentioned, optionally an SIF mode conversion of PAL or NTSC standard input signals may be activated by setting the I2C-bus control bit SS (see Tables 3 and 22). To convert the video signal to SIF resolution the bottom fields are discarded. Furthermore, all components of the video signal are horizontally subsampled by factor two. 2000 May 03 18 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) 7.3.3.4 SAA6750H Sync processing three external sync lines (H-SYNC, V-SYNC and FID) can also be adapted via the I2C-bus. Control bits HREFP, VREFP and FIDP are used for this purpose (see Table 22). Because the synchronization information may be delivered by a video data source in two different ways, the internal sync processing of the SAA6750H is carried out in two related modes: Internally, the edge-detection circuitries for these signals change polarity with these settings. By this way different synchronization schemes are supported. The horizontal respectively vertical processing starts with the selected edge. 1. The ITU-T 656 mode: The ITU-T 656 recommendation describes the unidirectional interconnection between a video data source and a video data sink. Luminance and chrominance data as well as the complete set of control data (V-sync, H-sync, field indication or byte information such as SAV, EAV, etc.) are transferred interleaved on one 8-bit bus. Both, sync and data signal, are in the form of binary coded 8-bit words. The external sync signals HSYNC, VSYNC and FID are not used. Due to requirements from the internal vertical filtering the line based processing needs 3 horizontal sync pulses during vertical blanking which have to follow directly the active part of the frame (e.g. 288 active lines in PAL mode). The related line data is not processed. This restriction does not allow edge selection at the end of the previous field [e.g. vertical sync of line 623 or line 1 (see Fig.3)]. In this case the polarity bit VREFP has to be set to select the falling edge of the sync lines. 2. The external sync mode: The synchronization may also be provided via pins HSYNC, VSYNC and FID. In this case, the 8-bit bus carries only the video data information. The following sections contain descriptions of different styles of synchronization signals and how they are handled in the SAA6750H. The internal sync processing mode may be selected by the I2C-bus control bit SMOD (see Tables 3 and 22). 7.3.3.5 Sync signals must be active at regular time intervals. If a time interval is too short, a sync is skipped. Top and bottom fields must follow each other. If two top fields or two bottom fields follow each other immediately, than the second field is skipped. The PAL (50 Hz) input signal has 625 lines per frame and typically takes 1728 clock cycles per line. The minimum number of clock cycles per line is 1706. The active part of a field consists of 288 lines of 720 pixels (see Fig.7). Figures 3 and 4 and the related Table 7 give an example illustrating how different sources providing different external sync signals can be adapted to the SAA6750H. In the given example, the SAA711x is connected to pins HSYNC, VSYNC and FID and provides external sync signals in two different modes: according to the timing convention of the ITU-T 656 mode and in a SAA711x proprietary format. In addition another mode HREF/VREF is mentioned in Table 7. From a timing point of view the HREF/VREF mode behaves like ITU-T 656, but horizontal sync and vertical sync signals (VSYNC) are inverted. See data sheet SAA7111A for detailed information. The number of clock cycles and H-sync signals that have to occur before processing starts (horizontal and vertical shift) can be set via the I2C-bus. In this way the active part of the video can be determined. The vertical shift can be specified independently for top and bottom fields by using the control words ‘Vertical shift top field’ and ‘Vertical shift bottom field’ (see Table 22). The horizontal shift is controlled by control word ‘Horizontal shift’. The shift can be programmed in a range of 127 clock cycles in horizontal direction respectively 127 lines in vertical direction. Horizontal shift should be carried out in steps of a multiple of 4 because a minimum data sequence (CB, Y, CR and Y) needs 4 clock cycles. It should be noted that the horizontal blanking in PAL mode takes 280 clock cycles and in NTSC mode 268 cycles. As mentioned, in addition to the external sync mode, the ITU-T 656 mode is supported. Sections 7.3.3.7, 7.3.3.8 and Figs 7 and 8 contain detailed information on this sync mode. Due to the fact that the horizontal offset value can not compensate the whole blanking interval, the polarity of the 2000 May 03 Sync processing PAL (50 Hz) 19 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) SAA6750H handbook, full pagewidth FID (ITU-T 656 timing) VSYNC (ITU-T 656 timing) FID (SAA711x proprietary timing) VSYNC (SAA711x proprietary timing) 621(1) 622 623 624 625 1 2 3 4 5 6 7 8 (308)(2) (309) (310) (311) (312) (1) (2) (3) (4) (5) (6) (7) (8) MHB662 (1) The line numbers not in parenthesis refer to ITU-T counting. (2) The line numbers in parenthesis refer to single field counting. Fig.3 External sync timing of SAA711x; 50 Hz; lines 621 to 8. handbook, full pagewidth FID (ITU-T 656 timing) VSYNC (ITU-T 656 timing) FID (SAA711x proprietary timing) VSYNC (SAA711x proprietary timing) 308(1) 309 310 311 312 313 314 315 316 317 318 319 320 321 (308)(2) (309) (310) (311) (312) (313) (1) (2) (3) (4) (5) (6) (7) (8) MHB663 (1) The line numbers not in parenthesis refer to ITU-T counting. (2) The line numbers in parenthesis refer to single field counting. Fig.4 External sync timing of SAA711x; 50 Hz; lines 308 to 321. 2000 May 03 20 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) Table 7 SAA6750H PAL mode programming example for different sync modes and timing schemes CONTROL BIT AND CONTROL WORD SETTINGS(1) PAL SYNC MODE AND TIMING SMOD FIDP VREFP HREFP VERTICAL SHIFT TOP FIELD VERTICAL SHIFT HORIZONTAL BOTTOM FIELD SHIFT ITU-T 656 mode 0 0 0 0 0 0 0 External sync mode; VREF/HREF mode input signals; ITU-T 656 timing; note 2 1 0 0 0 0 0 0 External sync mode; ITU-T 656 timing; note 3 1 0 1 1 0 0 0 External sync mode; SAA711x proprietary timing; note 3 1 0 1 1 15 16 0 Notes 1. Changes of video standard or synchronization set-up settings are only allowed in init mode or soft reset mode. See Section 7.2.3 for information of the SAA6750H operating modes. 2. See the SAA711x documentation. 3. As illustrated in Figs 3 and 4. 7.3.3.6 Sync processing NTSC (60 Hz ≈ 59.94 Hz) In addition, another mode, HREF/VREF, is mentioned in Table 7. From timing point of view the HREF/VREF mode behaves like ITU-T 656, but signals horizontal sync and vertical sync (VSYNC) are inverted. See data sheet SAA7111A for detailed information. This NTSC (60 Hz) input signal has 525 lines per frame and typically takes 1716 clock cycles per line. The minimum number of clock cycles per line is 1706. The active part of a field consists of 240 lines of 720 pixels (see Fig.9). As mentioned, in addition to the external sync mode, the ITU-T 656 mode is supported. Sections 7.3.3.7, 7.3.3.8 and Figs 9 and 10 contain detailed information on this sync mode. Figures 5 and 6 and the related Table 8 give an example illustrating how different sources providing different external sync signals can be adapted to the SAA6750H. In the given example, the SAA711x is connected to pins HSYNC, VSYNC and FID of the SAA6750H and provides external sync signals in two different modes: according to the timing convention of the ITU-T 656 mode and in an SAA711x proprietary format. 2000 May 03 21 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) SAA6750H handbook, full pagewidth FID (ITU-T 656 timing) VSYNC (ITU-T 656 timing) FID (SAA711x proprietary timing) VSYNC (SAA711x proprietary timing) 523(1) 524 525 1 2 3 4 5 6 7 8 9 10 11 (260)(2) (261) (262) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) MHB664 (1) The line numbers not in parenthesis refer to ITU-T counting. (2) The line numbers in parenthesis refer to single field counting. Fig.5 External sync timing of SAA711x; 60 Hz; lines 523 to 11. handbook, full pagewidth FID (ITU-T 656 timing) VSYNC (ITU-T 656 timing) FID (SAA711x proprietary timing) VSYNC (SAA711x proprietary timing) 261(1) 262 (261)(2) (262) 263 264 265 266 267 268 269 270 271 272 273 274 (263) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) MHB665 (1) The line numbers not in parenthesis refer to ITU-T counting. (2) The line numbers in parenthesis refer to single field counting. Fig.6 External sync timing of SAA711x; 60 Hz; lines 261 to 274. 2000 May 03 22 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) Table 8 SAA6750H NTSC mode programming example for different sync modes and timing schemes CONTROL BIT AND CONTROL WORD SETTINGS(1) NTSC SYNC MODE AND TIMING VERTICAL SHIFT TOP FIELD SMOD FIDP VREFP HREFP VERTICAL SHIFT BOTTOM FIELD HORIZONTAL SHIFT ITU-T 656 mode 0 0 0 0 0 0 0 External sync mode; VREF/HREF mode input signals; ITU-T 656 timing; note 2 1 0 0 0 0 0 0 External sync mode; ITU-T 656 timing; note 3 1 0 1 1 0 0 0 External sync mode; SAA711x proprietary timing; note 3 1 0 1 1 9 10 0 Notes 1. Changes of video standard or synchronization set-up settings are only allowed in init mode or soft reset mode. See Section 7.2.3 for information of the SAA6750H operating modes. 2. See data sheet SAA711x documentation. 3. As illustrated in Figs 5 and 6. 7.3.3.7 Sync processing coding characteristics according to “ITU-T 656” The video data and the control data H_sync, V_sync and field identification are interleaved as follows. handbook, full pagewidth internal H control signal start of digital line start of digital active line EAV code F F 0 0 0 0 4 blanking X Y 8 0 1 0 8 0 1 0 280 SAV code 8 0 1 0 F F 0 0 co-sited 0 0 4 X Y C B Y next line co-sited C R Y C B Y C R Y C R Y 1440 1728 MHB666 Fig.7 Digital horizontal blanking (PAL) in a digital video stream. 2000 May 03 23 F F Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) SAA6750H handbook, full pagewidthline 1 line 1 (V = 1) BLANKING line 23 (V = 0) field 1 (F = 0) odd FIELD 1 ACTIVE VIDEO line 311 (V = 1) line 313 BLANKING line 336 (V = 0) FIELD 2 field 2 (F = 1) even ACTIVE VIDEO line 624 (V = 1) BLANKING line 625 (V = 1) line 625 MHB667 H=1 EAV H=0 SAV Fig.8 Digital vertical timing (PAL). Table 9 Digital vertical timing (PAL) LINE NUMBER F V H (EAV) H (SAV) 1 to 22 0 1 1 0 23 to 310 0 0 1 0 311 and 312 0 1 1 0 313 to 335 1 1 1 0 336 to 623 1 0 1 0 624 and 625 1 1 1 0 2000 May 03 24 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) SAA6750H internal H control signal handbook, full pagewidth start of digital line start of digital active line EAV code F F 0 0 0 0 blanking X Y 8 0 1 0 4 8 0 1 0 SAV code 8 0 268 1 0 F F 0 0 co-sited 0 0 X Y C B Y next line co-sited C R 4 Y C B Y C R Y C R Y 1440 1716 MHB668 Fig.9 Digital horizontal blanking (NTSC) in a digital video stream. line 1 (V = 1) handbook, full pagewidthline 4 BLANKING line 10 (V = X) OPTIONAL BLANKING line 20 (V = 0) field 1 (F = 0) odd FIELD 1 ACTIVE VIDEO line 264 (V = 1) line 266 BLANKING line 273 (V = 1) OPTIONAL BLANKING line 283 (V = 0) field 2 (F = 1) even FIELD 2 ACTIVE VIDEO line 525 (V = 0) MHB669 line 3 H=1 EAV H=0 SAV Fig.10 Digital vertical timing (NTSC). 2000 May 03 25 F F Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) SAA6750H Table 10 Digital vertical timing (NTSC) LINE NUMBER F V H (EAV) H (SAV) 1 to 3 1 1 1 0 4 to 19 0 1 1 0 20 to 263 0 0 1 0 264 and 265 0 1 1 0 266 to 282 1 1 1 0 283 to 525 1 0 1 0 7.3.3.8 Video timing reference codes (ITU-T 656) 7.4.2 7.4.2.1 There are two timing reference signals, one at the beginning of each video data block (start of active video, SAV) and one at the end of each video data block (end of active video, EAV). 7.4.2.2 V(2) H(3) P3(4) P2(4) P1(4) P0(4) The motion estimation is based on the recursive block matching algorithm. Per macroblock the ASIP must feed the motion estimator with five candidate vectors. Depending on a control word, the last two vectors can be relative to the computed vector of the previous macroblock or can be absolute. The vectors are compared by the Minimum Absolute Difference (MAD) of the estimated macroblock in the previous frame and the current macroblock. The vector that leads to the smallest MAD is selected. The fifth vector gets a penalty and can be used as random vector candidate. The two coordinates of the selected vector and the corresponding MAD value are returned to the ASIP. Notes 1. F = 0 during field 1; F = 1 during field 2. 2. V = 1 during field blanking; V = 0 elsewhere. 3. H = 0 in SAV; H = 1 in EAV. 4. Protection bits are ignored by SAA6750H data processing. 7.4 7.4.1 Macroblock processor GENERAL The MacroBlock Processor (MBP) performs the compression of macroblocks. It fetches its input data from the external DRAM memory where this was stored by the video front-end and formatter. The data processing is macroblock related. The processing start information and the global scheduling is provided by the global controller module. 7.4.2.3 Noise filtering The availability of the motion estimator makes motion compensated adaptive temporal filtering possible. The functioning of this filter can be programmed by two parameters. These parameters are provided by the ASIP. The functionality of the MBP is controlled by the Application Specific Instruction-set Processor (ASIP). The ASIP does also perform some computing of data needed by the MBP. The compressed data is fed to the packer module. 2000 May 03 Motion estimation The motion estimator considers frame based motion. Furthermore, the frame distance is one frame and, consequently, can only be used for P frames. Table 11 Video timing reference codes F(1) General The MBP performs source coding on macroblock level. It contains several items: motion estimation; motion compensation, noise reduction and frame field conversion; Discrete and Inverse Discrete Cosine Transformations (DCT and IDCT), quantization and inverse quantization; motion decompensation and frame-field conversion; zigzag scanning; DC trend removal (residue); Run-Length Encoding (RLE) and Variable-Length Encoding (VLE). Each timing reference signal consists of a four word sequence in the following format: FF 00 00 XY (values are expressed in hexadecimal notation). The first three words are a fixed preamble. The forth word XY contains information defining field 2 identification, the state of field blanking, and the state of line blanking. The assignment of bits within the timing reference signal is shown in Table 11. 1 FUNCTIONAL DESCRIPTION The noise reduction may only be activated if control bit INTRA is set to logic 0 (see Table 22). 26 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) 7.4.2.4 SAA6750H Intra/inter coded macroblock selection in P frames 7.4.2.9 Addressing The MBP only relies on the format used to store macroblocks in the external DRAM. It works independently from the memory map where to find which macroblock. The ASIP has to keep track of the macroblocks base addresses and has to inform the MBP where to find the data. The MBP only increments the addresses to fetch next data or to write results back. The selection of intra or inter coded macroblock compression mode depends on a control byte from the ASIP or on the MAD value. A macroblock is coded intra, if the ASIP demands so or when the MAD resulting from the motion estimation is above a threshold value. This threshold value is provided by the ASIP. The resulting encoding mode is returned to the ASIP. 7.4.2.10 7.4.2.5 Field/frame DCT coded macroblock selection for luminance blocks The communication with the ASIP is the same for every macroblock. That means that although many settings remain unchanged they have to be repeatedly sent from the ASIP to the MBP. The communication is handled by FIFOs. Depending on motion between the two fields comprising a frame, the four 8 × 8 pixel DCT luminance blocks of a macroblock are differently derived from the 16 × 16 pixels. The luminance pixels of a macroblock are vertically Walsh-Hadamard transformed in order to detect the field motion. If the first coefficient is higher than a threshold value, then the DCT is performed field-wise. The ASIP can force frame DCT coding. The result, i.e. frame or field DCT coding, is returned to the ASIP. The output of the DCT are four luminance and two chrominance blocks consisting of 8 × 8 pixels each. 7.4.2.6 7.5 7.5.1 • Packing unit (packer and pre-packer) • Stuffing unit (Buffer_out_address and Buffer_out_data) • Various FIFOs connecting all parts together. The packing unit does the bit-wise processing of the ASIP and MBP generated streams while the stuffing unit is byte oriented. Handshaking of all blocks is done via FIFOs. 7.5.2 Trend removal PRE-PACKER AND PACKER The packing unit (consisting of packer and pre-packer) is responsible to compose a fluent bitstream. Each clock cycle the packer gets a certain amount of valid bits (0 to 24) as input data either from the ASIP (e.g. header information) or from the MBP (compressed macroblock coefficients via pre-packer) and generates 64-bit words with valid bits only. These words are stored into the 4 Mbit output buffer located in the external DRAM. DC coefficients are coded differentially. However, at the start of every slice and for every intra coded macroblock, the absolute values are coded. Therefore, the ASIP sends a control word to the MBP indicating the start of a slice. Run-length coding and variable-length coding The MBP compresses the quantized DCT coefficients by (zero) Run-Length Coding (RLC) and Variable-Length Coding (VLC). To inform the ASIP about the achieved compression, it sends the number of bits used in the bitstream to the ASIP. The maximum number of bits used for each of the six blocks (see Section 7.4.2.5) must be set by the ASIP. Furthermore, the coded block pattern is sent to the ASIP. 2000 May 03 GENERAL Parts involved are: Quantization The quantization may be customized by using a dedicated quantization table which can be loaded via the I2C-bus (see Section 7.9.4). The quantization table data is part of the software packages and will be described in the software specification. 7.4.2.8 Bitstream assembly While MBP only processes the incoming video data and the ASIP generates the corresponding MPEG2 compliant header and stuffing information, these information must be gathered to form a complete output stream. The quantization performs the redundancy removal, depending on settings provided by the ASIP. 7.4.2.7 Communication with the ASIP To reduce the memory needs of the compressed macroblock data, a pre-packing to get words of 24 valid bits is performed before storing data for packing. 27 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) 7.6 SAA6750H 1. Internal address decoding Data output port 7.6.1 The data output port provides a programmable internal address decoding. This does support e.g. the use of several slaves on the bus. The data output port’s 16-bit address is determined by the setting of bytes Bus address (MSB) and Bus address (LSB) in the I2C-bus control register (see Table 21). During reset mode the contents of Bus address will be set to 0000H. GENERAL The data output port connects the data output stream of the SAA6750H to the outside world. The data output port interface implements a Motorola-style bus protocol with different addressing modes. The status of the internal data buffer is reported by dedicated output signals. The data output interface of the SAA6750H will always behave as a slave on the bus. 7.6.2 The external host may select the data output port by sending the address value that was programmed in the I2C-bus control register. In internal address decoding mode, the output data bus carries multiplexed address and data information. DATA OUTPUT FORMAT The output data is provided in 16-bit words. The most significant bit of the data word represents the first bit in the serial MPEG2 elementary stream. Depending on the addressing mode the external host uses the bus transfers plain data (non-multiplex mode) or a multiplex of addresses and data (multiplex mode) for selection of the data output port, See Section 7.6.3 for information about the interface protocol. 7.6.3 Pin CSN is not used in this mode and must be set to HIGH. 2. External address decoding External address decoding mode may be appropriate if e.g. an external address decoding hardware is available or if the SAA6750H is the only slave on the bus. The data output port is selected by setting pin CSN to LOW. In this mode, the internal address decoder is disabled and consequently the setting of bytes Bus address is ignored. In external address decoding mode, the output data bus carries plain data information. FUNCTIONAL DESCRIPTION 7.6.3.1 General The data output port supports Motorola-style bus protocol. The addressing can be carried out by the external host in two different modes: The bus protocol mode and address decoding mode are depending on the setting of the I2C-bus control register bit BUS. See Tables 12 and 22 and Section 7.6.3.4 for detailed information. Table 12 Data output port mode selection BIT BUS PIN I_MN FUNCTION 0 LOW Motorola-style protocol mode with external address decoding (non-multiplexed bus); note 1 1 LOW Motorola-style protocol mode with internal 16-bit address decoding (multiplexed bus); notes 1 and 2 X(3) HIGH reserved Notes 1. Bit BUS is set to logic 0 during reset mode. 2. The 16-bit data output port address (see Table 21) must be loaded via the I2C-bus with the application specific value. The default address is set to 0000H during reset mode. 3. X = don’t care. 2000 May 03 28 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) 7.6.3.2 SAA6750H Interface definition The data output interface uses in total 23 pins. Pins AD0 to AD15 carry data and address information. 7 pins are reserved for control purposes. Partly, the functionality of these pins changes with the selected address or protocol mode (see Tables 13 and 14). Table 13 List of pins data output port PIN NAME PIN TYPE DESCRIPTION AD0 to AD15 input/output internal address decoding: multiplexed address/data bus; external address decoding: non-multiplexed data bus AS_ALE input protocol mode depending functionality; see Table 14 CSN input internal address decoding: not used; connect to HIGH; external address decoding: data output port select input DS_RDN input protocol mode depending functionality; see Table 14 DTACK_RDY output protocol mode depending functionality; see Table 14 I_MN input select protocol mode: LOW is Motorola-style protocol mode (must be set to logic 0); HIGH is reserved mode LRQN output LOW indicates that the fullness of the output buffer is below the programmable lower watermark value; see Table 22 URQN output LOW indicates that the fullness of the output buffer is higher than the programmable higher watermark value; see Table 22 Table 14 Protocol mode depending pins PIN NAME MOTOROLA-STYLE PROTOCOL MODE RESERVED MODE AS_ALE AS address strobe ALE reserved DS_RDN DS data strobe RDN reserved DTACK_RDY DTACK data transfer acknowledge RDY reserved 7.6.3.3 Status reporting data output buffer The upper watermark reporting may be used by the host to prevent data overflow of the output buffer of the SAA6750H. The fullness of the data output buffer located in the external DRAM is monitored. If the current value is two times or more than two times the value programmed in bytes ‘BS_BUFFER upper level’ in the I2C-bus control register, the signal URQN goes to LOW. The host may use this information to start requesting data. If it does not, an internal buffer overflow may result in loss of data. Value ‘BS_BUFFER upper level’ has a valid range of 1 to 32752. The threshold can be selected in 128-bit steps. The maximum watermark value equals 4 Mbit. The data output port of the SAA6750H provides information about the status of the internal 4 Mbit output buffer. Two signals that are available via pins LRQN and URQN are related to internal buffer watermarks. The external host may use this information to control the data stream in a way that highest rates are possible without out-of-data or buffer-overflow situations. The watermark levels are programmable via the I2C-bus (see Table 22). The lower watermark reporting may be used by the host to prevent out-of-data situations. The fullness of the data output buffer is monitored. If the current value is below the threshold programmed in control word ‘BS_BUFFER lower level’ in the I2C-bus control register, the signal LRQN goes to LOW. The host may use this information to stop requesting data. Value ‘BS_BUFFER lower level’ has a range of 0 to 63. If the value is set to 0, LRQN will not be activated. The threshold can be selected in 64-bit steps. 2000 May 03 During reset mode, ‘BS_BUFFER lower level’ and ‘BS_BUFFER upper level’ are set to logic 0. The I2C-bus control register values BS_BUFFER should be initialized with the desired values before starting operating mode. If ‘BS_ BUFFER lower level’ has a value greater than 0, LRQN will be LOW as long as no valid data is available. 29 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) 7.6.3.4 SAA6750H Motorola-style protocol mode 7.7 1. Internal address decoding 7.7.1 The host starts a data transfer cycle by applying the data output port address onto the multiplexed address/data lines (see Fig.16). By setting AS_ALE to LOW the host indicates that the address is valid and by setting DS_RDN to LOW that it gives up driving the address data and allows the data output interface of the SAA6750H to send data via the bus. The SAA6750H will drive DTACK_RDY to LOW, when it has placed valid data onto AD15 to AD0. A DS_RDN = HIGH by the host will force the SAA6750H to set DTACK_RDY back to HIGH, to stop driving the data bus and to interrupt the transfer of the current word, however, this may lead to a loss of data. The data read sequence may be repeated by setting DS_RDN to LOW and so forth. GENERAL The ASIP is a programmable controller specially designed for the architecture and system requirements of the SAA6750H. Generally it has to cover internal control functions. The following tasks are handled: • Controlling of the MBP • Macroblock base address generation for the MBP • Motion vector generation • Bitstream header generation • Management of bitstream assembly • Bit-rate control. The microcode of the ASIP has to be downloaded by the I2C-bus into internal RAMs during initialization of the SAA6750H. The transfer cycle is ended as soon as the host sets DS_RDN and AS_ALE back to HIGH. After this, the SAA6750H will also set DTACK_RDY to HIGH and stops driving data after a delay tdz (see Chapter “Characteristics”). A new transfer cycle may not be started as long as DTACK_RDY is LOW or the SAA6750H is driving the data bus. CSN has to be HIGH all the time. See Fig.16 and Chapter “Characteristics” for timing information. The ASIP is able to communicate with the outside world via an I2C-bus interface (see Section 7.9.4). 7.8 7.8.1 Global controller GENERAL The global controller generates a global scheduling for the loosely coupled processes of the SAA6750H. It is controlled by the bits E_ST, E_SP, SS and STD which are located in the I2C-bus control register (see Table 22). The global controller is automatically synchronized with the front-end block. 2. External address decoding The host starts a data transfer cycle by setting the CSN signal to LOW (see Fig.17). By setting DS_RDN to LOW the host indicates that it wants to read a data word and allows the data output interface of the SAA6750H to send data via the bus. The SAA6750H will drive DTACK_RDY to LOW, when it has placed valid data onto AD15 to AD0. A DS_RDN = HIGH by the host will force the SAA6750H to set DTACK_RDY back to HIGH, to stop driving the data bus and to interrupt the transfer of the current word however this may lead to a loss of data. The data read sequence may be repeated by setting DS_RDN to LOW and so forth. 7.9 7.9.1 I2C-bus interface and controller GENERAL The I2C-bus interface within the SAA6750H is a slave transceiver. It is used to download the microcode of the ASIP, constants and tables as well as the quantization matrix table to the MBP. In addition, all control settings are carried out via the I2C-bus. The read mode may be used to read back data from registers connected internally to the ASIP. In total 8 subaddresses are used to store or read data. The transfer cycle is ended as soon as the host sets DS_RDN and CSN back to HIGH. After this, the SAA6750H will also set DTACK_RDY to HIGH and stop driving data after a delay tdz (see Chapter “Characteristics”). A new transfer cycle may not be started as long as DTACK_RDY is LOW or the SAA6750H is driving the data bus. AS_ALE has to be HIGH all the time. See Fig.17 and Chapter “Characteristics” for timing information. 2000 May 03 Application Specific Instruction-set Processor (ASIP) The I2C-bus interface is compliant to the I2C-bus standard at 100 and 400 kHz clock frequency and suitable for bus-line voltage levels from 3.3 to 5 V. The I2C-bus slave address (SAD) is 40H respectively 42H depending on the state of pin MAD. This allows the use of two devices SAA6750H in one application. See the general I2C-bus specification for detailed information on the bus protocol. 30 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) 7.9.2 SAA6750H If the memory’s address or data word does not have a width of a multiple of 8 bits, dummy bits have to be added on the left side (most significant bit side) of the MSB. E.g. the ASIP microcode has 177 bits wide data words. 177 divided by 8 gives 22 and a remainder of 1. Therefore the I2C-bus master has to send 23 data bytes of which the higher 7 bits of the MSB are dummy bits. Also the same rule applies for read operations. SPECIAL CONSIDERATIONS Eight subaddresses are used to read or write data from or to the internal SRAM memories and registers of the SAA6750H. An explanation of purpose, function and data transfer will be given in the following chapters. It should be noted that all subaddresses can only be used as data sink or as data source. It is not possible to write data into a register and read it back later on. Depending on the type of storage the data transfer to or from the memories and registers has to be carried out in different modes which will be described in the following chapters. Due to the internal memory architecture data may only be transmitted to the subaddresses 00H to 03H when the SAA6750H is in init mode. After the control bit E_ST is set to logic 1, sending data via the I2C-bus to the SRAMs 00H to 03H is forbidden. Table 15 Abbreviations used in data transfer diagrams The I2C-bus interface will not respond to the general call address 00H and it will not use clock stretch to slow down a data transmission. ABBREVIATION The acknowledgement of a data byte by the I2C-bus interface only indicates that the transmission was received and that the correct slave address was used. It does not necessarily say that the data reached its destination. E.g. also if a subaddress outside the valid range from 00H to 007H was sent to the SAA6750H or a transmission to subaddress 01H took place while bit E_ST was logic 1, the I2C-bus interface will return an acknowledge. A special sequence of commands is used to read data from the subaddress 04H. See Section 7.9.3.4 for detailed information. 7.9.3 7.9.3.1 I2C-BUS DATA TRANSFER MODES S RS I2C-bus REPEATED START condition, generated by master SAD Higher 7 bits of slave address byte: 7-bit slave address: 0100000 (pin MAD = LOW), 40H/41H; 7-bit slave address: 0100001 (pin MAD = HIGH), 42H/43H W write mode: LSB of slave address byte = 0 R read mode: LSB of slave address byte = 1 MA master acknowledge (acknowledge generated by master) MN master acknowledge not (no acknowledge by master) SA slave acknowledge (acknowledge generated by SAA6750H) SD 8-bit subaddress ADR address byte DATA data byte to be written/read P I2C-bus STOP condition, generated by master General Data transfer follows the I2C-bus specification for fast (400 kHz) or normal (100 kHz) mode. The SAA6750H slave address in write mode is: • 40H if pin MAD is LOW • 42H if pin MAD is HIGH. For read operations the following slave addresses have to be used: • 41H if pin MAD is LOW • 43H if pin MAD is HIGH. The I2C-bus will transfer data always as a whole byte consisting of 8 bits. If the address or data word consists of several bytes, the Most Significant Byte (MSB) has to be sent first and the Least Significant Byte (LSB) last. This rule does also apply for read operations. In this case the MSB will be received first. 2000 May 03 31 FUNCTION I2C-bus START condition, generated by master Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) 7.9.3.2 SAA6750H Random access memory write mode This mode provides random access to specific memory addresses. The data has to be written according to following scheme: Table 16 Data transfer using random access write mode S SAD W SA SD SA ADR1 (MSB) SA ADR2 (LSB) SA DATA1 (MSB) SA ... DATAn − 1 SA DATAn (LSB) SA P In this example the address word consists of 2 bytes and the data word out of n bytes. This sequence has to be repeated for every data word that has to be sent to the memory. 7.9.3.3 Write mode The write mode is used if a number of data bytes has to be written to a subaddress if there is no specific memory address. I.e. this mode is used to write data to registers. The data has to be sent according to following scheme: Table 17 Data transfer using write mode S SAD W SA SD SA DATA1 (MSB) SA DATA2 SA DATA3 SA ... (MSB − 1) (MSB − 2) DATAn − 1 SA DATAn (LSB) SA P In this example the data word consists of n bytes. 7.9.3.4 Read mode This mode is used to read data bytes from memories or registers. It is not possible to access a specific memory address. The first byte to be received will be the MSB. If a certain information is needed, the read transfer has to be carried out until the specific byte is available. The data transfer has to be closed by the I2C-bus master by sending an MN (not acknowledge) after the last data byte. This tells the SAA6750H to stop sending further data. The transfer has to follow this scheme: Table 18 Data transfer using read mode S SAD W SA SD SA RS SAD R DATA1 (MSB) MA DATA2 MA ... (MSB − 1) In this example the read operation gets n data bytes out of the SAA6750H. 2000 May 03 32 DATAn − 1 MA DATAn (LSB) MN P Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) 7.9.4 SAA6750H I2C-BUS MEMORIES AND REGISTERS Eight different SRAM memories and registers may be written or read via the I2C-bus. Each has a specific subaddress. This chapter will explain the purpose of these storages and how they have to be used. 7.9.4.1 Allocation of subaddresses Following table shows which memories or registers are allocated to the subaddresses 00H to 07H: Table 19 Subaddresses and related memories SUBADDRESS STORAGE (HEX) NAME DESIGN BLOCK DEPTH (WORDS) WIDTH(BITS) DESCRIPTION 00 quantizatio n matrix SRAM MBP 128 8 SRAM memory containing a constant table for the macroblock processor quantization function 01 microcode SRAM ASIP 1024 177 SRAM memory containing the microcode of the ASIP 02 microcode ROM table ASIP 512 24 SRAM memory containing the microcode ROM table of the ASIP 03 microcode constants ASIP 256 24 SRAM memory containing the microcode constants of the ASIP 04 serial output register ASIP 7 24 register bank that can be written by the ASIP; contents depending on the ASIP software 05 serial input register ASIP 14 24 register bank that can be read by the ASIP; used to control the ASIP externally; the function of the register settings is depending on the ASIP software 06 control register I2C-bus 1 160 register containing the hardware control bits of the SAA6750H 07 internal use none − − 2000 May 03 33 − Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) SAA6750H I2C-bus data transfer to subaddresses 7.9.4.2 The following tables describe the data transfer to or from the subaddresses 0 to 7. See Sections 7.9.3.2, 7.9.3.3 and 7.9.3.4 for information of the data transfer modes. Table 20 Data transfer to subaddresses I2C-BUS BYTE TRANSFERS PER TRANSMISSION SUBADDRESS (HEX) STORAGE NAME DATA TRANSFER MODE 00 quantization matrix SRAM random access write mode 1 1 4=2+1+1 01 microcode SRAM random access write mode 2 23 27 = 2 + 2 + 23 02 microcode ROM table random access write mode 2 3 7=2+2+3 03 microcode constants random access write mode 1 3 6=2+1+3 04 serial output register read mode 0 21 24 = 2 + 1 + 21 05 serial input register random access write mode 1 24 6=2+1+3 06 control bits register write mode 0 20 22 = 2 + 20 07 internal use none − − − 7.9.4.3 ADDRESS DATA BYTES BYTES PER PER TRANSMISSION TRANSMISSION Quantization matrix SRAM SUBADDRESS (HEX) 00 STORAGE NAME quantization matrix SRAM DESIGN BLOCK MBP DEPTH WIDTH (WORDS) (BITS) 128 8 DATA TRANSFER MODE random access write mode SRAM memory containing a constant table for the macroblock processor quantization function. The data to be loaded into this memory will be part of the application software and described in the software specification. Remark: Data may only be sent to this subaddress if the SAA6750H is in the init mode (see Table 23). 7.9.4.4 Microcode SRAM SUBADDRESS (HEX) 01 STORAGE NAME microcode SRAM DESIGN BLOCK ASIP DEPTH WIDTH (WORDS) (BITS) 1024 177 DATA TRANSFER MODE random access write mode SRAM memory containing the ASIP’s microcode. The microcode to be loaded into this memory will be part of the application software and described in the software specification. Remark: Data may only be sent to this subaddress if the SAA6750H is in the init mode (see Table 23). 2000 May 03 34 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) 7.9.4.5 SAA6750H Microcode ROM table SRAM SUBADDRESS (HEX) 02 STORAGE NAME microcode ROM table SRAM DESIGN BLOCK DEPTH WIDTH (WORDS) (BITS) ASIP 512 24 DATA TRANSFER MODE random access write mode SRAM memory containing special tables that are needed by the ASIP software. The quantization matrix data loaded into subaddress 0 is also part of this set of data. The data to be loaded into this memory will be included in the application software and described in the software specification. Remark: Data may only be sent to this subaddress if the SAA6750H is in the init mode (see Table 23). 7.9.4.6 Microcode constant SRAM SUBADDRESS (HEX) 03 STORAGE NAME microcode constants SRAM DESIGN BLOCK DEPTH WIDTH (WORDS) (BITS) ASIP 256 24 DATA TRANSFER MODE random access write mode SRAM memory containing constants that are needed by the ASIP software. The data to be loaded into this memory will be included in the application software and described in the software specification. Remark: Data may only be sent to this subaddress if the SAA6750H is in the init mode (see Table 23). 7.9.4.7 Serial output register SUBADDRESS (HEX) 04 STORAGE NAME serial output register DESIGN BLOCK DEPTH WIDTH (WORDS) (BITS) ASIP 7 24 DATA TRANSFER MODE read mode Register bank that can be written by the ASIP and read by the I2C-bus. The ASIP is able to access a specific register by writing the address and the related data word. On the contrary it is not possible to access a specific register by the I2C-bus. Starting an I2C-bus read operation will return the data of register 0 first, starting with the most significant byte. After the LSB of register 0 was received, the register address will be incremented automatically and the MSB of register 1 will be received next. Consequently, 21 data words have to be read if the data of register 6 is needed. The register data depends on the ASIP’s software and the state of the SAA6750H. A description will be part of the software specification. 2000 May 03 35 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) 7.9.4.8 SAA6750H Serial input register SUBADDRESS (HEX) 05 STORAGE NAME serial input register DESIGN BLOCK ASIP DEPTH WIDTH (WORDS) (BITS) 14 24 DATA TRANSFER MODE random access write mode Register bank that can be read by the ASIP. Used to control the ASIP externally. The function of register settings is depending on the ASIP software. A description will be part of the software specification. The valid address range reaches from 01H to 0EH. Any data sent by the I2C-bus to address 00H will always be overwritten by an internal signal. 7.9.4.9 Control register SUBADDRESS (HEX) 06 STORAGE NAME control register DESIGN BLOCK I 2C DEPTH WIDTH (WORDS) (BITS) 1 160 DATA TRANSFER MODE write mode Register bank used to control internal signals. The allocation of control bits in the register is shown in Table 21. The function of the specific bits is described in Table 22. During external reset, all register bits will be set to logic 0. During initialization all 20 bytes starting with the MSB and ending with the LSB (control) have to be sent by the I2C-bus in one go. 2000 May 03 36 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) SAA6750H Table 21 Description of the I2C-bus control register; note 1 REGISTER BYTE BIT ADDRESS (HEX) MSB D7 LSB D6 D5 D4 D3 D2 D1 D0 Control 00 to 07 STD SS INTRA BUS E_ST E_SP SMOD BYP FIFO PMI(S) time slot setting 08 to 0F PMI7 PMI6 PMI5 PMI4 PMI3 PMI2 PMI1 PMI0 FIFO WR_AD(MC) time slot setting 10 to 17 WR7 WR6 WR5 WR4 WR3 WR2 WR1 WR0 FIFO RD_ADR(MA) time slot setting 18 to 1F RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 FIFO BUF_ADR(H) time slot setting 20 to 27 BUF7 BUF6 BUF5 BUF4 BUF3 BUF2 BUF1 BUF0 FIFO REFR(G) time slot setting 28 to 2F RFR7 RFR6 RFR5 RFR4 RFR3 RFR2 RFR1 RFR0 FIFO MC(E) time slot setting 30 to 37 MC7 MC6 MC5 MC4 MC3 MC2 MC1 MC0 FIFO ML(B) time slot setting 38 to 3F ML7 ML6 ML5 ML4 ML3 ML2 ML1 ML0 FIDP and vertical shift bottom field 40 to 47 FIDP VSB6 VSB5 VSB4 VSB3 VSB2 VSB1 VSB0 VREFP and vertical shift top field 48 to 4F VREFP VST6 VST5 VST4 VST3 VST2 VST1 VST0 HREFP and horizontal shift 50 to 57 HREFP HOR6 HOR5 HOR4 HOR3 HOR2 HOR1 HOR0 Filter coefficient a3 58 to 5F FA37 FA36 FA35 FA34 FA33 FA32 FA31 FA30 Filter coefficient a2 60 to 67 FA27 FA26 FA25 FA24 FA23 FA22 FA21 FA20 Filter coefficient a1 68 to 6F FA17 FA16 FA15 FA14 FA13 FA12 FA11 FA10 Shift start 70 to 77 SH7 SH6 SH5 SH4 SH3 SH2 SH1 SH0 BS_BUFFER lower level 78 to 7F X X BL5 BL4 BL3 BL2 BL1 BL0 BS_BUFFER upper level (LSB) 80 to 87 BU7 BU6 BU5 BU4 BU3 BU2 BU1 BU0 BS_BUFFER upper level (MSB) 88 to 8F X BU14 BU13 BU12 BU11 BU10 BU9 BU8 Bus address (LSB) 90 to 97 DADR7 DADR6 DADR5 DADR4 DADR3 DADR2 Bus address (MSB) 98 to 9F DADR15 DADR14 DADR13 DADR12 DADR11 DADR10 DADR9 DADR8 Note 1. X = don’t care; should be set to logic 0 during initialization. 2000 May 03 37 DADR1 DADR0 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) SAA6750H Table 22 Description of the I2C-bus control bits and words BIT ADDRESS (HEX) BIT NAME CONTROL WORD NAME DATA BYTE 00 BYP 01 SMOD(1) external/internal sync signal selection; LOW: sync is derived from the SAV and EAV information decoded from the data stream at port YUV; HIGH: sync is derived from the external sync signals at pins FID, HSYNC and VSYNC 02 E_SP engine stop; see Table 23 03 E_ST engine start; see Table 23 04 BUS data output port address mode selection; LOW: external address decoding (CSN pin); HIGH: internal address decoding (AD pin) 05 INTRA maximum output bit-rate selection; use default setting given in the software specification 06 SS(1) non SIF mode/SIF mode selection; LOW: subsampling off; HIGH: subsampling on (SIF mode convertion active) 07 STD(1) NTSC/PAL selection; LOW: NTSC mode input signal expected; HIGH: PAL mode input signal expected 08 to 0F PMI0 to PMI7 18 use default setting given in the software specification 10 to 17 WR0 to WR7 17 use default setting given in the software specification 18 to 1F RD0 to RD7 16 use default setting given in the software specification 20 to 27 BUF0 to BUF7 15 use default setting given in the software specification 28 to 2F RFR0 to RFR7 14 use default setting given in the software specification 30 to 37 MC0 to MC7 13 use default setting given in the software specification 38 to 3F ML0 to ML7 12 use default setting given in the software specification 40 to 46 VSB0 to VSB6 11 value determines number of H-syncs occurring after V-sync before the bottom field line based processing starts; note 2 47 FIDP(1) 2000 May 03 19 DESCRIPTION vertical shift bottom field internal use; it must be set to LOW during initialization FID signal polarity selection; LOW: FID signal not inverted (FID = LOW indicates odd field); HIGH: FID signal inverted (FID = HIGH indicates odd field); this setting takes affect for external as well as for SAV and EAV sync 38 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) BIT ADDRESS (HEX) 48 to 4E BIT NAME VST0 to VST6(1) CONTROL WORD NAME DATA BYTE vertical shift top field 10 SAA6750H DESCRIPTION value determines number of H-syncs occurring after V-sync before the top field line based processing starts; note 2 4F VREFP(1) 55 to 56 HOR0 to HOR6(1) 57 HREFP(1) 58 to 5F FA30 to FA37 Filter coefficient a3 8 filter coefficient a3 for the horizontal filtering of video input signal 60 to 67 FA20 to FA27 Filter coefficient a2 7 filter coefficient a2 for the horizontal filtering of video input signal 68 to 6F FA10 to FA17 Filter coefficient a1 6 filter coefficient a1 for the horizontal filtering of video input signal 70 to 77 SH0 to SH7 Shift start (time slot) 5 use default setting given in the software specification 78 to 7D BL0 to BL5 BS_BUFFER lower level 4 lower watermark value for data output buffer monitoring in 64-bit steps 7E to 7F − 80 to 87 BU0 to BU7 BS_BUFFER upper level (LSB) 3 upper watermark value for data output buffer monitoring (LSB); the valid range for BS_BUFFER upper level is 1 to 32752 in 128-bit steps 88 to 8E BU8 to BU14 BS_BUFFER upper level (MSB) 2 upper watermark value for data output buffer monitoring (MSB); the valid range for BS_BUFFER upper level is 1 to 32752 in 128-bit steps 8F − 90 to 97 DADR0 to DADR7 Bus address (LSB) 1 address value for internal address decoding mode of data output port (LSB) 98 to 9F DADR8 Bus address (MSB) to DADR15 0 address value for internal address decoding mode of data output port (MSB) VSYNC signal polarity selection; LOW: VSYNC signal not inverted, VREF signal expected at pin VSYNC; HIGH: VSYNC signal inverted, vertical blanking qualifier expected at VSYNC pin; this setting does not affect the sync derived from SAV and EAV codes horizontal shift 9 setting determines the number of clock cycles occurring after the H-sync before the line based processing starts; value should have a multiple of 4 because a minimum data sequence (CB, Y, CR and Y) needs 4 clock cycles HSYNC signal polarity selection; LOW: HSYNC signal not inverted, HREF signal expected at pin HSYNC; HIGH: HSYNC signal inverted, horizontal blanking qualifier expected at pin HSYNC; this setting does not affect the sync derived from SAV and EAV codes not used; it must be set to LOW during initialization not used; it must be set to LOW during initialization Notes 1. Changes of this setting are only allowed in init mode or soft reset mode. See Section 7.2.3 for information of the SAA6750H operating modes. 2. The range of sensible values is 00H to 10H for PAL and 00H to 07H for NTSC. 2000 May 03 39 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) SAA6750H There has to be a 0.5 ms delay between the end of the external reset RESETN and the start of the I2C-bus initialization. Table 23 Description of engine bits E_ST E_SP SELECTED OPERATING MODE 0 0 init mode 0 1 soft reset mode The registers and memories of the SAA6750H should be initialized in following order: 1 0 operating mode 1. Subaddress 00H: MBP quantization matrix 1 1 internal use only 2. Subaddress 01H: ASIP microcode 3. Subaddress 02H: ASIP microcode ROM table The engine control bits are used to set the SAA6750H in a specific operating mode. After reset mode the init mode will be activated automatically. For information about the operating modes of the SAA6750H refer to Table 1. 7.9.5 4. Subaddress 03H: ASIP microcode constant 5. Subaddress 05H: ASIP serial input 6. Subaddress 06H: Control register (see Table 24). The following example shows a control register setting for PAL input signal, SAV/EAV sync and external output port address decoding for inter and intra mode. It should be noted that the settings for the INTRA bit and the FIFO time slot values are depending on a specific ASIP software version. Use in any case those settings given in the ASIP software specification. I2C-BUS INITIALIZATION After power-on and the related RESETN pulse the SAA6750H has to be initialized via the I2C-bus. The internal RAMs must be loaded and the control bits must be set. The internal memories reachable via subaddresses 00H, 01H, 02H and 03H should be loaded first. Use the data files that belong to a specific ASIP software version. The control register should be written at last. Activate bit E_ST only if all other settings have the desired state. 2000 May 03 40 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) SAA6750H Table 24 Example for control register settings INTER/INTRA MODE REGISTER BYTE INTRA FORCE MODE DATA BYTE BINARY HEX BINARY HEX Control 19 1000 1000 88 1010 1000 A8 PMI 18 0010 0011 23 0010 0011 23 WR 17 1000 0100 84 1000 0100 84 RD 16 0110 1011 6B 1000 0001 81 BUF 15 0000 0111 07 0000 0111 07 RFR 14 0000 0001 01 0000 0001 01 MC 13 1010 0001 A1 1010 0001 A1 ML 12 1001 0111 97 1001 0111 97 FIDP and vertical shift bottom 11 0000 0000 00 0000 0000 00 VREFP and vertical shift top 10 0000 0000 00 0000 0000 00 HREFP and horizontal shift 9 0000 0000 00 0000 0000 00 Filter coefficient a3 8 0000 0000 00 0000 0000 00 Filter coefficient a2 7 0000 0000 00 0000 0000 00 Filter coefficient a1 6 0000 0000 00 0000 0000 00 Shift start 5 0000 1000 08 0000 0100 04 BS_BUFFER lower level 4 0000 0000 00 0000 0000 00 BS_BUFFER upper level (LSB) 3 1111 1111 FF 1111 1111 FF BS_BUFFER upper level (MSB) 2 0100 1111 4F 0100 1111 4F Bus address (LSB) 1 1111 1111 FF 1111 1111 FF Bus address (MSB) 0 1111 1111 FF 1111 1111 FF 7.10 7.10.1 DRAM interface 7.10.3 7.10.3.1 GENERAL The DRAM interface of the SAA6750H schedules and handles all accesses of internal read and write clients to the external 4 × 4 Mbit DRAM memory. It also takes care of the DRAM refresh after Power-on reset and performs the initialization of the external DRAM. 7.10.3.2 APPLICATION HINTS DRAM initialization After the external reset signal RESETN becomes inactive, the DRAM interface immediately starts generating a DRAM initialization sequence. First, the Row Address Strobe (RASN) and Column Address Strobe (CASN) are kept stable in HIGH state for a minimum of 200 µs. After this the DRAM interface generates a sequence of initialization pulses. This sequence consists of 9 CASN cycles before RASN refresh (CBR) events (see Fig.15). It should be noted that the DRAM interface is timing sensitive. Make sure that wires between the SAA6750H and the external DRAM memories are as short as possible. In addition the CASN, RASN, address and data lines should have approximately the same parasitic load. 2000 May 03 Interface definition The connection between the DRAM interface and the memory consists of 77 signals. ADR0 to ADR8 are used to transfer the row or the column address. The signals CASN and RASN indicate, that a column/row address is present on ADR0 to ADR8. WEN enables a write access and OEN selects/deselects the associated memory chip. The signals CASN, RASN, WEN and OEN are active LOW. Four fast page mode or Extended Data Out (EDO) DRAM devices (tRAC = 60 ns) with 16-bit data and 9-bit row and column address have to be applied in parallel. Therefore the accessible DRAM format is 262144 × 64 bits. 7.10.2 FUNCTIONAL DESCRIPTION 41 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) 7.10.3.3 SAA6750H DRAM refresh 7.12 Clock distribution The DRAM interface takes care of periodically refresh of the external DRAM. Refresh is carried out by addressing the specific DRAM page. It should be noted that refresh only works if the SAA6750H is in operating mode (see Table 1). The SAA6750H needs a video clock signal VCLK as specified in Chapter “Quick reference data”. The external clock signal has to be synchronous to the video input data stream. In the standard application e.g. the clock signal is provided by a SAA7111A colour decoder. 7.10.3.4 The internal clock generation unit creates all internal processing clocks. Memory sharing The SAA6750H can be part of a system in which it shares the memory with other devices. To this end the DRAM interface output ports of the SAA6750H can be put to 3-state respectively input state by an appropriate setting of the I2C-bus control register (see Table 1). Another IC cannot use the memory concurrently with the SAA6750H. 7.10.3.5 7.13 Input/output levels All input and I/O pad cells are 5 V tolerant. The output and I/O pad cells provide 3.3 V output levels. See Chapters “Quick reference data” and “Limiting values” for detailed information. Scheduling 7.14 Boundary scan test The DRAM interface allows access to the external DRAM once every two clock cycles. Therefore the nominal ‘Fast Page Mode Cycle Time’ is tPC = 74 ns for a 27 MHz clock. If the DRAM address changes from one page to another page, which means a change in the most significant 9 bits of the address, a page transition occurs. A page transition also happens, if the data direction changes from read to write or vice versa (a change of the WEN signal). A detailed description of the timing can be found in Figs 13 and 14 and Chapter “Characteristics”. The SAA6750H has built-in logic and 5 dedicated pins to support boundary scan testing, which allows board testing without special hardware (nails). The SAA6750H follows the “IEEE Std. 1149.1 - Standard Test Access Port and Boundary Scan Architecture” set by the Joint Test Action Group (JTAG) chaired by Philips. All internal clients of the DRAM interface are served using a round robin scheme where the access time of each client can be programmed via the I2C-bus within some limits. These settings are depending on the embedded microcode and will be provided in the software package. Within one macroblock-period, which is defined as 650 clock cycles of the 27 MHz system clock, all clients have to be served at least with two accesses but the sum of all client accesses is not allowed to exceed the time of one macroblock period. The Boundary Scan Test (BST) functions BYPASS, EXTEST, SAMPLE, CLAMP and IDCODE are all supported (see Table 25). Details about the JTAG BST-TEST can be found in the specification “IEEE Std. 1149.1”. A file containing the detailed Boundary Scan Description Language (BSDL) description of the SAA6750H is available on request. 7.11 7.14.1 The 5 special pins are Test Mode Select (TMS), Test Clock (TCK), Test Reset (TRST), Test Data Input (TDI) and Test Data Output (TDO). FIFO memories The FIFOs are data buffers which connect the internal processes. This kind of coupling is necessary because due to the multi-processor architecture e.g. one process may give bursts of data, while the next process consumes the data at constant rate. The state of the FIFOs therefore also has an impact on the process behaviour. As long as the FIFO buffers are not full or empty, the depending processes work at their normal speed. If a data read or write request from or to a FIFO cannot be served, the depending process is interrupted. 2000 May 03 GENERAL 42 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) SAA6750H Table 25 Boundary Scan Test (BST) instructions supported by the SAA6750H INSTRUCTION DESCRIPTION BYPASS This mandatory instruction provides a minimum length serial path (1 bit) between TDI and TDO, when no test operation of the component is required. EXTEST This mandatory instruction allows testing of off-chip circuitry and board level interconnections. SAMPLE This mandatory instruction can be used to take a sample of the inputs during normal operating of the component. It can also be used to preload data values into the latched outputs of the boundary scan register. CLAMP This optional instruction is useful for testing, when not all ICs have BST. This instruction addresses the bypass register, while the boundary scan register is in external test mode. IDCODE This optional instruction will provide information on the components manufacturer, part number and version number. 7.14.2 INITIALIZATION OF BOUNDARY SCAN CIRCUIT Its biggest advantage is the possibility to check for the correct ICs mounted after production and determination of the version number of ICs during field service. The Test Access Port (TAP) controller of an IC should be in the reset state (TEST_LOGIC_RESET), when the IC is in functional mode. This reset state also forces the instruction register into a functional instruction such as IDCODE or BYPASS. When the IDCODE instruction is loaded into the BST instruction register, the identification register will be connected between TDI and TDO of the IC. The identification register will load a component specific code during the CAPTURE_DATA_REGISTER state of the TAP controller and this code can subsequently be shifted out. At board level this code can be used to verify component manufacturer, type and version number. The device identification register contains 32 bits, numbered 31 to 0, where bit 31 is the most significant bit (nearest to TDI) and bit 0 is the least significant bit (nearest to TDO); see Fig.11. To solve the power-up reset, the standard specifies that the TAP controller will be forced asynchronously to the TEST_LOGIC_RESET state by setting pin TRST to LOW. 7.14.3 DEVICE IDENTIFICATION CODES A device identification register is specified in “IEEE Std. 1149.1-1990 -IEEE Standard Test Access Port and Boundary Scan Architecture”. It is a 32-bit register which contains fields for the specification of the IC manufacturer, the IC part number and the IC version number. MSB handbook, full pagewidth TDI LSB 31 28 27 0001 4 bits version code 12 11 1 0 0010 1011 0110 0000 0000 0010 101 1 16-bit part number 11-bit manufacturer identification Fig.11 32 bits of identification code. 2000 May 03 43 TDO MHB670 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) SAA6750H 8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER VDD digital supply voltage VI digital input voltage CONDITIONS note 1 MIN. MAX. UNIT −0.5 +4.0 V −0.5 +5.5 V VO digital output voltage −0.5 VDD + 0.5 V Ilu(prot) latch-up protection current − 100 mA Ptot total power dissipation − 2.0 W Tstg storage temperature −25 +150 °C Tamb ambient temperature Ves electrostatic handling voltage 0 70 °C note 2 −2000 +2000 V note 3 −200 +200 V Notes 1. All input pads, input/output pads in input mode and output pads in 3-state mode are 5 V tolerant. 2. Human body model: C = 100 pF; R = 1.5 kΩ. 3. Machine model: C = 200 pF; L = 0.75 µH; R = 0 Ω. 9 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) 2000 May 03 PARAMETER thermal resistance from junction to ambient CONDITIONS VALUE UNIT in free air; soldered to a PCB with supply and ground plane 28 K/W 44 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) SAA6750H 10 CHARACTERISTICS VDDCO = 3.3 V; VDD = 3.3 V; supply voltages VDD and VDDCO are connected externally together; grounds VSS and VSSCO are connected externally together; Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies: VDD and VDDCO VDD digital supply voltage (I/O cells) 3.0 3.3 3.6 V VDDCO digital supply voltage (core) 3.0 3.3 3.6 V IDD digital supply current (I/O cells) − 40 − mA IDDCO digital supply current (core) − 180 − mA IDD(tot) total digital supply current − 0.22 0.56 A Ptot total power dissipation − 0.73 2.0 W Inputs: YUV7 to YUV0, FID, HSYNC, VSYNC, VCLK, RESETN, MAD, FAD_RWN, FAD_EN, AS_ALE, DS_RDN, CS_TEST and TEST; note 1 VIL LOW-level input voltage −0.5 − +0.8 V VIH HIGH-level input voltage VDD = 3.6 V 2.0 − 5.5 V IIL LOW-level input current VIL = VSS − − 1 µA IIH HIGH-level input current VIH = VDD −1 − − µA CI input capacitance − − 10 pF −0.5 − +0.8 V Inputs: TRST, TCK, TMS, TDI, I_MN and CSN; notes 1 and 2 VIL LOW-level input voltage VIH HIGH-level input voltage VDD = 3.6 V 2.0 − 5.5 V Ipu pull-up input current VIL = VSS − − 125 µA IIH HIGH-level input current VIH = VDD −10 − − µA CI input capacitance − − 10 pF −0.5 − +0.8 V Inputs/outputs (3-state): DATA63 to DATA0, AD15 to AD0, GPIO11 to GPIO0; note 1 VIL LOW-level input voltage VIH HIGH-level input voltage VDD = 3.6 V 2.0 − 5.5 V VOL LOW-level output voltage 3 mA sink current − − 0.4 V VOH HIGH-level output voltage 3 mA load current 2.4 − VDD V ITL 3-state leakage current VIH = VDD; VIL = VSS −5 − +5 µA CI input capacitance − − 10 pF CL load capacitance − − 40 pF Output (3-state): TDO; note 3 VOL LOW-level output voltage 3 mA sink current − − 0.4 V VOH HIGH-level output voltage 3 mA load current 2.4 − VDD V ITL 3-state leakage current VIH = VDD; VIL = VSS −5 − +5 µA CL load capacitance − − 40 pF 2000 May 03 45 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) SYMBOL PARAMETER SAA6750H CONDITIONS MIN. TYP. MAX. UNIT Outputs (3-state): ADR8 to ADR0, CASN, RASN, WEN and OEN; note 3 VOL LOW-level output voltage 3 mA sink current; CASN: 6 mA sink current − − 0.4 V VOH HIGH-level output voltage 3 mA load current; CASN: 6 mA load current 2.4 − VDD V ITL 3-state leakage current VIH = VDD; VIL = VSS −5 − +5 µA CL load capacitance any pin except CASN − − 40 pF only CASN pin − − 60 pF − − 0.4 V 2.4 − VDD V −5 − − µA − − 40 pF 35 37 39 ns Outputs (open-drain): LRQN, URQN, DTACK_RDY and FAD_RDYN; note 4 VOL LOW-level output voltage VOH HIGH-level output voltage ISL switch-off leakage current CL load capacitance 3 mA sink current VOH = VDD Video clock input timing: VCLK; see Fig.12 Tcy cycle time δ duty factor tHIGH/Tcy 40 50 60 % tr(VCLK) rise time VDD = 0.8 to 2.0 V − − 5 ns tf(VCLK) fall time VDD = 2.0 to 0.8 V − − 6 ns Video input data and control input timing: YUV7 to YUV0, FID, HSYNC and VSYNC; see Fig.12 tSU; DAT data set-up time 6 − − ns tHD; DAT data hold time 3 − − ns 2000 May 03 46 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) SYMBOL PARAMETER SAA6750H CONDITIONS MIN. TYP. MAX. UNIT DRAM interface data, address and control timing: DATA63 to DATA0, ADR8 to ADR0, CASN, RASN, WEN and OEN; see Figs 13 to 15 tPC fast page mode cycle time 60 2Tcy − ns tRP RASN precharge time 60 2Tcy − ns tRHCP RASN hold time from CASN precharge 60 2Tcy − ns tRDH read data hold time 0 − − ns tCAS CASN pulse width 30 Tcy 45 ns tCP precharge time (page mode) 30 Tcy − ns tRCS read command set-up time 60 2Tcy − ns tRCH read command hold time referenced to CASN 30 Tcy − ns tWCS WEN set-up time 60 2Tcy − ns tWCH WEN hold time referenced to CASN 30 2Tcy − ns tRRH read command hold time referenced to RASN 30 Tcy − ns tCSS chip select OEN set-up time 60 2Tcy − ns tCSH chip select OEN hold time referenced to CASN 0 − − ns tASR row address set-up time 20 Tcy − ns tRAH row address hold time 12 1⁄ 2Tcy − ns tASC column address set-up time 10 note 5 − ns tCAH column address hold time 20 Tcy − ns tDS data write set-up time 20 Tcy − ns tDH data write hold time 20 Tcy − ns tRAC access time from RASN − − 60 ns tCAC access time from CASN − − 20 ns tRCI read/write cycle time in initialization mode 160 5Tcy − ns tRASI RASN pulse width in initialization mode 100 3Tcy − ns tCSR CASN set-up time 30 Tcy − ns tCHR CASN hold time 30 Tcy − ns 2000 May 03 47 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) SYMBOL PARAMETER SAA6750H CONDITIONS MIN. TYP. MAX. UNIT Data output interface timing: DTACK_RDY, I_MN, CSN, AS_ALE, DS_RDN and AD15 to AD0; see Figs 16 and 17 and Table 13 tas address set-up time 15 − − ns tah address hold time 20 − − ns taz address 3-state time 20 − − ns tcs CSN set-up time 0 − − ns tdhr data hold time read 0 − − ns tdsr data set-up time read 0 − − ns tidl AS pulse width tdrtL DTACK reaction time LOW tdrtH DTACK reaction time HIGH trwi tdz 60 − − ns − 2Tcy − ns − Tcy − ns read/write or data strobe pulse width 60 − − ns data 3-state 0 − 60 ns note 6 I2C-bus interface: SCL and SDA; note 7 fSCL SCL clock frequency 100 − 400 kHz VIL LOW-level input voltage − − 0.3VDD V VIH HIGH-level input voltage 0.7VDD − 5.5 V II input current −10 − +10 µA VOL LOW-level output voltage 3 mA sink current 0 − 0.4 V 6 mA sink current 0 − 0.6 V 1.3 − − µs tLOW SCL LOW time tHIGH SCL HIGH time 0.6 − − µs tr rise time SDA and SCL − − 0.3 µs tf fall time SDA and SCL − − 0.3 µs tSU;DAT data set-up time 100 − − ns tHD;STA hold time START condition 0.6 − − µs tSU;STO set-up time STOP condition 0.6 − − µs Notes 1. All input pins are 5 V tolerant. 2. In accordance with the “IEEE1149.1” standard the input pins TCK, TDI, TMS and TRST must have an internal pull-up resistor. 3. The outputs, which can be switched in the 3-state mode, are 5 V tolerant due to the bus application of 5 V. 4. The open-drain outputs, which can be switched off, are 5 V tolerant due to the 5 V application. 5. 1⁄ 2Tcy applies for first column address after a row address, Tcy for all other modes. 6. Typical values are maximum when data is available. 7. I/O pins of the I2C-bus interface must not obstruct the SDA and SCL lines if the supply voltage VDD is switched off. 2000 May 03 48 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) SAA6750H Tcy handbook, full pagewidth t HIGH t LOW 2.0 V 1.5 V 0.8 V VCLK t SU;DAT data and control inputs t HD;DAT t f(VCLK) valid t r(VCLK) not valid valid not valid valid 2.0 V 0.8 V t OH;DAT data and control outputs valid 2.4 V 0.4 V MHB671 Fig.12 Clock data timing. 2000 May 03 49 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) SAA6750H t RP handbook, full pagewidth t RHCP RASN t RRH t CP CASN t CAS t WCH t PC t WCS WEN OEN HIGH tASR tASC t CAH t RAH ADR8 to ADR0 RA CA1 CA2 CA3 CA4 DATA3 DATA4 CA5 t DS t DH DATA63 to DATA0 DATA1 DATA2 DATA5 MHB672 RA = row address. CA = column address. Fig.13 DRAM fast page mode write cycles to external DRAM. 2000 May 03 50 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) SAA6750H t RP handbook, full pagewidth t RHCP RASN t RCS t RRH t CP CASN t CAS t RCH WEN t PC t CSS t RDH OEN tASR t CSH tASC t RAH ADR8 to ADR0 t CAH RA CA1 CA2 CA3 CA4 CA5 t CAC t RAC DATA63 to DATA0 XXXX DATA1 DATA2 DATA3 DATA4 MHB673 RA = row address. CA = column address. Fig.14 DRAM fast page mode read cycles from external DRAM. handbook, full pagewidth 9 cycles are provided t RCI t RASI t RP t VCLK t RP RASN t CSR t CHR CASN MHB674 Fig.15 DRAM initialization sequence. 2000 May 03 51 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) address phase handbook, full pagewidth t as SAA6750H first data phase second data phase stop t ah AD15 to AD0 address read data address read data t az t idl t dsr AS_ALE t dhr t rwi DS_RDN t drtL t dz t drtH DTACK_RDY I_MN CSN LOW HIGH MHB675 Fig.16 Motorola-style protocol mode (internal address decoding). address phase handbook, full pagewidth first data phase AD15 to AD0 AS_ALE second data phase read data stop read data HIGH t dsr t rwi t dhr DS_RDN t drtL t drtH t dz DTACK_RDY t cs I_MN LOW t idl CSN MHB676 Fig.17 Motorola-style protocol mode (external address decoding). 2000 May 03 52 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) SAA6750H 11 APPLICATION INFORMATION handbook, full pagewidth audio input (analog) audio output (analog) audio data AUDIO AD/DA D1 16 Mbit EXTERNAL DRAM audio clock S-video or CVBS input (analog) I2S SAA1309 SAA7146A PCI BRIDGE SAA7112/ SAA7114 SAA6750H CVBS CVBS DECODER ES data MPEG2 VIDEO ENCODER I2C-bus S-video or CVBS output (analog) SAA7185 DEBI I2C D1 VIDEO ENCODER PCI-bus MHB677 PCI TO SCSI VGA HARDDISK MONITOR CPU AND MEMORY Fig.18 PC application circuit. 2000 May 03 53 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) SAA6750H 12 PACKAGE OUTLINE SQFP208: plastic shrink quad flat package; 208 leads (lead length 1.3 mm); body 28 x 28 x 3.4 mm; high stand-off height SOT316-1 c y X A 156 157 105 104 ZE e E HE A A2 A1 (A 3) wM θ Lp bp L pin 1 index 208 detail X 53 52 1 ZD wM bp e v M A D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 4.10 0.50 0.25 3.6 3.2 0.25 0.27 0.17 0.20 0.09 28.1 27.9 28.1 27.9 0.5 30.9 30.3 30.9 30.3 1.3 0.75 0.45 0.2 0.08 0.08 Z D (1) Z E (1) θ 1.39 1.11 8 0o 1.39 1.11 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT316-1 2000 May 03 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 99-12-27 00-01-25 MS-029 54 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) SAA6750H If wave soldering is used the following conditions must be observed for optimal results: 13 SOLDERING 13.1 Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. 13.2 – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 13.3 13.4 Wave soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. 2000 May 03 Manual soldering When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 55 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) 13.5 SAA6750H Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA not suitable suitable(2) HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO REFLOW(1) suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 14 DATA SHEET STATUS DATA SHEET STATUS PRODUCT STATUS DEFINITIONS (1) Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Note 1. Please consult the most recently issued data sheet before initiating or completing a design. 2000 May 03 56 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) SAA6750H 15 DEFINITIONS 16 DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 17 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2000 May 03 57 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) SAA6750H NOTES 2000 May 03 58 Philips Semiconductors Product specification Encoder for MPEG2 image recording (EMPIRE) SAA6750H NOTES 2000 May 03 59 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753504/25/02/pp60 Date of release: 2000 May 03 Document order number: 9397 750 06806