CXD2931R 1 chip GPS LSI Description The CXD2931R is a dedicated LSI for the GPS (Global Positioning System) satellite-based position measurement system. This LSI contains a 32-bit RISC CPU, 2M-bit MASK ROM, RAM, UART, timer, and others. This LSI, used together with the RF LSI (CXA1951AQ), enables the configuration of a 2-chip system capable of measuring its position anywhere on the globe. Features • 16-channel GPS receiver capable of simultaneously receiving 16 satellites • Supports differential GPS — Comforms to RTCM SC-104 Ver. 2.1 — Supports DARC • All-in-view measurement • 2-satellite measurement • Timer supporting GPS time • High performance 32-bit RISC CPU • 256K-byte program ROM • 36K-byte RAM • 3-channel UART — Baud rate generator — Supports 1.2K, 2.4K, 4.8K, 9.6K, 19.2K and 38.4K baud — Supports 1/2/4-byte buffer mode • 23-bit general-purpose I/O port capable of defining input/output independently for each bit 144 pin LQFP (Plastic) Absolute Maximum Ratings • Supply voltage VDD VSS – 0.5 to 4.6 V • Input voltage VI VSS – 0.5 to VDD + 0.5 V • Output voltage VO VSS – 0.5 to VDD + 0.5 V • Operating temperature Topr –40 to +85 °C • Storage temperature Tstg –50 to +150 °C Recommended Operating Conditions • Supply voltage VDD 3.0 to 3.6 • Operating temperature Topr –40 to +85 V °C Input/Output Pin Capacitance • Input capacitance CIN • Output capacitance COUT • I/O capacitance CI/O 9 (Max.) 11 (Max.) 11 (Max.) pF pF pF Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E99702-PS CXD2931R Performance • 16-channel GPS receiver • High performance 32-bit RISC CPU • Reception frequency 1575.42MHz (L1 band, CA code) • Reception sensitivity (using the CXA1951AQ in the RF block) –130dBm or less • Time to first fix∗ (time until initial measurement after power-on) Cold Start (without ephemeris and almanac) 35 to 60s Warm Start (without ephemeris with almanac) 33 to 50s Hot Start (with ephemeris and almanac) 6 to 20s Reacquisition Time (interrupt recovery time) Less than 5 minutes: < 3 to 6s 5 minutes or more: < 6 to 10s • Positioning accuracy Stand alone (GPS unit only) D-GPS (differential GPS) 1σ: < 30m 3σ: < 90m 1σ: < 6m 3σ: < 18m • Measurement data update time Every 1s • Communication method Sony standard serial communication Supports NMEA-0183 • All-in-view measurement • 2-satellite measurement • High performance 32-bit RISC CPU ∗ The noted values may be exceeded depending on the operating environment and other conditions. Antenna CXA1951AQ RF Converter 0V 0V TCXO IF TXD CXD2931R 16ch GPS Processor RXD GPS receiver system diagram using the CXD2931R –2– CXD2931R PORT (0:15) DWR DRD DB (0:7) DADR (0:15) DC0 to 5/PORT (16:21) XCS0 IWR IRD IB (0:15) IADR (0:18) ICS0, 1 Block Diagram TEST0, 1 ICST0, 1 BIU RUN XROMW HOLD CLKS NMI CLKI PMI 32bit RISC IODBK CLKO CLKOUT HOLDA TCXOS SINT/PORT (22) EXRS 256K Byte ROM PWRST 36K Byte SRAM VDD × 10 VSS × 10 TXD0 to 2 UART (Baud Rate Generator) × 3 RXD0 to 2 TIMER × 3 AVD 8bit ADC 16ch GPS DSP AVS VRT –3– AVIN IF0 IF0O CCKI CCKO TOSEL OTCXO ITCXO TCXO XTCXO VRB CXD2931R IB9 IB10 VDD IB11 IB12 IB13 IB14 IB15 DRD DWR XCS0 DADR0 DADR1 VSS DADR2 DADR3 DADR4 DADR5 DADR6 DADR7 DADR8 DADR9 VDD DADR10 DADR11 DADR12 DADR13 DADR14 DADR15 DB0 DB1 VSS DB2 DB3 DB4 DB5 Pin Configuration 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 DB6 109 72 IB8 DB7 110 71 IB7 SINT/PORT22 111 70 VSS DCS0/PORT21 112 69 IB6 VDD 113 68 IB5 DCS1/PORT20 114 67 IB4 DCS2/PORT19 115 66 IB3 DCS3/PORT18 116 65 IB2 DCS4/PORT17 117 64 IB1 DCS5/PORT16 118 63 VDD PORT15 119 62 IB0 PORT14 120 61 IADR18 VSS 121 60 IADR17 PORT13 122 59 IADR16 PORT12 123 58 IADR15 PORT11 124 57 IADR14 PORT10 125 56 IADR13 PORT9 126 55 VSS PORT8 127 54 IADR12 PORT7 128 53 IADR11 VDD 129 52 IADR10 PORT6 130 51 IADR9 PORT5 131 50 IADR8 PORT4 132 49 IADR7 PORT3 133 48 IADR6 PORT2 134 47 VDD PORT1 135 46 IADR5 PORT0 136 45 IADR4 VSS 137 44 IADR3 TXD2 138 43 IADR2 RXD2 139 42 IADR1 TXD1 140 41 XROMW RXD1 141 40 ICS1 TXD0 142 39 VSS RXD0 143 38 ICS0 37 IRD IWR RUN VDD CLKOUT CLKS CLKO CLKI VSS PWRST EXRS IODBK VDD HOLDA XTCXO PMI TCXO NMI VSS HOLD AVS VDD VRB –4– TCXOS VRT IF0O AVD IF0 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 ICST1 8 ICST0 7 VSS 6 CCKO 5 CCKI 4 TEST1 3 TEST0 2 OTCXO 1 AVIN VDD 144 CXD2931R Pin Configuration Pin No. Symbol I/O Description 1 AVD — 2 AVIN I 3 VRT I 4 VRB I 5 AVS — A/D converter GND. 6 VSS — GND 7 TCXO I 8 XTCXO O 9 VDD — Power supply. 10 OTCXO O TCXO clock output. 11 TEST0 I 12 TEST1 I 13 CCKI I 14 CCKO O 15 VSS — 16 ICST0 I 17 ICST1 I 18 IF0 I 19 IF0O O 20 TCXOS I 21 VDD 22 HOLD I Hold input signal. (High: Hold) 23 NMI I Non maskable interrupt. 24 PMI I Program maskable interrupt. 25 HOLDA O Hold acknowledge signal. 26 IODBK O Break signal for debugging. 27 EXRS I Reset input signal. 28 PWRST I Connect to main power supply. Leave open during backup. 29 VSS 30 CLKI I 31 CLKO O 32 CLKS I CPU clock select signal. (Low: TCXO, High: CLKI) 33 CLKOUT O CPU clock output. 34 VDD — Power supply. 35 RUN O Signal indicating CPU operating status. — — A/D converter power supply. Analog input. Reference input. TCXO binary conversion circuit/crystal oscillator. Test. (Low level fixed) Timer oscillation. (32.768kHz ± 100ppm) GND Test. (Low level fixed) IF signal binary conversion circuit. TCXO select. (Low: TCXO/2, High: TCXO through) Power supply. GND CPU clock oscillation circuit. –5– CXD2931R Pin No. Symbol I/O Description 36 IWR O Write signal for external expansion memory. 37 IRD O Read signal for external expansion memory. 38 ICS0 O Chip select 0 for external expansion memory. 39 VSS — GND 40 ICS1 O Chip select 1 for external expansion memory. 41 XROMW I Wait signal for external expansion memory. (High: Wait) 42 IADR1 I/O 43 IADR2 I/O 44 IADR3 I/O 45 IADR4 I/O 46 IADR5 I/O 47 VDD — 48 IADR6 I/O 49 IADR7 I/O 50 IADR8 I/O 51 IADR9 I/O 52 IADR10 I/O 53 IADR11 I/O 54 IADR12 I/O 55 VSS — 56 IADR13 I/O 57 IADR14 I/O 58 IADR15 I/O 59 IADR16 I/O 60 IADR17 I/O 61 IADR18 I/O (MSB) 62 IB0 I/O (LSB) Data bus I/O for external expansion memory. 63 VDD — Power supply. 64 IB1 I/O 65 IB2 I/O 66 IB3 I/O 67 IB4 I/O 68 IB5 I/O 69 IB6 I/O 70 VSS — (LSB) Address signal for external expansion memory. Power supply. Address signal for external expansion memory. GND Address signal for external expansion memory. Data bus I/O for external expansion memory. GND –6– CXD2931R Pin No. Symbol I/O Description 71 IB7 I/O 72 IB8 I/O 73 IB9 I/O 74 IB10 I/O 75 VDD — 76 IB11 I/O 77 IB12 I/O 78 IB13 I/O 79 IB14 I/O 80 IB15 I/O (MSB) 81 DRD O Read signal for external expansion data memory. 82 DWR O Write signal for external expansion data memory. 83 XCS0 O Chip select signal for external expansion data memory. 84 DADR0 I/O (LSB) 85 DADR1 I/O Address signal for external expansion data memory. 86 VSS — GND 87 DADR2 I/O 88 DADR3 I/O 89 DADR4 I/O 90 DADR5 I/O 91 DADR6 I/O 92 DADR7 I/O 93 DADR8 I/O 94 DADR9 I/O 95 VDD — 96 DADR10 I/O 97 DADR11 I/O 98 DADR12 I/O 99 DADR13 I/O 100 DADR14 I/O 101 DADR15 I/O (MSB) 102 DB0 I/O (LSB) 103 DB1 I/O Data bus I/O for external expansion data memory. 104 VSS — GND Data bus I/O for external expansion memory. Power supply. Data bus I/O for external expansion memory. Address signal for external expansion data memory. Power supply. Address signal for external expansion data memory. –7– CXD2931R Pin No. Symbol I/O Description 105 DB2 I/O 106 DB3 I/O 107 DB4 I/O 108 DB5 I/O 109 DB6 I/O 110 DB7 I/O (MSB) 111 SINT/PORT22 I/O External interrupt input signal/general-purpose I/O port. This pin can be used as a general-purpose I/O port according to the internal registers. 112 DCS0/PORT21 I/O Chip select for external expansion data memory/general-purpose I/O port. This pin can be used as a general-purpose I/O port according to the internal registers. 113 VDD — Power supply. 114 DCS1/PORT20 I/O 115 DCS2/PORT19 I/O 116 DCS3/PORT18 I/O 117 DCS4/PORT17 I/O 118 DCS5/PORT16 I/O 119 PORT15 I/O 120 PORT14 I/O 121 VSS — 122 PORT13 I/O 123 PORT12 I/O 124 PORT11 I/O 125 PORT10 I/O 126 PORT9 I/O 127 PORT8 I/O 128 PORT7 I/O 129 VDD — 130 PORT6 I/O 131 PORT5 I/O 132 PORT4 I/O 133 PORT3 I/O 134 PORT2 I/O 135 PORT1 I/O 136 PORT0 I/O 137 VSS — GND 138 TXD2 O UART transmission data output (channel 2) Data bus I/O for external expansion data memory. Chip select for external expansion data memory/general-purpose I/O port. These pins can be used as a general-purpose I/O port according to the internal registers. General-purpose I/O port. GND General-purpose I/O port. Power supply. General-purpose I/O port. –8– CXD2931R Pin No. Symbol Description I/O 139 RXD2 I UART reception data input (channel 2) 140 TXD1 O UART transmission data output (channel 1) 141 RXD1 I UART reception data input (channel 1) 142 TXD0 O UART transmission data output (channel 0) 143 RXD0 I UART reception data input (channel 0) 144 VDD — Power supply. –9– CXD2931R Electrical Characteristics DC Characteristics (VDD = 3.0 to 3.6V, Topr = –40 to +85°C) Item Symbol Input voltage (1) (CMOS level) High level VIH (1) Input voltage (2) (5V interface) High level VIH (2) Output voltage (1) Low level Low level Output voltage (3) Typ. VIL (1) 0.7 × VDD VIL (2) VOL (1) VOL (2) Max. Unit Applicable pins VDD V 0.2 × VDD ∗1 V 5.5 V 0.2 × VDD V VDD – 0.4 V IOL = 4.0mA High level VOH (2) IOH = –8.0mA Low level Min. 0.7 × VDD High level VOH (1) IOH = –4.0mA Low level Output voltage (2) Condition 0.4 VDD – 0.4 0.4 High level VOH (3) IOH = –12.0mA VDD – 0.4 Low level VOL (3) Current consumption in standby mode ISTB Supply current IDD 0.4 VDD = 3.0V 20 70 VDD = 1.8V 4 50 f = 18.414MHz 55 ∗4 V V IOL = 12.0mA ∗3 V V IOL = 8.0mA ∗2 ∗5 V µA — mA — Applicable pins ∗1 Pins 11, 12, 16, 17, 20, 22 to 24, 32, 41 ∗2 Pins 62, 64 to 69, 72 to 74, 76 to 80, 84, 85, 87 to 94, 96 to 103, 105 to 112, 114 to 120, 122, 128, 130 to 136, 139, 141, 143 ∗3 Pins 10, 25, 26, 33, 35, 42 to 46, 48 to 54, 56 to 61, 81 to 83, 138, 140, 142 ∗4 Pins 38, 40, 62, 64 to 69, 71 to 74, 76 to 80, 84, 85, 87 to 94, 96 to 103, 105 to 112, 114 to 120, 122 to 128, 130 to 136 ∗5 Pins 36, 37 – 10 – CXD2931R AC Characteristics (1) When inputting a pulse to the TCXO pin (VDD = 3.0 to 3.6V, Topr = –40 to +85°C) 1/fTCK tTH tTL TCXO When inputting a binary-converted signal Item Symbol TCXO clock frequency fTCK TCXO clock pulse width tTH, tTL Min. Typ. Max. Unit Typ. – 3ppm 18.414 Typ. + 3ppm MHz 10 ns 0.01µF 7 VDD/2 0.8Vp-p 1MΩ 8 When performing binary conversion with the TCXO and XTCXO pins (Pins 7 and 8) (2) When performing self-oscillation with the CCKI and CCKO pins (VDD = 3.0 to 3.6V, Topr = –40 to +85°C) 220pF 13 220pF 10MΩ 14 32.768kHz ± 100ppm (3) IF signal input (VDD = 3.0 to 3.6V, Topr = –40 to +85°C) 0.01µF 18 VDD/2 0.8Vp-p 1MΩ 19 (4) When performing self-oscillation with the MCKI, MCKO pins (VDD = 3.0 to 3.6V, Topr = –40 to +85°C) 15pF 30 1MΩ 15pF 31 X'tal – 11 – CXD2931R Battery Backup Mode The battery backup mode is activated when the power for the GPS receiver is turned off and power-on reset goes to low level. The timer clock continues to operate even when power-on reset goes low, but all other clock are fixed high and the LSI is set to the low power consumption mode. At this time, the RAM data is held and the registers are initialized. Battery backup mode is canceled by setting power-on reset to high. 10 clocks Power-on reset EXRS PWRST 100ms or more Timer clocks CCKI, CCKO Other clocks TCXO, XTCXO, CLKI, CLKO Normal outputs TXD0 to 2, OTCXO, HOLDA Fixed low Tri-state outputs IODBK, RUN, CLKOUT Fixed low Tri-state outputs ICS0, ICS1, IADR[18:1], IRD, IWR, DRD, DWR, XCS0 Hi-Z Fixed low Bidirectional (Input) SINT, IB[15:0], DCS0 to 5, DADR[15:0], DB[7:0], PORT[15:0] (Outut) Hi-Z Inputs RXD0 to 2, ITCXO, IF0 to 2, HOLD, NMI, PMI Fixed low – 12 – CXD2931R CXD2931R Initialization CXD2931R initialization is started by setting the reset input signal EXRS (Pin 27) to low level. The timing should satisfy the conditions noted below. 1. During power-on (power-on reset) (VDD = 3.0 to 3.6V, Topr = –40 to +85°C) VDD VDD [V] Power supply, PWRST (Pin 28) EXRS (Pin 27) 100ms or more VDD/2 GND The PWRST (Pin 28) signal should rise simultaneously with the power supply. The EXRS (Pin 27) signal should rise 100ms or more after the power supply and the PWRST signal have risen. Note that the PWRST signal should be left open during battery backup. 2. Initialization during operation (VDD = 3.0 to 3.6V, Topr = –40 to +85°C) Power supply, PWRST (Pin 28) VDD EXRS (Pin 27) VDD [V] 100µs or more VDD/2 GND The internal registers can be initialized during operation by setting the EXRS (Pin 27) signal to low level for 100µs or more. Keep the PWRST (Pin 28) signal at high level at this time. – 13 – CXD2931R • External Command Fetch Timing (XROMW = 0) CLKOUT (a) (b) IADR (c) (d) ICS0, ICS1 (e) (f) IRD (g) (16) IB No. (h) Item Min. Typ. Max. Unit (a) Read cycle time (Fex: @20MHz) — 100 — ns (b) Address delay time — — 5 ns (c) Chip select fall delay time 2 — 10 ns (d) Chip select rise delay time 2 — 9 ns (e) Read signal fall delay time 1 — 3 ns (f) Read signal rise delay time 1 — 5 ns (g) Read data setup time 23 — — ns (h) Read data hold time 0 — — ns ∗ The load capacitance = 30pF. • External Command Fetch Timing (XROMW = 1) CLKOUT IADR ICS0, ICS1 IRD (16) IB – 14 – CXD2931R • External Data Access Timing (ICS0, ICS1/XROMW = 0) (1) Read (half-word access/XROMW = 0) CLKOUT (a) (b) IADR (c) (d) (e) (f) ICS0, ICS1 IRD (g) (h) (16) IB (2) Write (half-word access/XROMW = 0) CLKOUT (a) (b) IADR (c) (d) (i) (j) ICS0, ICS1 IWR (k) (16) IB No. (l) Item Min. Typ. Max. Unit (a) Read/write cycle time (Fex: @20MHz) — 100 — ns (b) Address delay time — — 5 ns (c) Chip select fall delay time 2 — 10 ns (d) Chip select rise delay time 2 — 9 ns (e) Read signal fall delay time 1 — 3 ns (f) Read signal rise delay time 1 — 5 ns (g) Read data setup time 23 — — ns (h) Read data hold time 0 — — ns (i) Write signal fall delay time 0 — 1 ns (j) Write signal rise delay time 0 — 2 ns (k) Write data established time — — 5 ns (l) Write data hold time 5 — — ns ∗ The load capacitance = 30pF. – 15 – CXD2931R (3) Read (word access/XROMW = 0) CLKOUT IADR ICS0, ICS1 IRD IB H (16) L (16) (4) Write (word access/XROMW = 0) CLKOUT IADR ICS0, ICS1 IWR IB L (16) – 16 – H (16) CXD2931R • External Data Access Timing (ICS0, ICS1/XROMW = 1) (1) Read (half-word access/XROMW = 1) CLKOUT IADR ICS0, ICS1 IRD (16) IB (2) Write (half-word access/XROMW = 1) CLKOUT IADR ICS0, ICS1 IWR (16) IB (3) Read (word access/XROMW = 1) CLKOUT IADR ICS0, ICS1 IRD IB H (16) L (16) (4) Write (word access/XROMW = 1) CLKOUT IADR ICS0, ICS1 IWR IB L (16) – 17 – H (16) CXD2931R • External Data Access Timing (XCS0, DCS0 to 5/no data wait) (1) Read (byte access/no data wait) CLKOUT (a) (b) DADR (c) (d) XCS0, DCS0 to 5 (e) (f) DRD (h) (g) DB (8) (2) Write (byte access/no data wait) CLKOUT (a) (b) DADR (c) (d) XCS0, DCS0 to 5 (i) (j) DWR (l) (k) (8) DB No. Item Min. Typ. Max. Unit (a) Read/write cycle time (Fex: @20MHz) — 100 — ns (b) Address delay time — — 9 ns (c) Chip select fall delay time 4 — 13 ns (d) Chip select rise delay time 4 — 13 ns (e) Read signal fall delay time 2 — 8 ns (f) Read signal rise delay time 3 — 10 ns (g) Read data setup time 16 — — ns (h) Read data hold time 0 — — ns (i) Write signal fall delay time 0 — 1 ns (j) Write signal rise delay time 0 — 2 ns (k) Write data established time — — 7 ns (l) Write data hold time 5 — — ns ∗ The load capacitance = 30pF. – 18 – CXD2931R (3) Read (half-word access/no data wait) CLKOUT DADR XCS0, DCS0 to 5 DRD DB H (8) H (8) (4) Write (half-word access/no data wait) CLKOUT DADR XCS0, DCS0 to 5 DWR DB L (8) H (8) (5) Read (word access/no data wait) CLKOUT DADR XCS0, DCS0 to 5 DRD DB HH (8) HL (8) LH (8) LL (8) LH (8) HL (8) HH (8) (6) Write (word access/no data wait) CLKOUT DADR XCS0, DCS0 to 5 DWR DB LL (8) – 19 – CXD2931R • External Data Access Timing (XCS0, DCS0 to 5/data wait = 1) (1) Read (byte access/data wait = 1) CLKOUT DADR XCS0, DCS0 to 5 DRD (8) DB (2) Write (byte access/data wait = 1) CLKOUT DADR XCS0, DCS0 to 5 DWR (8) DB (3) Read (half-word access/data wait = 1) CLKOUT DADR XCS0, DCS0 to 5 DRD DB H (8) L (8) L (8) H (8) (4) Write (half-word access/data wait = 1) CLKOUT DADR XCS0, DCS0 to 5 DWR DB – 20 – CXD2931R (5) Read (word access/data wait = 1) CLKOUT DADR XCS0, DCS0 to 5 DRD HH (8) DB HL (8) LH (8) LL (8) LH (8) HL (8) HH (8) (6) Write (word access/data wait = 1) CLKOUT DADR XCS0, DCS0 to 5 DWR LL (8) DB • External Data Access Timing (XCS0, DCS0 to 5/data wait = 2) (1) Read (byte access/data wait = 2) CLKOUT DADR XCS0, DCS0 to 5 DRD (8) DB (2) Write (byte access/data wait = 2) CLKOUT DADR XCS0, DCS0 to 5 DWR (8) DB – 21 – CXD2931R (3) Read (half-word access/data wait = 2) CLKOUT DADR XCS0, DCS0 to 5 DRD DB H (8) L (8) L (8) H (8) (4) Write (half-word access/data wait = 2) CLKOUT DADR XCS0, DCS0 to 5 DWR DB (5) Read (word access/data wait = 2) CLKOUT DADR XCS0, DCS0 to 5 DRD DB HH (16) HL (16) LH (16) LL (16) LH (16) HL (16) HH (16) (6) Write (word access/data wait = 2) CLKOUT DADR XCS0, DCS0 to 5 DWR DB LL (16) – 22 – CXD2931R Package Outline Unit: mm 144PIN LQFP (PLASTIC) 22.0 ± 0.2 1.7 MAX 20.0 ± 0.1 1.4 ± 0.1 73 108 109 72 B A 37 144 1 36 0.5 b 0.08 M 0.1 S S S 0.1 ± 0.05 DETAIL A DETAIL B : SOLDER 0.125 ± 0.04 b = 0.20 ± 0.03 0.145 ± 0.04 (0.2) (0.125) 0° to 10° 0.5 ± 0.15 (21.0) b = 0.22 ± 0.05 DETAIL B : PALLADIUM PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER / PALLADIUM PLATING SONY CODE LQFP-144P-L01 LEAD TREATMENT EIAJ CODE LQFP144-P-2020 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 1.3 g JEDEC CODE – 23 –