CXA1951AQ GPS Down Converter Description The CXA1951AQ is an IC developed as a GPS down converter, featuring low current consumption and small package. This IC is suitable for the mobile GPS (Global Positioning System). Features • Includes all functions required for the GPS converter • Total gain: 100 dB or more • Operating supply voltage range: 2.7 to 5.5 V • Low current consumption: ICC = 30 mA (Typ. at VCC = 3 V) • Excellent temperature characteristics Applications GPS (Global Positioning System) Structure Bipolar silicon monolithic IC 40 pin QFP (Plastic) Absolute Maximum Ratings (Ta = 25 °C) • Supply voltage VCC 7.0 • Operating temperature Topr –40 to +85 • Storage temperature Tstg –65 to +150 • Allowable power dissipation PD 200 Operating Conditions Supply voltage VCC 2.7 to 5.5 V °C °C mW V Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E96743-TE CXA1951AQ LIM DEC2 LIM DEC1 LIM IN LIM VCC IF VCC IF OUT IF DEC2 IF DEC1 IF IN2 IF IN1 Block Diagram and Pin Configuration 30 29 28 27 26 25 24 23 22 21 LIM OUT 31 20 IF GND LIM GND 32 19 RF OUT2 N.C 33 18 RF OUT1 REF INV 34 17 RF VCC REF IN 35 16 RF IN2 1/4 or 1/6 PLL GND 36 15 RF IN1 PLL FC 37 14 RF GND 1/338 or 1/570 TEST OUT 38 13 RF GND OSC LOCK DET 39 12 OSC DEC 1 2 3 4 5 6 7 8 9 10 CP OUT N.C OSC GND OSC GND OSCB1 OSCE1 OSCE2 OSCB2 OSC GND 11 OSC VCC NSW PLL VCC 40 —2— CXA1951AQ Pin Description Pin No. Symbol Pinvoltage Equivalent circuit Description VCC 40k 200 1 NSW 1 — 20k Internal PLL frequency division value switching 40k 81k GND VCC 200 2 CPOUT 2 — Charge pump output GND 3, 33 NC 4, 5, OSC GND 10 — Not connected Ground for the internal oscillator 0V VCC 1.6k 1.6k 1k 6 9 7 8 OSCB1 OSCB2 OSCE1 OSCE2 2.5 V 1.7 V 1.7 V 2.5 V 1k 6 9 7 8 12k 12k Connects the internal oscillator resonator. Connects to main counter input via the internal buffer. GND 11 OSC VCC 3V 12 OSC DEC 1.7 V 13, 14 RF GND Internal oscillator power supply Connects decoupling capacitor for the internal oscillator bias power supply RF amplifier ground 0V VCC 15, 16 RF IN1 RF IN2 1.6 V 1.6 V RF amplifier input. When using as a single input, ground Pin 16 via the capacitor. 15 16 12k 12k GND —3— CXA1951AQ Pin No. 17 Symbol RF VCC Pinvoltage Equivalent circuit Description RF amplifier power supply 3V VCC 19 2k 18 18, 19 RF OUT1 RF OUT2 — — RF amplifier mixer output GND 20 IF GND 0V IF amplifier ground VCC 21, 22 IF IN1 IF IN2 1.9 V 1.9 V IF amplifier input 21 990 99k 22 200 99k 990 23, 24 IF DEC1 IF DEC2 1.9 V 1.9 V 200 IF amplifier decoupling GND 23 24 VCC 990 25 25 IF OUT IF amplifier mixer output 2.7 V GND 26 IF VCC 3V 27 LIM VCC 3V IF amplifier power supply Limiter buffer power supply VCC 28 LIM IN 2.1 V Limiter input 200 28 29 1k LIM DEC1 29, 30 LIM DEC2 2.1 V 2.1 V 30 200 96k GND —4— 1k 96k Limiter decoupling CXA1951AQ Pin No. Symbol Pinvoltage Equivalent circuit Description VCC 31 LIM OUT Limiter buffer output 31 GND 32 LIM GND 0V VCC 34 REF INV High: 2.2 V Low: 2.0 V 39.6k 200 35 200 34 39.6k 35 REF IN 36 PLL GND 2.1 V GND 0V Limiter buffer ground Reference frequency signal output. The reference frequency signal can also be made by connecting this pin and Pin 35 with a crystal oscillator to configure an oscillator. Reference frequency input and reference counter input PLL ground VCC 81k Switching for the charge pump output status and for the signal output to Pin 38 200 37 FC — 37 100k 100k GND VCC 38 High: 2.2 V TEST OUT Low: 2.0 V 200 38 GND —5— Output of the frequency division signal by the counter CXA1951AQ Pin No. Symbol Pinvoltage Equivalent circuit Description VCC 39 LOCK DET 200 High: 2.2 V Low: 0.1 V 39 Lock detection signal output GND 40 PLL VCC 3V PLL power supply —6— CXA1951AQ Electrical Characteristics Item Current consumption (VCC = 3 V, Ta = 25 °C) Symbol ICC Measurement conditions Min. Typ. 30 14 16 dB 24.5 26.5 dB fin = 4 MHz, –80 dBm fin = 4 MHz, –30 dBm Pin = VCC 59 0.7 PIN = GND Pin = VCC PIN = GND Vcpout = VCC/2 Vcpout = VCC/2 Load current = 0.1 mA Load current = 0.1 mA Balanced output Single input Single output Single input –16.5 63 0.75 9.5 –11.5 25 –25 –2 2 Front-end conversion gain CGmix1 fin = 1575.42 MHz, –60 dBm fout = 20.46 MHz fosc = 1554.96 MHz, –10 dBm 2nd mixer conversion gain CGmix2 fin = 20 MHz, –60 dBm fref = 16 MHz, –10 dBm Limiter gain Limiter output level Input High current FC Input Low current Input High current NSW Input Low current Charge pump output H current L LOCK DET output H voltage L 1st IF output resistance 1st IF input resistance 2nd IF output resistance Limiter input resistance PGlim Volim IIH IIL IFCin IFCin IOH IOL VOH VOL Romix1 Rimix2 Romix2 Rilim —7— –36 –3 Max. 40 0.8 14 36 3 2 1.4 0.84 0.69 0.84 2 1.2 1 1.2 500 2.6 1.56 1.3 1.56 Unit mA dB Vp-p µA µA µA µA mA mA V mV kΩ kΩ kΩ kΩ CXA1951AQ Design Reference Values Item Noise figure 1st IF output capacitance 1st IF input capacitance 2nd IF output capacitance Limiter input capacitance IF amplifier band width (VCC = 3 V, Ta = 25 °C) Symbol NF BWif Measurement conditions Min. f = 1.58 GHz DBS measurement Balanced output Single input Single output Single input Input Level = –60 dBm Typ. Max. 7 dB 2 2 2 2 41 pF pF pF pF MHz 2kΩ : 50Ω Noise Source Matching Circuit 100p RF MIX 1n OUT IN 1n 100p NF Measurement —8— Unit NF Meter CXA1951AQ Electrical Characteristics Measurement Circuit VCC VCC 68µ 68µ 51 4.7µ 4.7µ 1n 1n 100n 51 10n 100n 100n 100n 30 29 28 27 26 25 10n 24 10n 23 10n 22 21 0.1µ 31 20 32 19 10n VCC N. C 33 18 34 17 68µ 10n VCC 1n 51 35 4.7µ 16 10n 100p 1/4 or 1/6 36 15 10n PLL 37 VCC 14 1/338 or 1/570 38 13 OSC 39 12 100n 68µ VCC 40 4.7µ 68µ 11 1n VCC 1n 1 2 51 3 4 5 6 7 8 10 9 N. C 1n VCC —9— 1n 1n 4.7µ CXA1951AQ Application Circuit L7, L8, C10 : Jumper L9, C9 : Open LQH1NR56K04/LQH1NR47K04 LQH3N331J04/LQS33N220G04 C20 LQS33N680G04 68µ 1M R1 0.1µ 31 30 29 28 27 C15 C14 10n C13 10n 10n 4.7µ C21 C11 C18 4.7µ C22 C18 L6 0.56µ/0.47µ 51p/62p L5 0.56µ/0.47µ 10n C12 26 25 24 23 22 21 20 32 19 NC 33 18 34 17 18.414 or 16.368MHz TCXO (18fo/16fo) input SW2 C26 10n 100 15 C4 100p f = 1575.42MHz 37 68µ L3 LQS33N680G04 RF input LQP21A3N3J04 CN1 3.9n CV1 L2 C5 100p CXA1951AQ 1/4 or 1/6 36 14 PLL 3p 1/338 or 1/570 38 13 TZC03P060A110 100n C37 OSC 39 Lock detect 4.7µ C7 16 R2 Test output 68µ L4 1n C6 35 CN2 (19fo/20fo) C19 0.1µ C25 IC2 C24 Output (fo/4fo) TC7SU04F C8 4.7µ LQS33N680G04 C23 L12 4.7µ 100n 68µ L11 100n LQS33N680G04 100n VCC C17 82p 100n L10 330µ/22µ 12 (1521fo/1520fo) 47µ 1n 40 C3 11 C27 L13 LQS33N680G04 4 5 6 7 10 9 0 100p L14 D1 1p C2 100p L15 D1 C33 68µ L1 10n C29 10n C32 0 R5 4.7µ 51k NC C28 8 C35 51k R4 680 68µ 3 10n fo/4fo SW1 R3 680 100 2 1T365 1T365 1 C1 4.7µ R6 R4 R7 1n C30 2.4k R8 VCC 1.5n C31 Notice: Two component values are indicated, the order is depending on the output frequency. The first value is as for 'fo output' and the second value is as for ‘4fo output’. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. —10— CXA1951AQ Description of Operation This IC down-converts the GPS (Global Positioning System) frequency of 1.57542 GHz to fo (fo: 1.023 MHz) or 4fo. The internal configuration is divided into the analog block, consisting of the amplifier and mixer, and the digital block (including limiter), which forms the PLL. The two-stage analog block has an external filter; it converts the frequency and amplifies the signal. The PLL frequency division ratio can be switched in the digital block in order to down-convert the output signal to fo or 4fo. 1. Oscillator Transistor and bias circuits are incorporated in this IC. A Colpitts or Hartley oscillator can be configured by adding an external resonator. Also, the oscillator is a paired circuit so as to enable balanced output. IC 6 7 8 9 Example of Colpitts Oscillator Configuration (one side) IC 6 7 8 9 CP Example of Balanced Configuration A varactor (variable capacitance) diode, as shown by the dotted line, is added to this IC to configure a VCO, and the resonant frequency is varied depending on the control voltage of Pin 2 (charge pump output) to CP. —11— CXA1951AQ 2. 1st IF Output Pins 18 and 19 are open collector outputs. The bias signal is supplied by the coils, and the output is connected to the 2nd mixer input Pins 21 and 22 via the filter. Use a capacitor to cut direct current. Decoupling for Pins 23 and 24 should be done as close to the IC as possible. Filter 24 23 22 21 20 When fo is selected for IF, the frequency here is 19fo. When 4fo is selected for IF, the frequency here is 20fo. 19 VCC 18 3. 2nd IF Output Pin 25 is emitter follower output. After passing via the filter, the direct current is cut, and input is to the limiter input Pin 28. fo or 4fo is output from the limiter output Pin 31. (Pin 31 is emitter follower output.) Decoupling for Pins 29 and 30 must be done as close to the IC as possible. Filter 30 IF output (fo/4fo) 29 31 —12— 28 25 CXA1951AQ 4. NSW (Pin 1) The internal counter frequency division value is determined by connecting this pin to VCC or GND when selecting fo or 4 fo for IF, as shown in the table below. IF NSW VCO counter Reference frequency counter fo VCC 338 frequency division 4 frequency division 4fo GND 570 frequency division 6 frequency division 5. CPOUT (Pin 2) A current output charge pump configures an external loop filter for VCO control voltage. R2 2 R1 C2 C1 6. FC (Pin 37) This pin performs two functions when connected to VCC or GND; CPOUT (Pin 2) output status switching and TEST OUT (Pin 38) selector switch. (See Table 1) 7. TEST OUT (Pin 38) This is the monitor pin for the internal counter frequency division output. The frequency division signals for VCO counter and reference frequency counter can be switched depending on FC status. (See Table 1) fr > fm fr = fm fr < fm FC to VCC CPOUT TESTOUT L fr Z fr H fr FC to GND CPOUT TESTOUT H fm Z fm L fm Table 1 Z: High-impedance H: High L: Low fr: Reference frequency counter output frequency fm: VCO counter output frequency 8. LOCK DET (Pin 39) This pin detects PLL lock status. When PLL is not locked, the pin voltage is not set; when locked, it is 2V DC. Note) • The voltages mentioned are for supply voltage of 3 V, load current of 100 µA. • A thin pulse will be observed on monitoring this pin with an oscilloscope, but this is normal. —13— CXA1951AQ 9. REF IN (Pin 35) and REF INV (Pin 34) The signal input from the external oscillator to REF IN can be used as the reference signal. Further, a reference signal can be generated by connecting a crystal oscillator between Pin 35 and Pin 34. (1) Example of reference signal generated by the external oscillator As shown in the figure below, input to RFIN via the capacitor to use the external oscillator signal as the reference signal. 34 35 (2) Example of reference signal generated by the crystal oscillator As shown below, connect the crystal oscillator between Pin 34 and Pin 35, making sure that the oscillation stability, etc. is satisfactory. Further, the capacitance ratio of CI and CO should be 1 to 2 : 1 (CI : CO). Select the capacitance values so that the serial capacitance of CI and CO may be the load capacitance specified by the crystal oscillator. 34 35 CO Xtal CI 10. Power supply pin and OSC DEC (Pin 12) decoupling This IC has five power supply and ground systems, due to the following reasons: 1) It handles high frequency signals. 2) The total gain is high. (100 dB or more) 3) It combines analog and digital blocks. Therefore, it is absolutely necessary to decouple these power supply lines as close to the IC as possible. When necessary, insert the inductor (about 6.8 µ) in series in the power supply line. GND VCC As short as possible L C Power supply OSC DEC is the internal reference voltage decoupling pin, and must be grounded with a capacitor (about 100 nF). Notes on Operation Make sure to take measures for static electric damage because the high frequency signals are handled so that protection elements are omitted from this IC. —14— CXA1951AQ 2nd MiXer BW (O/P) 2nd MiXer Conversion Gain VCC = 3.0V fIF2 = 4.092MHz 30 6.5MHZ@–3dB 26 CG [dB] CG [dB] 25 VCC = 2.7V fin = 20.368MHz PLo = –10dBm Pin = –60dBm fLo = variable 23 0.1 20 75°C 25°C 0°C 40°C 15 10 1 10 100 1 10 f output [MHz] F/E 2-signal characteristics 20 60 0 55 –20 Pout [dBm] Gain [dB] Lim Amp Gain 65 50 VCC = 3.0V Input Level = –80dBm 25°C 0°C –40°C 85°C 45 40 35 –60 –100 –100 –80 –60 102 10 Frequency [MHz] IP3 IIP3 = –15dBm VCC = 2.7V fRF = 1574.42MHz fRF2 = 1575.42MHz fref = 16.368MHz Pref = –10dBm N = 190 –40 VCC vs. Current consumption –40 –20 Pin [dBm] 0 20 Front End conversion GAIN, NF 40 19 Ta = 25°C 17 35 CG, NF [dB] Current consumption [mA] P – 1dBm –28dBm –80 30 1 100 fIF1 [MHz] 35 25 15 VCC = 3V Ta = 25°C 13 CG NF 11 9 20 7 15 2.5 3 3.5 4 4.5 5 5.5 5 1450 6 VCC [V] 1500 1550 1550 Frequency [MHz] —15— 1650 1700 CXA1951AQ Unit : mm 40PIN QFP (PLASTIC) + 0.35 1.5 – 0.15 + 0.1 0.127 – 0.05 9.0 ± 0.4 + 0.4 7.0 – 0.1 0.1 21 30 20 31 A 11 40 1 + 0.15 0.3 – 0.1 0.65 10 ± 0.12 M (8.0) + 0.15 0.1 – 0.1 0.5 ± 0.2 Package Outline DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE QFP-40P-L01 LEAD TREATMENT SOLDER / PALLADIUM PLATING EIAJ CODE QFP040-P-0707 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.2g JEDEC CODE —16—