CXG1050TN Receiving Dual-Band Mixer Description The CXG1050TN is a receiving dual-band mixer MMIC. This IC is designed using the Sony's GaAs JFET process. 16 pin TSSOP (Plastic) Features • High conversion gain Gc = 9.5dB (Typ.) • Low noise figure NF = 4.9 to 5.2dB (Typ.) • Low distortion Input IP3 = –0.5 to 0dBm (Typ.) • Single 2.7V power supply operation • Low LO input power operation PLO = –15dBm • 16-pin TSSOP small package Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VDD 4.5 V • Input power PIN +5 dBm • Current consumption IDD (Mixer block) 20 mA • Operating temperature Topr –35 to +85 °C • Storage temperature Tstg –65 to +150 °C Applications 800MHz Japan digital cellular telephones (PDC) Structure GaAs J-FET MMIC Recommended Operating Conditions • Supply voltage VDD 2.7 to 3.3 • Control voltage Block Diagram 9 IFOUT 15 2.4 to 3.3 0 to 0.3 Pin Configuration 9 8 RFIN2 GND 10 7 GND VDD1 11 6 VDD2 CAP 12 5 CAP CAP 13 4 CAP CTL1 14 3 CTL2 IFOUT/VDD3 15 2 LOIN NC 16 1 OPT RFIN1 RFIN1 VCTL (H) VCTL (L) V V V 8 2 RFIN2 LOIN Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E98432-PS CXG1050TN Electrical Characteristics Conditions: VDD = 2.7V, VCTL (H) = 2.7V, VCTL (L) = 0V, fRF1 = 820MHz, fRF2 = 870MHz, fLO = fRF – 130MHz, PLO = –15dBm, unless otherwise specified (Ta = 25°C) Item Symbol Path Current consumption IDD Control current ICTL VCTL1 VCTL2 VDD1, VDD2 VDD3 → GND H L L H CTL1 → GND H L CTL2 → GND L H H Input IP3 LO to RF leak level Max. Unit — 6.3 7.5 mA L 7 9.5 12 L H — –16 –12 H L — –13 –9 L H 7 9.5 12 RFIN1 → IFOUT H L — 4.9 6.5 RFIN2 → IFOUT L H — 5.2 6.5 RFIN1 → IFOUT H L –2.5 0 — RFIN2 → IFOUT L H –3 –0.5 — LOIN → RFIN1 H L — –37 –30 LOIN → RFIN2 L H — –37 –30 IIP3 PLK Measurement condition When no signal 35 GC NF Typ. 18 RFIN2 → IFOUT Noise figure Min. — RFIN1 → IFOUT Conversion gain Control pin condition µA dB When a small signal dB PRF = –25dBm, offset = 100kHz Conversion by dBm the IM3 suppression ratio for twowave input dBm fLO = 690MHz fLO = 740MHz Note) The values shown above are the specified values on the Sony's recommended evaluation board. –2– CXG1050TN Recommended Evaluation Circuit L6 RFIN1 50Ω C13 C14 9 L8 L9 L7 10 7 11 6 R1 R2 VDD1 (LO AMP 1) C10 4 13 C8 C7 CTL1 3 14 CTL2 C6 C5 L1 15 L2 C12 5 12 C9 C2 VDD2 (LO AMP 2) L5 L4 C11 IFOUT 50Ω RFIN2 50Ω 8 2 C4 C1 L3 LOIN 50Ω R3 VDD3 (MIX) C3 16 1 L1 82nH C1 12pF C10 100pF L2 39nH C2 1000pF C11 100pF L3 27nH C3 1000pF C12 100pF L4 47nH C4 100pF C13 2pF L5 39nH C5 100pF C14 2pF L6 39nH C6 100pF R1 680Ω L7 10nH C7 1000pF R2 680Ω L8 33nH C8 1000pF R3 820Ω L9 8.2nH C9 100pF –3– CXG1050TN Example of Representative Characteristics (Ta = 25°C) Path RFIN1 → IFOUT Gc, NF vs. fRF Gc 10 12 VDD = 2.7V VCTL1 = 2.7V VCTL2 = 0V fLO = fRF – 130MHz PLO = –15dBm Gc – Conversion gain, NF – Noise figure [dB] Gc – Conversion gain, NF – Noise figure [dB] 12 Path RFIN2 → IFOUT Gc, NF vs. fRF 8 6 NF 4 2 800 820 840 860 880 10 VDD = 2.7V VCTL1 = 0V VCTL2 = 2.7V fLO = fRF – 130MHz PLO = –15dBm 8 6 NF 4 2 800 900 820 fRF – RF frequency [MHz] 0 0 POUT – IF output power [dBm] POUT – IF output power [dBm] 20 POUT –20 –40 VDD = 2.7V VCTL1 = 2.7V VCTL2 = 0V fRF1 = 820MHz fRF2 = 820.1MHz fLO = 690MHz PLO = –15dBm IM3 –60 –20 –10 860 880 900 Path RFIN2 → IFOUT POUT, IM3 vs. PIN 20 –30 840 fRF – RF frequency [MHz] Path RFIN1 → IFOUT POUT, IM3 vs. PIN –80 –40 Gc POUT –20 –40 –60 –80 –40 0 PIN – RF input power [dBm] VDD = 2.7V VCTL1 = 0V VCTL2 = 2.7V fRF1 = 870MHz fRF2 = 870.1MHz fLO = 740MHz PLO = –15dBm IM3 –30 –20 –10 PIN – RF input power [dBm] –4– 0 CXG1050TN Path RFIN1 → IFOUT Gc, NF vs. PLO Path RFIN2 → IFOUT Gc, NF vs. PLO Gc 10 VDD = 2.7V VCTL1 = 2.7V VCTL2 = 0V fRF = 820MHz fLO = 690MHz 8 6 NF 4 –20 –15 –10 –5 IIP3 – Input IP3 [dBm] NF 4 –20 –15 –10 –5 PLO – LO input power [dBm] Path RFIN1 → IFOUT IIP3, PLK vs. PLO Path RFIN2 → IFOUT IIP3, PLK vs. PLO –25 VDD = 2.7V VCTL1 = 2.7V VCTL2 = 0V fRF = 820MHz fLO = 690MHz 1 –30 IIP3 0 –2 –25 6 PLO – LO input power [dBm] 2 –1 VDD = 2.7V VCTL1 = 0V VCTL2 = 2.7V fRF = 870MHz fLO = 740MHz 8 2 –25 0 –35 PLK –20 –40 –15 –10 –5 0 0 2 IIP3 – Input IP3 [dBm] 2 –25 Gc 10 –25 VDD = 2.7V VCTL1 = 0V VCTL2 = 2.7V fRF = 870MHz fLO = 740MHz 1 0 –2 –25 PLO – LO input power [dBm] –35 IIP3 PLK –1 –45 –20 –40 –15 –10 –5 PLO – LO input power [dBm] –5– –30 0 –45 PLK – LO leak power [dBm] Gc – Conversion gain, NF – Noise figure [dB] 12 PLK – LO leak power [dBm] Gc – Conversion gain, NF – Noise figure [dB] 12 CXG1050TN Example of Characteristics for Option Resistance R3 Changed (Ta = 25°C) IDD3 vs. R3 IDD3 – Mixer block current consumption [mA] 10 8 6 4 2 VDD = 2.7V VCTL1 = 2.7V, VCTL2 = 0V or VCTL1 = 0V, VCTL2 = 2.7V 0 OPEN 1.5k 820 470 270 R3 – Option resistance [Ω] Path RFIN1 → IFOUT Gc, NF vs. R3 Path RFIN2 → IFOUT Gc, NF vs. R3 12 Gc – Conversion gain, NF-Noise figure [dB] Gc VDD = 2.7V VCTL1 = 2.7V VCTL2 = 0V fRF = 820MHz fLO = 690MHz PLO = –15dBm 8 6 NF 4 2 OPEN 1.5k 820 470 270 R3 – Option resistance [Ω] 10 6 NF 4 –25 2 –30 IIP3 0 –35 –4 OPEN VDD = 2.7V VCTL1 = 2.7V VCTL2 = 0V fRF = 820MHz fLO = 690MHz PLO = –15dBm 1.5k 820 470 270 R3 – Option resistance [Ω] –40 IIP3 – Input IP3 [dBm] 4 –2 1.5k 820 470 270 R3 – Option resistance [Ω] 150 Path RFIN2 → IFOUT IIP3, PLK vs. R3 PLK – LO leak power [dBm] IIP3 – Input IP3 [dBm] Path RFIN1 → IFOUT IIP3, PLK vs. R3 PLK VDD = 2.7V VCTL1 = 0V VCTL2 = 2.7V fRF = 870MHz fLO = 740MHz PLO = –15dBm 8 2 OPEN 150 Gc 4 –25 2 –30 IIP3 0 PLK –2 –4 OPEN –45 150 –6– –35 VDD = 2.7V VCTL1 = 0V VCTL2 = 2.7V fRF = 870MHz fLO = 740MHz PLO = –15dBm 1.5k 820 470 270 R3 – Option resistance [Ω] –40 –45 150 PLK – LO leak power [dBm] Gc – Conversion gain, NF-Noise figure [dB] 12 10 150 CXG1050TN Recommended Evaluation Board Front 25mm SONY CXG1050TN EVB RFIN1 L7 L9 L6 L8 C13 R1 RFIN2 C14 L5 C12 C11 L4 C9 C7 R2 C10 C8 C5 C6 C1 R3 L1 IFOUT L2 C4 L3 C3 LOIN C2 CTL1 VDD3 GND CTL2 VDD1/2 GND VDD1/2 CTL2 VDD3 CTL1 Back Glass fabric-base 4-layer epoxy board (thickness: 0.3mm × 2) GND for the 2nd and 3rd layers –7– CXG1050TN Package Outline Unit: mm 16PIN TSSOP(PLASTIC) 1.2MAX 4.1 S 2.05 A 16 B 0.08 S X2 9 0.2 S A B 3.9 (3.0) 0.1 ± 0.05 0.25 0.1 2.9 0.1 X X 8 X4 0.1 0.5 S A B 0.45 ± 0.1 1 0° to 8° 0.08 M S A 0.2 ± 0.02 + 0.036 0.22 – 0.03 DETAIL B 0.1 ± 0.01 + 0.026 0.12 – 0.02 B PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT SOLDER PLATING EIAJ CODE LEAD MATERIAL COPPER ALLOY JEDEC CODE PACKAGE MASS 0.03g SONY CODE TSSOP-16P-L01 –8–