CXG7001FN Power Amplifier/Antenna Switch + Low Noise Down Conversion Mixer for PHS Description The CXG7001FN is a MMIC consisting of the power amplifier, antenna switch and low noise down conversion mixer. This IC is designed using the Sony’s GaAs J-FET process featuring a single positive power supply operation. Features • Operates at a single positive power supply: VDD = 3V • Small mold package: 26-pin HSOF <Power amplifier/antenna switch transmitter block > • Low current consumption: IDD = 150mA (POUT = 20.2dBm, f = 1.9GHz) • High power gain: Gp = 39dB Typ. (POUT = 20.2dBm, f = 1.9GHz) <Antenna switch receiver block/ low noise down conversion mixer> • Low current consumption: IDD = 5.5mA Typ. (When no signal) • High conversion gain: Gc = 20.5dB Typ. (f = 1.9GHz) • Low distortion: Input IP3 = –13dBm Typ. (f = 1.9GHz) • High image suppression ratio: IMR = 40dBc Typ. (f = 1.9GHz) • High 1/2 IF suppression ratio: 1/2IFR = 44dBc Typ. (f = 1.9GHz) Applications Japan digital cordless telephones (PHS) 26 pin HSOF (Plastic) Absolute Maximum Ratings <Power amplifier block> • Supply voltage VDD • Voltage between gate and source VGSO • Gain control voltage VPCTL • Drain current IDD • Allowable power dissipation PD 6 1.5 2.5 550 V V mA 3 W V <Switch block> Control voltage VCTL 6 <Front-end block> • Supply voltage • Input power VDD PRF 6 +10 <Common to each block> • Channel temperature Tch • Operating temperature Topr • Storage temperature Tstg V V dBm 150 –35 to +85 –65 to +150 °C °C °C Recommended Operating Conditions Structure GaAs J-FET MMIC <Common to each block> • Supply voltage VDD 2.7 to 3.3 V <Power amplifier block> • Gain control voltage VPCTL to VDD–1.0 V VCTL (H) 2.9 to 3.3 VCTL (L) 0 to 0.2 V V <Switch block> • Control voltage (H) • Control voltage (L) Notes on Handling GaAs MMICs are ESD sensitive devices. Special handling precautions are required. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E04139-PS CXG7001FN Block Diagram and External Circuit 2.2nH PIN 14 13 15 12 (VGG1) 1kΩ VPCTL 100pF VDD1 1nF 18nH 1nF 18nH 10nF 1.8nH 16 11 17 10 VGG2 1nF 2.2nH VDD2 VDD3 (POUT) 1pF 30pF 18 9 (TX) 30pF 19 VCTL1 8 100pF ANT 7 20 (RX) 30pF 30pF VCTL2 21 6 22 5 23 4 100pF (RFIN) 10nH 10pF 3.9nH 6.8nH 13pF 24 3 25 2 100nF VDD (IF AMP, MIX) 26 1 PIN 14 13 VGG1 82nH 1nF 5pF IFOUT Pin Configuration GND 15 12 VPCTL VDD1 16 11 VGG2 VDD2 17 10 POUT VDD3 18 9 Tx GND 19 8 VCTL1 RX 20 7 ANT VCTL2 21 6 GND RFIN 22 5 GND CAP 23 4 VDD (RF AMP) GND 24 3 GND CAP 25 2 VDD (LO AMP) IFOUT/VDD (IF AMP, MIX) 26 1 LOIN 26 pin – HSOF (Plastic) –2– 13pF 1nF 18pF 1nF VDD (RF AMP) VDD (LO AMP) LOIN CXG7001FN Pin Description Pin No. Description Symbol 1 LOIN LO signal input. 2 VDD (LO AMP) LO AMP VDD. 3 GND 4 VDD (RF AMP) RF AMP VDD. 5 GND GND. 6 GND GND. 7 ANT Antenna switch. Either ANT-Tx or ANT-Rx is depending on whether the setting is VCTL1 or VCTL 2. 8 VCTL1 Antenna switch control Pin 1. 9 TX Tx. Input the signal into the antenna switch when ANT-Tx. 10 POUT Power amplifier output. 11 VGG2 Power amplifier (the final-stage FET) gate voltage adjustment Pin 2. 12 VPCTL The first-stage FET control pin for the power amplifier. 13 VGG1 Power amplifier (the first-stage FET, the second-stage FET) gate voltage adjustment Pin 1. 14 PIN Signal input into the power amplifier. 15 GND GND. 16 VDD1 Power amplifier (the first-stage FET) VDD1. 17 VDD2 Power amplifier (the second-stage FET) VDD2. 18 VDD3 Power amplifier (the final-stage FET) VDD3. 19 GND GND. 20 RX Rx. Output ANT input signal into Rx when ANT-Rx. 21 VCTL2 Antenna switch control Pin 2. 22 RFIN RF signal input. 23 CAP Connector for the external capacitor. Connected to LNA FET source. Self-vibration frequency becomes 1.9GHz by this capacitor (Typ. 13pF). 24 GND GND. 25 CAP Connector for the external capacitor. IF AMP distortion is corrected by this capacitor. 26 IFOUT/VDD (IF AMP, MIX) IF output and IF AMP, MIX VDD. GND. –3– CXG7001FN Electrical Characteristics 1. Control Pin Logic for Antenna Switch Conditions of control pins ANT – TX ANT – RX VCTL1 = 3V, VCTL2 = 0V ON OFF VCTL1 = 0V, VCTL2 = 3V OFF ON 2. Power Amplifier Block + Antenna Switch Transmitter Block These specifications are those when the Sony's recommended evaluation board, shown on page 7, is used. Unless otherwise specified: VDD = 3V, VPCTL = 2V, VCTL1 = 3V, VCTL2 = 0V, IDD = 150mA, POUT = 20.2dBm, f = 1.9GHz, Ta = 25°C Item Symbol Measurement conditions Min. Typ. Max. Unit Current consumption IDD 150 mA Gate voltage adjustment value VGG 0.04 0.25 0.60 V Output power POUT Power gain GP Adjacent channel leak power ratio (600 ± 100kHz) ACPR600kHz Adjacent channel leak power ratio (900 ± 100kHz) Occupied bandwidth Measured with the ANT pin 20.2 36 dBm 39 dB Measured with the ANT pin –63 –55 dBc ACPR900kHz Measured with the ANT pin –70 –60 dBc OBW Measured with the ANT pin 250 275 kHz 2nd-order harmonic level — Measured with the ANT pin –25 dBc 3rd-order harmonic level — Measured with the ANT pin –25 dBc 3. Antenna Switch Receiver Block + Low Noise Down Conversion Mixer Block These specifications are those when the Sony's recommended evaluation board, shown on page 7, is used. Unless otherwise specified: VDD = 3V, VCTL1 = 0V, VCTL2 = 3V, RF1 = 1.90GHz/–35dBm, LO = 1.66GHz/–15dBm, Ta = 25°C Item Symbol Measurement conditions Min. Typ. Max. Unit Current consumption IDD When no signal 5.5 Conversion gain GC When a small signal Noise figure NF Input IP3 IIP3 When a small signal ∗1 Image suppression ratio IMR RF2 = 1.42GHz/–35dBm 30 40 dBc 1/2 IF suppression ratio 1/2IFR RF2 = 1.78GHz/–35dBm 39 44 dBc 17 7.5 20.5 4.2 –17.5 –13 mA dB 5.5 dB dBm 2 × LO–IF suppression ratio — RF2 = 3.08GHz/–35dBm 39 47 dBc 2 × LO+IF suppression ratio — RF2 = 3.56GHz/–35dBm 24 62 dBc –42 –37 dBm LO to ANT leak PLK ∗1 Conversion from IM3 suppression ratio during FR1 = 1.9000GHz/–35dBm and FR2 = 1.9006GHz/–35dBm input. –4– CXG7001FN Example of Representative Characteristics 20 –45 POUT 15 –50 10 –55 5 –60 ACPR600kHz 0 –35 –30 –25 –20 –15 –70 –10 –45 35 –50 30 –55 25 –60 ACPR600kHz 20 –65 15 0 0.5 1.0 1.5 2.0 2.5 VPCTL – Gain control voltage [V] POUT, ACPR600kHz vs. VDD Gp, ACPR600kHz vs. IDD –45 22 POUT – Output power [dBm] GP PIN – Input power [dBm] VDD = var., VPCTL = 2V, VGG = const., VCTL1 = 3V, VCTL2 = 0V IDD = 150mA (@VDD = 3V, POUT = 20.2dBm), PIN = –19.3dBm 23 –40 POUT 21 –50 20 –55 ACPR600kHz 19 –60 –65 18 17 2.0 –40 40 2.5 3.0 3.5 4.0 4.5 –70 5.0 –70 3.0 VDD = 3V, VPCTL = 2V, VGG = var., VCTL1 = 3V, VCTL2 = 0V IDD = var., PIN = var., POUT = 20.2dBm Gp – Power gain [dB] –5 –40 –65 45 42 –40 41 –45 GP 40 –50 39 –55 ACPR600kHz 38 –60 37 –65 36 100 VDD – Supply voltage [V] 120 140 160 180 200 IDD – Current consumption [mA] –5– –70 220 ACPR600kHz – Adjacent channel leak power ratio [dBc] –40 Gp – Power gain [dB] 25 ACPR600kHz – Adjacent channel leak power ratio [dBc] Gp, ACPR600kHz vs. VPCTL VDD = 3V, VPCTL = var., VGG = const., VCTL1 = 3V, VCTL2 = 0V IDD = 150mA (@VPCTL = 2V), PIN = var., POUT = 20.2dBm ACPR600kHz – Adjacent channel leak power ratio [dBc] POUT, ACPR600kHz vs. PIN VDD = 3V, VPCTL = 2V, VGG = const., VCTL1 = 3V, VCTL2 = 0V IDD = 150mA (@POUT = 20.2dBm), PIN = var. ACPR600kHz – Adjacent channel leak power ratio [dBc] POUT – Output power [dBm] 1. Power Amplifier + Antenna Switch Transmitter Block (f = 1.9GHz, Ta = 25°C) CXG7001FN 2. Antenna Switch Receiver Block + Low Noise Down Conversion Mixer (Ta = 25°C) GC, NF vs. PLO POUT, PIM3 vs. PIN 22 5.50 5.25 GC 20 5.00 19 4.75 18 4.50 NF – Noise figure [dB] GC – Convertion gain [dB] 21 NF 17 4.25 16 –25 4.00 –20 –15 –10 –5 0 PLO – Local input [dBm] Input IP3, PLK vs. PLO –10 Input IP3 [dBm] Input IP3 –12 –35 –14 –40 –16 –45 PLK –18 –50 –20 –55 PLK – LO to ANT leak level [dBm] –30 –60 –20 –15 –10 VDD = 3V, VCTL1 = 0V, VCTL2 = 3V, RF1 = 1.9000GHz, RF2 = 1.9006GHz, LO = 1.66GHz/–15dBm 20 0 POUT –20 –40 PIM3 –60 –80 Input IP3 –100 –50 –40 –30 –20 –10 PIN – RF input power [dBm] VDD = 3V, VCTL1 = 0V, VCTL2 = 3V, RF = 1.90GHz/–35dBm, LO = 1.66GHz –22 –25 POUT – IF output power, PIM3 – 3rd-order intermodulation distortion power [dBm] VDD = 3V, VCTL1 = 0V, VCTL2 = 3V, RF = 1.90GHz/small signal, LO = 1.66GHz –5 0 PLO – Local input [dBm] –6– 0 CXG7001FN Recommended Evaluation Board Via Hole VGG PAIN VPCTL VDD_PA VCTL1 VCTL2 ANT VDD_LNA VDD_LO IFOUT LOIN VDD_IF Via Hole Glass fabric-base epoxy board (4 layers) Thickness between 1 and 2: 0.2mm Dimensions: 50mm × 50mm VCTL2 VDD (PA) VCTL1 VDD (LO) VDD (IF) VPCTL VGG VDD (LNA) Enlarged Diagram of External Circuit Block R1 R1 = 1k C8 C8 L1 = 1.8nH L2 = 2.2nH L3 = 3.9nH C7 L2 L6 C8 L6 C9 L1 C1 L2 C6 C6 C6 C7 C6 C3 L3 C7 C4 L5 C4 L4 L4 = 6.8nH L5 = 10nH L6 = 18nH L7 = 82nH C10 C5 C2 C8 L7 C8 –7– C8 C1 = 1pF C2 = 5pF C3 = 10pF C4 = 13pF C5 = 18pF C6 = 30pF C7 = 100pF C8 = 1nF C9 = 10nF C10 = 100nF CXG7001FN Package Outline Unit: mm HSOF 26PIN (PLASTIC) 0.08 ∗5.6 ± 0.05 0.45 ± 0.15 0.9 ± 0.1 S 5.5 4.2 A 0.4 0.5 (1.5) (0.7) 4.4 ± 0.1 (1.75) 14 3.8 ± 0.05 26 13 1 0.4 S 4.4 0.2 0.2 0.07 M S A (0.2) 0.2 ± 0.05 + 0.05 0.2 0 Solder Plating B + 0.05 0.14 – 0.03 NOTE: Dimension “ ∗” does not include mold protrusion. DETAIL B PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT SOLDER PLATING EIAJ CODE LEAD MATERIAL COPPER ALLOY JEDEC CODE PACKAGE MASS 0.06g HSOF-26P-01 SONY CODE LEAD PLATING SPECIFICATIONS ITEM SPEC. LEAD MATERIAL COPPER ALLOY SOLDER COMPOSITION Sn-Bi Bi:1-4wt% PLATING THICKNESS 5-18µm –8– Sony Corporation