CXP81952/81960 CMOS 8-bit Single Chip Microcomputer Description The CXP81952/81960 is a CMOS 8-bit microcomputer which consists of A/D converter, serial interface, timer/counter, time base timer, vector interruption, high precision timing pattern generation circuit, PWM generator, PWM for tuner, 32kHz timer/event counter, remote control receiving circuit, general purpose prescaler, and external signal, as well as basic configurations like 8-bit CPU, ROM, RAM and I/O port. They are integrated into a single chip. Also the CXP81952/81960 provides sleep/stop function which enables to lower power consumption and ultra-low speed instruction mode in 32kHz operation. 100 pin QFP (PIastic) 100 pin LQFP (PIastic) Structure Silicon gate CMOS IC Features • A wide instruction set (213 instructions) which cover various types of data — 16-bit operation/multiplication and division/boolean bit operation instructions • Minimum instruction cycle 250ns at 16MHz operation 122µs at 32kHz operation • Incorporated ROM capacity 52K bytes (CXP81952), 60K bytes (CXP81960) • Incorporated RAM capacity 2048 bytes • Peripheral functions — A/D converter 8-bit, 12-channel, successive approximation system (Conversion time 20.0µs/16MHz) — Serial Interface Incorporated buffer RAM (1 to 32 bytes auto transfer) 1-channel Incorporated 8-bit and 8-stage FIFO for data (1 to 8 bytes auto transfer) 1-channel — Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer, 32kHz timer/counter — High precision timing pattern generator PPG 19-pin 32-stage programmable RTG 5-pin 2-channel — PWM/DA gate output PWM 12-bit, 2-channel (Repetitive frequency 62kHz/16MHz) DA gate pulse output 13-bit, 4-channel — FRC capture unit Incorporated 26-bit and 8-stage FIFO — PWM output 14-bit, 1-channel — Remote control receiving circuit 8-bit pulse measurement counter with on-chip, 6-stage FIFO — General purpose prescaler 7-bit (PG5 input frequency divided, FRC capture possible) • Interruption 20 factors, 15 vectors, multi-interruption possible • Standby mode SLEEP/STOP • Package 100-pin plastic QFP/LQFP • Piggyback/evaluation chip CXP81900 100-pin ceramic QFP/LQFP Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E95110-ST AVDD PG5/PCK PE2/PWM0 PE4/DAA0 PE6/DAB0 PE3/PWM1 PE5/DAA1 PE7/DAB1 PROGRAMMABLE PRESCALER 12 BIT PWM GENERATOR CH1 12 BIT PWM GENERATOR CH0 14 BIT PWM GENERATOR PI2/PWM FIFO REMOCON INPUT PI1/RMC PG6/EXI0 PG7/EXI1 8 BIT TIMER 1 FIFO RAM PI3/TO SERIAL INTERFACE UNIT (CH1) SERIAL INTERFACE UNIT (CH0) A/D CONVERTER 2 2 4 2 2 PE0/INT0 NMI PE1/INT2 CH0 1 CH REALTIME PULSE GENERATOR 5 2 32kHz TIMER/COUNTER PRESCALER/ TIME BASE TIMER RAM 2048 BYTES CLOCK GENERATOR/ SYSTEM CONTROL AA 19 RAM PROGRAMMABLE PATTERN GENERATOR ROM 52K/60K BYTES SPC700 CPU CORE FIFO PI4/INT1/NMI FRC CAPTURE UNIT INTERRUPT CONTROLLER AVREF 8 BIT TIMER/COUNTER 0 12 AVss PE1/EC PI5/SCK1 PI7/SI1 PI6/SO1 CS0 SI0 SO0 SCK0 AN0 to AN3 PF0/AN4 to PF7/AN11 PA0/PPO0 to PC2/PPO18 PB0 to PB7 PC0 to PC7 8 8 8 PG0 to PG7 8 8 PF4 to PF7 4 7 PF0 to PF3 4 PJ0 to PJ7 PI1 to PI7 PH0 to PH7 PE2 to PE7 6 8 PE0 to PE1 2 PD0 to PD7 PA0 to PA7 8 PORT B TEX TX EXTAL XTAL RST MP VDD PC3/RTO3 to PC7/RTO7 PORT A PORT C PORT D PORT E PORT F PORT G PORT H PORT I –2– PORT J Block Diagram CXP81952/81960 Vss CXP81952/81960 PI5/SCK1 PI4/INT1/NMI PI3/TO/ADJ PI2/PWM PI1/RMC TEX TX VDD VSS NC PA7/PPO7 PA6/PPO6 PA5/PPO5 PA4/PPO4 PA3/PPO3 PA2/PPO2 PA1/PPO1 PA0/PPO0 PB7/PPO15 PB6/PPO14 Pin Configuration 1 (Top View) 100-pin QFP package 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PB5/PPO13 1 80 PI6/SO1 PB4/PPO12 2 79 PI7/SI1 PB3/PPO11 3 78 PE0/INT0 PB2/PPO10 4 77 PE1/EC/INT2 PB1/PPO9 5 76 PE2/PWM0 PB0/PPO8 6 75 PE3/PWM1 PC7/RTO7 7 74 PE4/DAA0 PC6/RTO6 8 73 PE5/DAA1 PC5/RTO5 9 72 PE6/DAB0 PC4/RTO4 10 71 PE7/DAB1 PC3/RTO3 11 70 PG0 PC2/PPO18 12 69 PG1 PC1/PPO17 13 68 PG2 PC0/PPO16 14 67 PG3 PJ7 15 66 PG4 PJ6 16 65 PG5/PCK PJ5 17 64 PG6/EXI0 PJ4 18 63 PG7/EXI1 PJ3 19 62 AN0 PJ2 20 61 AN1 PJ1 21 60 AN2 PJ0 22 59 AN3 PD7 23 58 PF0/AN4 PD6 24 57 PF1/AN5 PD5 25 56 PF2/AN6 PD4 26 55 PF3/AN7 PD3 27 54 AVDD PD2 28 53 AVREF PD1 29 52 AVSS PD0 30 51 PF4/AN8 PF5/AN9 PF6/AN10 PF7/AN11 SCK0 SO0 SI0 CS0 EXTAL XTAL VSS RST MP PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note) 1. NC (Pin 90) is always connected to VDD. 2. Vss (Pins 41 and 88) are both connected to GND. –3– CXP81952/81960 PE0/INT0 PI7/SI1 PI6/SO1 PI5/SCK1 PI4/INT1/NMI PI3/TO/ADJ PI2/PWM PI1/RMC TEX TX VDD VSS NC PA7/PPO7 PA6/PPO6 PA5/PPO5 PA4/PPO4 PA3/PPO3 PA2/PPO2 PA1/PPO1 PA0/PPO0 PB7/PPO15 PB6/PPO14 PB5/PPO13 PB4/PPO12 Pin Configuration 2 (Top View) 100-pin LQFP package 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PB3/PPO11 1 75 PE1/EC/INT2 PB2/PPO10 2 74 PE2/PWM0 PB1/PPO9 3 73 PE3/PWM1 PB0/PPO8 4 72 PE4/DAA0 PC7/RTO7 5 71 PE5/DAA1 PC6/RTO6 6 70 PE6/DAB0 PC5/RTO5 7 69 PE7/DAB1 PC4/RTO4 8 68 PG0 PC3/RTO3 9 67 PG1 PC2/PPO18 10 66 PG2 PC1/PPO17 11 65 PG3 PC0/PPO16 12 64 PG4 PJ7 13 63 PG5/PCK PJ6 14 62 PG6/EXI0 PJ5 15 61 PG7/EXI1 PJ4 16 60 AN0 PJ3 17 59 AN1 PJ2 18 58 AN2 PJ1 19 57 AN3 PJ0 20 56 PF0/AN4 PD7 21 55 PF1/AN5 PD6 22 54 PF2/AN6 PD5 23 53 PF3/AN7 PD4 24 52 AVDD PD3 25 51 AVREF Note) 1. NC (Pin 88) is always connected to VDD. 2. Vss (Pins 39 and 86) are both connected to GND. –4– AVSS PF4/AN8 PF5/AN9 PF6/AN10 PF7/AN11 SCK0 SO0 SI0 CS0 XTAL EXTAL VSS RST MP PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 PD0 PD1 PD2 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CXP81952/81960 Pin Description Symbol I/O Description PA0/PPO0 to PA7/PPO7 Output/ Real time output (Port A) 8-bit output port. Data is gated with PPO contents by OR-gate and they are output. (8 pins) PB0/PPO8 to PB7/PPO15 Output/ Real time output (Port B) 8-bit output port. Data is gated with PPO contents by OR-gate and they are output. (8 pins) PC0/PPO16 to PC2/PPO18 I/O/ Real time output PC3/RTO3 to PC7/RTO7 I/O/ Real time output (Port C) 8-bit I/O port, enables to specify I/O by bit unit. Data is gated with PPO or RTO contents by OR-gate and they are output. (8 pins) Programmable pattern generator (PPG) output. Functions as high precision real time pulse output port. (19 pins) Real time pulse generator (RTG) output. Functions as high precision real time pulse output port. (5 pins) (Port D) 8-bit I/O port. Enable to specify I/O by 4-bit unit. Enables to drive 12mA sink current. (8 pins) PD0 to PD7 I/O PE0/INT0 Input/Input PE1/EC/INT2 Input/Input/Input PE2/PWM0 Output/Output PE3/PWM1 Output/Output PE4/DAA0 Output/Output PE5/DAA1 Output/Output PE6/DAB0 Output/Output PE7/DAB1 Output/Output AN0 to AN3 Input Analog input pins to A/D converter. (12 pins) PF0/AN4 to PF3/AN7 Input/Input PF4/AN8 to PF7/AN11 Output/Input (Port F) Lower 4 bits are input port and upper 4 bits are output port. Lower 4 bits also serve as standby release input pin. (8 pins) SCK0 I/O Serial clock (CH0) I/O pin. SO0 Ouput Serial data (CH0) output pin. SI0 Input Serial data (CH0) input pin. CS0 Input Serial chip select (CH0) input pin. Input pin to request external interruption. Active when falling edge. (Port E) 8-bit port. Lower 2 bits are input pins and upper 6 bits are output pins. (8 pins) External event input pin for timer/counter. Input pin to request external interruption. Active when falling edge. PWM output pins. (2 pins) DA gate pulse output pins. (4 pins) –5– CXP81952/81960 Symbol I/O Description PG0 to PG4 PG5/PCK PG6/EXI0 Input (Port G) 8-bit input port. (8 pins) 7 bit general purpose prescaler input pin. External input pin to FRC capture unit. PG7/EXI1 (Port H) 8-bit output port ; Medium withstand voltage (12V) and high current (12mA), N-ch open drain output. (8 pins) PH0 to PH7 Output PI1/RMC I/O/Input Remote control receiving circuit input pin. PI2/PWM I/O/Output 14-bit PWM output pin. PI3/TO/ADJ I/O/Output/Output PI4/INT1/ NMI I/O/Input/Input PI5/SCK1 I/O/I/O PI6/SO1 I/O/Output Serial data (CH1) output pin. PI7/SI1 I/O/Input Serial data (CH1) input pin. PJ0 to PJ7 I/O EXTAL Input XTAL Output TEX Input TX Output Connecting pin of crystal oscillator for 32kHz timer clock. When used as event counter, input to TEX pin and leave TX pin open. (Feedback resistor is not removed.) RST Input System reset pin of active "L" level. MP Input Microprocessor mode input pin. Always connect to GND. Timer/counter, 32kHz oscillation adjustment output pin. Input pin to request external interruption and non-maskable interruption. Active when falling edge. Serial clock (CH1) I/O pin. (Port J) 8-bit I/O port. Function as standby release input can be specified by bit unit. I/O can be specified by bit unit. Connecting pin of crystal oscillator for system clock. When supplying the external clock, input the external clock to EXTAL pin and input opposite phase clock to XTAL pin. Positive power supply pin of A/D converter. AVDD AVREF (Port I) 7-bit I/O port. I/O port can be specified by bit unit. (7 pins) Input Reference voltage input pin of A/D converter. AVss GND pin of A/D converter. VDD Positive power supply pin. Vss GND pin. Connect both Vss pins to GND. –6– CXP81952/81960 Input/Output Circuit Formats for Pins Pin When reset Circuit format Port A AA AA Port B PA0/PPO0 to PA7/PPO7 PB0/PPO8 to PB7/PPO15 AAAA AAAA PPO data Port A or Port B Hi-Z Output becomes active from high impedance by data writing to port register. Data bus RD 16 pins Port C PC0/PPO16 to PC2/PPO18 AAAA AAAA AAAA PPO, RTO data Input protection circuit Port C data PC3/RTO3 to PC7/RTO7 AA AA AA AA Hi-Z IP Port C direction (Every bit) Data bus RD (Port C) 8 pins Port D PD0 to PD7 AAAA AAAA AAAA AA AA AA AA High current 12mA Port D data IP Port D direction (Every 4 bits) PD0 to 3 PD4 to 7 Data bus RD (Port D) 8 pins –7– Hi-Z CXP81952/81960 Pin Port E PE0/INT0 Interruption circuit 1 pin Port E PE1/EC/INT2 AAAA AA Hi-Z AAAA AA Hi-Z IP Data bus RD Data bus Input protection circuit IP RD (Port E) 1 pin When reset Circuit format Input protection circuit Interruption circuit/ event counter AA AA AAAA AA AAAA AA AAAA AAAA Port E DA gate output or PWM output PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 MPX Hi-Z control Port E data AA AA Hi-Z Port/DA output select Data bus RD (Port E) 4 pins Port E AAA AAA AAAA AAA AAAA AAAA DA gate output MPX Hi-Z control PE6/DAB0 PE7/DAB1 Port E data Port/DA output select Data bus 2 pins RD (Port E) –8– AA AA H level CXP81952/81960 Pin When reset Circuit format AA AA AAAA AA AA AAAA Input multiplexer AN0 to AN3 IP 4 pins Port F Hi-Z A/D converter Input multiplexer PF0/AN4 to PF3/AN7 IP A/D converter Hi-Z Data bus 4 pins RD (Port F) AAAA AAAA AAAA AA AA A Port F PF4/AN8 to PF7/AN11 Port F data Data bus RD (Port F) 4 pins Port G PG0 to PG4 IP Port/AD select AAA AA 6 pins Port G A/D converter Input multiplexer Schmitt input IP PG5/PCK Hi-Z Data bus Hi-Z RD (Port G) PG5: To general purpose prescaler AAA AA Schmitt input PG6/EXI0 PG7/EXI1 FRC capture unit IP 2 pins RD (Port G) AA AA Port H PH0 to PH7 Medium withstand voltage 12V AAA AAA Port H data Data bus 8 pins Hi-Z Data bus Large current 12mA RD (Port H) –9– Hi-Z CXP81952/81960 Pin AAAA AAAAAAA AAA AAAA AAA AAAA AAA AAAA When reset Circuit format Port I Port I function select AA AA AA AA PI2: From 14-bit PWM PI3: From timer/counter, 32kHz timer PI2/PWM PI3/TO/ADJ MPX Port I data Port I direction Data bus 2 pins IP RD (Port I) Port I AAAA AAAA AAAA AA AA AA AA Port I data PI1/RMC PI4/INT1/NMI PI7/SI1 Port I direction IP Data bus RD (Port I) 3 pins Hi-Z Hi-Z Schmitt input PI1: To remote control circuit PI4: To interruption circuit PI7: To serial CH1 AAAA AAAA AAA AAAA AAA AA AAAA AAA AA AAAA AA AA Port I Port I function select PI5/SCK1 PI6/SO1 From serial CH1 MPX Port I data MPX Port I direction Data bus 2 pins RD (Port I) IP Note) PI5 is schmitt input PI6 is inverter input To serial CH1 – 10 – AA A Hi-Z CXP81952/81960 Pin AAAA AAAA AAAA AAAA AA AA AAAA AA Circuit format Port J AA AA AA Port J data Port J direction PJ0 to PJ7 IP Data bus RD (Port J) Standby release 8 pins Edge detection When reset Hi-Z Data bus RD CS0 SI0 Schmitt input IP 2 pins SO0 SO0 from SIO 1 pin SO0 output enable Internal serial clock from SIO SCK0 External serial clock to SIO Hi-Z Hi-Z Schmitt input 1 pin 2 pins AA AA AA AA AA AA IP SCK0 output enable EXTAL XTAL Hi-Z To SIO AA AA AA AA EXTAL IP XTAL – 11 – • Shows the circuit composition during oscillation. Oscillation • Feedback resistor is removed during stop. CXP81952/81960 Pin TEX TX 2 pins RST When reset Circuit format AA AA AA AA AA AA TEX 32kHz timer counter IP TX • Shows the circuit composition during oscillation. • Feedback resistor is removed during 32kHz oscillation circuit stop by software. At this time TEX pin outputs "L" level and TX pin outputs "H" level. Oscillation Pull-up resistor Mask option AA A AA AA AAAA Schmitt input L level OP IP 1 pin MP IP 1 pin – 12 – CPU mode Hi-Z CXP81952/81960 Absolute Maximum Ratings Item (Vss = 0V) Symbol Rating Unit –0.3 to +7.0 AVss to +7.0∗1 V V VIN –0.3 to +0.3 –0.3 to +7.0∗2 Output voltage VOUT –0.3 to +7.0∗2 V Medium withstand output voltage VOUTP –0.3 to +15.0 V High level output current IOH –5 mA High level total output current ∑IOH –50 mA Total of output pins IOL 15 mA IOLC 20 mA Other than large current output pins: per pin Large current port pin∗3: per pin Low level total output current ∑IOL 130 mA Total of output pins Operating temperature Topr –20 to +75 °C Storage temperature Tstg –55 to +150 °C Allowable power dissipation PD VDD Supply voltage AVDD AVSS Input voltage Low level output current V V 600 380 Remarks mW PH pin QFP package type LQFP package type ∗1 AVDD and VDD should be set to a same voltage. ∗2 VIN and VOUT should not exceed VDD + 0.3V. ∗3 The large current operation transistors are the N-CH transistors of the PD and PH ports. Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should better take place under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI. – 13 – CXP81952/81960 Recommended Operating Conditions Item Supply voltage Analog power supply High level input voltage Symbol Min. Max. Unit Remarks 3.0 5.5 V Guaranteed range during high speed mode (1/2 dividing clock) operation 2.7 5.5 V Guaranteed range during low speed mode (1/16 dividing clock) operation 2.7 5.5 V Guaranteed operation range by TEX clock 2.0 5.5 V 3.0 5.5 V Guaranteed data hold operation range during STOP ∗1 VIH 0.7VDD VDD V ∗2 VIHS 0.8VDD VDD V 5.5 V VDD AVDD VIHEX VIL Low level input voltage VILS VILEX Operating temperature Topr ∗1 ∗2 ∗3 ∗4 ∗5 ∗6 ∗7 ∗8 (Vss = 0V) CMOS schmitt input∗3 and PE0/INT0 pin CMOS schmitt input∗6 VDD – 0.4 VDD + 0.3 V VDD – 0.2 VDD + 0.2 V EXTAL pin∗4, ∗7 and TEX pin∗5, ∗7 EXTAL pin∗4, ∗8 and TEX pin∗5, ∗8 0 0.3VDD V ∗2, ∗7 0 0.2VDD V ∗2, ∗8 0 0.2VDD V –0.3 0.4 V CMOS schmitt input∗3 and PE0/INT0 pin EXTAL pin∗4, ∗7 and TEX pin∗5, ∗7 –0.3 0.2 V EXTAL pin∗4, ∗8 and TEX pin∗5, ∗8 –20 +75 °C AVDD and VDD should be set to a same voltage. Normal input port (each pin of PC, PD, PF0 to PF3, PG, PI and PJ), MP pin. Each pin of SCK0, RST, PE1/EC/INT2, PI1/RMC, PI4/INT1/NMI, PI5/SCK1 and PI7/SI1. It specifies only when the external clock is input. It specifies only when the external event count clock is input. Each pin of CS0, SI0, and PG. In case of 4.5 to 5.5V supply voltage (VDD). In case of 3.0 to 3.6V supply voltage (VDD). – 14 – CXP81952/81960 Electrical Characteristics DC Characteristics (VDD = 4.5 to 5.5V) Item High level output voltage Low level output voltage Symbol VOH VOL Pins Input current Min. Typ. Max. Unit VDD = 4.5V, IOH = –0.5mA 4.0 V VDD = 4.5V, IOH = –1.2mA 3.5 V PD, PH EXTAL IIHT IILT Conditions PA to PD, PE2 to PE7, PF4 to PF7, PH (VOL only) PI1 to PI7 PJ, SO0, SCK0 IIHE IILE (Ta = –20 to +75°C, Vss = 0V) TEX VDD = 4.5V, IOL = 1.8mA 0.4 V VDD = 4.5V, IOL = 3.6mA 0.6 V VDD = 4.5V, IOL = 12.0mA 1.5 V VDD = 5.5V, VIH = 5.5V 0.5 40 µA VDD = 5.5V, VIL = 0.4V –0.5 –40 µA VDD = 5.5V, VIH = 5.5V 0.1 10 µA –0.1 –10 µA –1.5 –400 µA IILR RST∗1 VDD = 5.5V, VIL = 0.4V I/O leakage current IIZ PA to PG, PI, PJ, MP AN0 to AN3, CS0, SI0, SO0 SCK0, RST∗1 VDD = 5.5V, VI = 0, 5.5V ±10 µA Open drain output leakage current (N-CH Tr OFF in state) ILOH PH VDD = 5.5V VOH = 12V 50 µA 31 50 mA 2.0 8 mA 46 110 µA 9 35 µA 10 µA 20 pF 16MHz crystal oscillation (C1 = C2 = 15pF) IDD1 VDD = 5V ± 0.5V∗3 SLEEP mode IDDS1 VDD = 5V ± 0.5V Supply current∗2 IDD2 IDDS2 32kHz crystal oscillation (C1 = C2 = 47pF) VDD VDD = 3V ± 0.3V SLEEP mode VDD = 3V ± 0.3V IDDS3 STOP mode (EXTAL and TEX pins oscillation stop) VDD = 5V ± 0.5V Input capacity CIN Other than VDD, Clock 1MHz Vss, AVDD, and 0V other than the measured pins AVss 10 ∗1 RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current when non-resistor is selected. ∗2 When entire output pins are open. ∗3 When setting upper 2 bits (CPU clock selection) of clock control register CLC (address: 00FEH) to "00" and operating in high speed mode (1/2 dividing clock). – 15 – CXP81952/81960 DC Characteristics (VDD = 3.0 to 3.6V) Item High level output voltage Low level output voltage Symbol VOH VOL (Ta = –20 to +75°C, Vss = 0V) Pins PA to PD, PE2 to PE7, PF4 to PF7, PH (VOL only) PI1 to PI7 PJ, SO0, SCK0 PD, PH IIHE Conditions Min. Typ. Max. Unit VDD = 3.0V, IOH = –0.15mA 2.7 V VDD = 3.0V, IOH = 0.5mA 2.3 V VDD = 3.0V, IOL = 1.2mA 0.3 V VDD = 3.0V, IOL = 1.6mA 0.5 V VDD = 3.0V, IOL = 5mA 1.0 V VDD = 3.6V, VIH = 3.6V 0.3 20 µA VDD = 3.6V, VIL = 0.3V –0.3 –20 µA VDD = 3.6V, VIH = 3.6V 0.1 10 µA –10 µA IILR VDD = 3.6V, VIL = 0.3V –0.1 RST∗1 –0.9 –200 µA I/O leakage current IIZ PA to PG, PI, PJ, MP AN0 to AN3, CS0, SI0, SO0 SCK0, RST∗1 VDD = 3.6V, VI = 0, 3.6V ±10 µA Open drain output leakage current ILOH PH VDD = 3.6V, VOH = 12V 50 µA 15 30 mA 0.8 2.5 mA 10 µA 20 pF IILE Input current EXTAL IIHT IILT TEX 12MHz crystal oscillation (C1 = C2 = 15pF) IDD1 Supply current∗2 IDDS1 IDDS3 VDD = 3.3V ± 0.3V∗3 SLEEP mode VDD VDD = 3.3V ± 0.3V STOP mode (EXTAL and TEX pins oscillation stop) VDD = 3.3V ± 0.3V Input capacity CIN Other than VDD, Clock 1MHz Vss, AVDD, and 0V other than the measured pins AVss 10 ∗1 RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current when non-resistor is selected. ∗2 When entire output pins are open. ∗3 When setting upper 2 bits (CPU clock selection) of clock control register CLC (address: 00FEH) to "00" and operating in high speed mode (1/2 dividing clock). – 16 – CXP81952/81960 AC Characteristics (1) Clock timing Item (Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V) Symbol System clock frequency fC Pins Conditions XTAL EXTAL Fig. 1, 1 16 1 12 Fig. 2 VDD = 4.5 to 5.5V tXL, tXH XTAL EXTAL Fig. 1, System clock input rise and fall times XTAL EXTAL Fig. 1, Fig. 2 (External clock drive) EC Fig. 3 Event count clock input rise and fall times tCR, tCF tEH, tEL tER, tEF EC Fig. 3 System clock frequency fC TEX TX Fig. 2 VDD = 2.7 to 5.5V (32kHz clock applied condition) Event count clock input pulse width tTL, tTH tTR, tTF TEX Fig. 3 TEX Fig. 3 Event count clock input rise and fall times Max. VDD = 4.5 to 5.5V System clock input pulse width Event count clock input pulse width Min. 28 Fig. 2 (External clock drive) Unit MHz ns 37.5 200 tsys × 4∗ ns ns 20 ns 32.768 kHz 10 µs 20 ms ∗ tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Fig. 1. Clock timing 1/fc VDD – 0.4V EXTAL 0.4V tXH tCF tXL tCR Fig. 2. Clock applied condition AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA Crystal oscillation Ceramic oscillation EXTAL C1 32kHz clock applied condition crystal oscillation External clock EXTAL XTAL C2 TEX XTAL TX C2 C1 74HC04 Fig. 3. Event count clock timing 0.8VDD TEX EC 0.2VDD tEH tEF tEL tER tTH tTF tTL tTR – 17 – CXP81952/81960 (2) Serial transfer (CH0) Item (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Symbol Pin Condition Min. Max. Unit CS ↓ → SCK delay time tDCSK SCK0 Chip select transfer mode (SCK = output mode) tsys + 200 ns CS ↑ → SCK floating delay time tDCSKF SCK0 Chip select transfer mode (SCK = output mode) tsys + 200 ns CS ↓ → SO delay time tDCSO SO0 Chip select transfer mode tsys + 200 ns CS ↓ → SO floating delay time tDCSOF SO0 Chip select transfer mode tsys + 200 ns CS high level width tWHCS CS0 Chip select transfer mode tsys + 200 ns SCK cycle time Input mode SCK0 2tsys + 200 ns tKCY 8000/fc ns SCK high and low level widths tKH tKL tsys + 100 ns SCK0 Output mode 8000/fc – 100 ns SI input setup time (against SCK ↑) SCK input mode SI0 –tsys + 100 ns tSIK 200 ns SI input hold time (against SCK ↑) SI0 2tsys + 100 ns tKSI 100 ns SCK ↓ → SO delay time tKSO SO0 Output mode Input mode SCK output mode SCK input mode SCK output mode SCK input mode SCK output mode 2tsys + 200 ns 100 ns Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) CS, SCK, SI and SO means each pin of CS → CS0, SCK → SCK0, SI → SI0, and SO → SO0 respectively. Note 3) The load of SCK output mode and SO output delay time is 50pF + 1TTL. – 18 – CXP81952/81960 Serial transfer (CH0) Item (Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V) Symbol Pin Condition Min. Max. Unit CS ↓ → SCK delay time tDCSK SCK0 Chip select transfer mode (SCK = output mode) tsys + 250 ns CS ↑ → SCK floating delay time tDCSKF SCK0 Chip select transfer mode (SCK = output mode) tsys + 200 ns CS ↓ → SO delay time tDCSO SO0 Chip select transfer mode tsys + 250 ns CS ↓ → SO floating delay time tDCSOF SO0 Chip select transfer mode tsys + 200 ns CS high level width tWHCS CS0 Chip select transfer mode tsys + 200 ns SCK cycle time Input mode SCK0 2tsys + 200 ns tKCY 8000/fc ns SCK high and low level widths tKH tKL tsys + 100 ns SCK0 8000/fc – 150 ns SI input setup time (against SCK ↑) SI0 –tsys+100 ns tSIK 200 ns SI input hold time (against SCK ↑) SI0 2tsys+100 ns tKSI 100 ns SCK ↓ → SO delay time tKSO SO0 Output mode Input mode Output mode SCK input mode SCK output mode SCK input mode SCK output mode SCK input mode SCK output mode 2tsys + 250 ns 125 ns Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) CS, SCK, SI and SO means each pin of CS → CS0, SCK → SCK0, SI → SI0, and SO → SO0 respectively. Note 3) The load of SCK output mode and SO output delay time is 50pF. – 19 – CXP81952/81960 Fig. 4. Serial transfer timing (CH0) tWHCS CS0 0.8VDD 0.2VDD tKCY tDCSK tKL tDCSKF tKH 0.8VDD 0.8VDD SCK0 0.2VDD tKSI tSIK 0.8VDD Input data SI0 0.2VDD tDCSO tKSO tDCSOF 0.8VDD SO0 Output data 0.2VDD – 20 – CXP81952/81960 Serial transfer (CH1) Item (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Symbol Pin Condition tKCY SCK1 SCK1 high and low level widths tKH tKL SCK1 SI1 input setup time (against SCK1 ↑) tSIK SI1 SI1 input hold time (against SCK1 ↑) tKSI SI1 SCK1 ↓ → SO1 delay time tKSO SO1 Max. Unit 2tsys + 200 ns 8000/fc ns tsys + 100 ns 4000/fc – 100 ns SCK1 input mode 100 ns SCK1 output mode 200 ns tsys + 200 ns 100 ns Input mode SCK1 cycle time Min. Output mode Input mode Output mode SCK1 input mode SCK1 output mode SCK1 input mode SCK1 output mode tsys + 200 ns 100 ns Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL. Serial transfer (CH1) Item (Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V) Symbol Pin SCK1 cycle time tKCY SCK1 SCK1 high and low level widths tKH tKL SCK1 SI1 input setup time (against SCK1 ↑) tSIK SI1 SI1 input hold time (against SCK1 ↑) tKSI SI1 SCK1 ↓ → SO1 delay time tKSO SO1 Condition Min. Max. Unit 2tsys + 200 ns 8000/fc ns tsys + 100 ns 4000/fc – 150 ns SCK1 input mode 100 ns SCK1 output mode 200 ns tsys + 200 ns 100 ns Input mode Output mode Input mode Output mode SCK1 input mode SCK1 output mode SCK1 input mode SCK1 output mode tsys + 250 ns 125 ns Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF. – 21 – CXP81952/81960 Fig. 5. Serial transfer CH1 timing tKCY tKL tKH SCK1 0.8VDD 0.2VDD tSIK tKSI 0.8VDD SI1 Input data 0.2VDD tKSO 0.8VDD Output data SO1 0.2VDD (3) General purpose prescaler Item (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Symbol Pin External clock input frequency fPCK PCK External clock input pulse width tWH, tWL tR, tF PCK External clock input rise and fall times Condition Min. PCK Unit 12 MHz ns 200 1/fPCK tF 0.8VDD PCK Max. 33 Fig. 6. General purpose prescaler timing tWH Typ. 0.5VDD 0.2VDD tR tWL – 22 – ns CXP81952/81960 (4) A/D converter characteristics Item Symbol (Ta = –20 to +75°C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V) Pins Conditions Min. Typ. Max. Unit 8 Bits ±1 LSB ±2 LSB Resolution Ta = 25°C VDD = AVDD = AVREF = 5.0V VSS = AVSS = 0V Linearity error Absolute error tCONV tSAMP Conversion time Sampling time Reference input voltage VREF Analog input voltage VIAN IREFS µs 12/fADC∗ µs VDD = AVDD = 4.5 to 5.5V AVDD – 0.5 AVREF AVDD 0 AN0 to AN11 IREF AVREF current 160/fADC∗ V 0.6 Operating mode SLEEP mode STOP mode 32kHz operating mode AVREF V 1.0 mA 10 µA (Ta = –20 to +75°C, VDD = AVDD = 3.0 to 3.6V, AVREF = 2.7 to AVDD, Vss = AVSS = 0V) Item Symbol Pins Conditions Min. Typ. Max. Unit 8 Bits ±1 LSB ±2 LSB Resolution Ta = 25°C VDD = AVDD = AVREF = 5.0V VSS = AVSS = 0V Linearity error Absolute error 160/fADC∗ 12/fADC∗ tCONV tSAMP Conversion time Sampling time Reference input voltage VREF Analog input voltage VIAN AVREF current IREFS AVDD V 0.7 mA 10 µA 0 AN0 to AN11 Operating mode AVREF µs VDD = AVDD = 3.0 to 3.6V AVDD – 0.3 AVREF IREF µs 0.4 SLEEP mode STOP mode 32kHz operating mode Fig. 7. Definitions of A/D converter terms Digital conversion value FFH FEH ∗ The value of fADC is as follows by selecting ADC operation clock (MSC: Address 01FFH bit 0). When PS2 is selected, fADC = fc/2 When PS1 is selected, fADC = fc Linearity error 01H 00H VFT VZT Analog input – 23 – CXP81952/81960 (5) Interruption, reset input (Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V) Item Symbol Pins Conditions External interruption high and low level widths tIH tIL INT0 INT1 INT2 NMI PJ0 to PJ7 Reset input low level width tRSL RST Min. Max. Unit 1 µs 32/fc µs Fig. 8. Interruption input timing INT0 INT1 INT2 NMI PJ0 to PJ7 (During standby release input) (Falling edge) tIH tIL 0.8VDD 0.2VDD Fig. 9. Reset input timing tRSL RST 0.2VDD (6) Others (Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V) Item EXI input high and low level widths Note) Symbol tEIH tEIL Pins EXI0 EXI1 Conditions tsys = 2000/fc Min. Max. tFRC × 8 + 200 + tsys Unit ns tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") tFRC = 1000/fc [ns] Fig. 10. Other timings tEIH EXI0 EXI1 tEIL 0.8VDD 0.2VDD – 24 – CXP81952/81960 Supplement Fig. 11. Recommended oscillation circuit AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA (i) EXTAL (ii) TEX XTAL Rd C1 RIVER ELETEC CO., LTD. Rd C2 Manufacturer Model C2 C1 fc (MHz) C1 (pF) C2 (pF) 8.00 10 10 5 5 8.00 16 (12) 16 (12) 10.00 16 (12) 16 (12) 12.00 12 12 16.00 12 12 32.768kHz 30 18 10.00 HC-49/U03 TX 12.00 Rd (Ω) Circuit example 0 (i) 0 (i) 470K (ii) 16.00 HC-49/U (-S) KINSEKI LTD. P3 Mask option table Content Item Reset pin pull-up resistor Non-existent Existent – 25 – CXP81952/81960 Characteristics Curve IDD vs. fc IDD vs. VDD (VDD = 5V, Ta = 25°C, Typical) (fc = 16MHz, Ta = 25°C, Typical) 40 20.0 1/4 dividing mode 10.0 1/16 dividing mode 5.0 1/2 dividing mode 30 SLEEP mode 1.0 32kHz mode (instruction) 0.5 32kHz SLEEP mode 0.1 (100µA) 0.05 (50µA) IDD – Supply current [mA] IDD – Supply current [mA] 1/2 dividing mode 20 1/4 dividing mode 10 1/16 dividing mode 0.01 (10µA) SLEEP mode 3 6 4 5 VDD – Supply voltage [V] 0 5 10 Frequency [MHz] 16 IDD vs. VDD IDD vs. fc (fc = 12MHz, Ta = 25°C, Typical) (VDD = 3.3V, Ta = 25°C, Typical) 40 1/2 dividing mode 20.0 1/4 dividing mode 10.0 1/16 dividing mode 30 SLEEP mode 1.0 0.5 0.1 (100µA) 0.05 (50µA) IDD – Supply current [mA] IDD – Supply current [mA] 5.0 20 1/2 dividing mode 10 1/4 dividing mode 0.01 (10µA) 1/16 dividing mode SLEEP mode 3 6 4 5 VDD – Supply voltage [V] 0 1 – 26 – 5 10 Frequency [MHz] 15 CXP81952/81960 Unit: mm 100PIN QFP (PLASTIC) + 0.4 14.0 – 0.01 17.9 ± 0.4 15.8 ± 0.4 + 0.1 0.15 – 0.05 23.9 ± 0.4 + 0.4 20.0 – 0.1 A 0.65 + 0.35 2.75 – 0.15 ±0.12 M 0° to 15° DETAIL A 0.8 ± 0.2 (16.3) 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING SONY CODE QFP-100P-L01 LEAD TREATMENT EIAJ CODE ∗QFP100-P-1420-A LEAD MATERIAL COPPER / 42 ALLOY PACKAGE WEIGHT 1.4g JEDEC CODE 100PIN LQFP (PLASTIC) 16.0 ± 0.2 ∗ 14.0 ± 0.1 75 51 76 (15.0) 50 0.5 ± 0.2 A 26 (0.22) 100 1 0.5 ± 0.08 + 0.08 0.18 – 0.03 25 + 0.2 1.5 – 0.1 + 0.05 0.127 – 0.02 0.1 0.1 ± 0.1 0° to 10° 0.5 ± 0.2 Package Outline DETAIL A NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY/PHENOL RESIN SONY CODE LQFP-100P-L01 LEAD TREATMENT SOLDER PLATING EIAJ CODE ∗QFP100-P-1414-A LEAD MATERIAL 42 ALLOY JEDEC CODE PACKAGE WEIGHT – 27 –