CXP871P40 CMOS 8-bit Single Chip Microcomputer Description The CXP871P40 is a CMOS 8-bit microcomputer which consists of A/D converter, serial interface (2ch independently), timer/counter, time base timer, vector interruption, high precision timing pattern generation circuit (PPG 2ch independently, RTG 2ch independently), PWM generator, general purpose prescaler, PWM for tuner, VCR vertical sync separation circuit and the measuring circuit which measures signals of capstan FG and drum FG/PG and other servo systems, as well as basic configurations like 8-bit CPU, PROM, RAM and I/O port. They are integrated into a single chip. Also CXP871P40 provides power on reset function, sleep/stop function which enables to lower power consumption . CXP871P40 is the PROM-incorporated version of the CXP87132/87140 with built-in mask ROM. This provides the additional feature of being able to write directly into the program. Thus, it is most suitable for evaluation use during system development and for small-quantity production. 100 pin QFP (PIastic) 100 pin LQFP (PIastic) Features • A wide instruction set (213 instructions) which covers various types of data — 16-bit arithmetic instruction/multiplication and division instructions/boolean bit operation instruction • Minimum instruction cycle 333ns at 12MHz operation (3.0 to 5.5V) 250ns at 16MHz operation (4.5 to 5.5V) • Incorporated PROM capacity 40K bytes • Incorporated RAM capacity 1312 bytes • Peripheral functions — A/D converter 8-bit, 12-channel, successive approximation system (Conversion time: 20µs/16MHz) — Serial I/O Incorporated buffer RAM (1 to 32 bytes auto transfer) 1-channel Incorporated 8-bit and 8-stage FIFO (1 to 8 bytes auto transfer) 1-channel — Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer — High precision timing pattern generator PPG 19 pins 32-stage programmable PPG 10 pins 21-stage programmable RTG 5 pins 2-channel — PWM/DA gate output PWM 12-bit, 2-channel (Repetitive frequency 62.5kHz/16MHz) DA gate pulse 12-bit, 4-channel — Servo input control Capstan FG, Drum FG/PG, CTL input — VSYNC separator — FRC capture unit Incorporated 26-bit and 8-stage FIFO — PWM output 14-bit, 1-channel — General purpose prescaler 10-bit (System clock asynchronous) — Pulse cycle measurement circuit • Interruption 18 factors, 14 vectors, multi-interruption possible • Standby mode Sleep/stop • Package 100-pin plastic QFP/LQFP Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E93X30A81-PS PG4/PMI PG7/PMSK PE2/PWM0 PE4/DAA0 PE6/DAB0 PE3/PWM1 PE5/DAA1 PE7/DAB1 PI2/PWM PI0/PCK/OSCI PK0/OSCO PI1/PO PE0/XOUT PG0/CFG PG1/DFG PG2/DPG PG3/PBCTL PG6/EXI0 PG7/EXI1 PG4/SYNC0 PG5/SYNC1 PE1/EC PI3/TO PI5/SCK1 PI7/SI1 PI6/SO1 AVREF AVDD FIFO SERIAL INTERFACE UNIT (CH1) SERVO INPUT CONTROL PULSE MEASURE UNIT 12BIT PWM GENERATOR CH1 12BIT PWM GENERATOR CH0 14BIT PWM GENERATOR PROGRAMMABLE PRESCALER CTL DRUM CAPSTAN V SYNC SEPARATOR 8BIT TIMER 1 8BIT TIMER/COUNTER 0 BUFFER RAM AVss SERIAL INTERFACE UNIT (CH0) A/D CONVERTER 4 4 2 2 3 2 2 2 INTERRUPT CONTROLLER PE1/INT2 PI4/INT1 19 19 PROGRAMMABLE PATTERN GENERATOR (CH0) FRC CAPTURE UNIT RAM FIFO PPO000 to PPO018 CS0 SI0 SO0 SCK0 12 PROM 40K BYTES SPC700 CPU CORE PPO100 to PPO107 AN0 to AN3 PF0/AN4 to PF7/AN11 2 Vss Vpp VDD EXTAL XTAL 10 10 CH0 5 CH1 REALTIME PULSE GENERATOR 2 RAM PRESCALER/ TIME BASE TIMER RAM 1312 BYTES CLOCK GENERATOR/ SYSTEM CONTROL RST MP PROGRAMMABLE PATTERN GENERATOR (CH1) PPO112 to PPO113 1 PK0 PJ0 to PJ7 8 PF4 to PF7 PI1 to PI7 PF0 to PF3 4 4 7 PE2 to PE7 6 PI0 PE0 to PE1 2 1 PD0 to PD7 8 PH0 to PH7 PC0 to PC7 8 8 PB0 to PB7 8 PG0 to PG7 PA0 to PA7 8 8 PORT H PORT I –2– RTO3 to RTO7 PORT A PORT B PORT C PORT D PORT E PORT F PORT G PORT J PORT K Block Diagram CXP871P40 PE0/INT0 CXP871P40 PI5/SCK1 PI3/TO PI4/INT1 PI1/PO PI2/PWM Mask option PI0/PCK/OSCI PK0/OSCO VDD VSS PA7/PPO007/PPO107 Vpp PA5/PPO005/PPO105 PA6/PPO006/PPO106 PA3/PPO003/PPO103 PA4/PPO004/PPO104 PA2/PPO002/PPO102 PA0/PPO000/PPO100 PA1/PPO001/PPO101 PB7/PPO015 PB6/PPO014 Pin Configuration 1 (Top View) 100-pin QFP Package A A 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PB5/PPO013/PPO113 1 PB4/PPO012/PPO112 2 PB3/PPO011 3 PB2/PPO010 4 PB1/PPO009 80 PI6/SO1 79 PI7/SI1 78 PE0/INT0/XOUT 77 PE1/EC/INT2 5 76 PE2/PWM0 PB0/PPO008 6 75 PE3/PWM1 PC7/RTO7 7 74 PE4/DAA0 PC6/RTO6 8 73 PE5/DAA1 PC5/RTO5 9 72 PE6/DAB0 PC4/RTO4 10 71 PE7/DAB1 PC3/RTO3 11 70 PG0/CFG PC2/PPO018 12 69 PG1/DFG PC1/PPO017 13 68 PF2/DPG PC0/PPO016 14 67 PG3/PBCTL PJ7 15 66 PG4/SYNC0/PMI PJ6 16 65 PG5/SYNC1 PJ5 17 64 PG6/EXI0 PJ4 18 63 PG7/EXI1/PMSK PJ3 19 62 AN0 PJ2 20 61 AN1 PJ1 21 60 AN2 PJ0 22 59 AN3 PD7 23 58 PF0/AN4 PD6 24 57 PF1/AN5 PD5 25 56 PF2/AN6 PD4 26 55 PF3/AN7 PD3 27 54 AVDD PD2 28 53 AVREF PD1 29 52 AVSS PD0 30 51 PF4/AN8 Note) PF5/AN9 PF7/AN11 PF6/AN10 SO0 SCK0 SI0 CS0 XTAL EXTAL VSS RST MP PH0 PH1 PH2 PH3 PH4 PH5 PH7 PH6 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1. Vpp (Pin 90) is always connected to VDD. 2. Vss (Pins 41 and 88) are both connected to GND. –3– CXP871P40 PI7/SI1 PE0/INT0/XOUT PI5/SCK1 PI6/SO1 PI3/TO PI4/INT1 PI1/PO PI2/PWM Mask option PI0/PCL/OSCI PK0/OSCO VDD VSS PA7/PPO007/PPO107 Vpp PA5/PPO005/PPO005 PA6/PPO006/PPO106 PA3/PPO003/PPO103 PA4/PPO004/PPO104 PA2/PPO002/PPO102 PA0/PPO000/PPO100 PA1/PPO001/PPO101 PB6/PPO014 PB7/PPO015 PB5/PPO013/PPO113 PB4/PPO012/PPO112 Pin Configuration 2 (Top View) 100-pin LQFP Package 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PB3/PPO011 1 PB2/PPO010 2 PB1/PPO009 3 PB0/PPO008 4 PC7/RTO7 5 PC6/RTO6 6 PC5/RTO5 AA AA 75 PE1/EC/INT2 74 PE2/PWM0 73 PE3/PWM1 72 PE4/DAA0 71 PE5/DAA1 70 PE6/DAB0 7 69 PE7/DAB1 PC4/RTO4 8 68 PG0/CFG PC3/RTO3 9 67 PG1/DFG PC2/PPO018 10 66 PF2/DPG PC1/PPO017 11 65 PG3/PBCTL PC0/PPO016 12 64 PG4/SYNC0/PMI PJ7 13 63 PG5/SYNC1 PJ6 14 62 PG6/EXI0 PJ5 15 61 PG7/EXI1/PMSK PJ4 16 60 AN0 PJ3 17 59 AN1 PJ2 18 58 AN2 PJ1 19 57 AN3 PJ0 20 56 PF0/AN4 PD7 21 55 PF1/AN5 PD6 22 54 PF2/AN6 PD5 23 53 PF3/AN7 PD4 24 52 AVDD PD3 25 51 AVREF Note) AVSS PF4/AN8 PF5/AN9 PF6/AN10 SCK0 PF7/AN11 SI0 SO0 CS0 EXTAL VSS XTAL MP RST PH1 PH0 PH2 PH4 PH3 PH5 PH6 PH7 PD0 PD2 PD1 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1. Vpp (Pin 88) is always connected to VDD. 2. Vss (Pins 39 and 86) are both connected to GND. –4– CXP871P40 Pin Description Symbol I/O PA0/PPO000 /PPO100 to PA7/PPO007 /PPO107 Output/ Real time output PB0/PPO008 to PB7/PPO015 Output/ Real time output PC0/PPO016 to PC2/PPO018 I/O/ Real time output PC3/RTO3 to PC7/RTO7 I/O/ Real time output Description (Port A) 8-bit output port. Data is gated with PPO0 and PPO1 contents by OR-gate and they are output. (8 pins) Programmable pattern generator (PPG0, PPG1) output. (Port B) 8-bit output port. Data is gated Functions as high precision real time with PPO0 and PPO1 contents pulse output port. PPG0 19 pins by OR-gate and they are output. PPG1 10 pins (8 pins) ( (Port C) 8-bit I/O port. Enables to specify I/O by bit unit. Data is gated with PPO or RTO contents by OR-gate and they are output. (8 pins) ) Real time pulse generator (RTG) output. Functions as high precision real time pulse output port. (5 pins) (Port D) 8-bit I/O port. Enables to specify I/O by 4-bit unit. Enables to drive 12mA sink current. (During 5V±0.5V operation) (8 pins) PD0 to PD7 I/O PE0/INT0 /XOUT Input/Input/Output Input pin to request 1/2 dividing external interruption. clock output of Active when falling edge. XTAL or OSCO. PE1/EC/INT2 Input/Input/Input External event Input pin to request external interruption. input pin for timer/counter. Active when falling edge. PE2/PWM0 Output/Output PE3/PWM1 Output/Output PE4/DAA0 Output/Output PE5/DAA1 Output/Output PE6/DAB0 Output/Output PE7/DAB1 Output/Output AN0 to AN3 Input Analog input pins to A/D converter. (12 pins) PF0/AN4 to PF3/AN7 Input/Input PF4/AN8 to PF7/AN11 Output/Input (Port F) Lower 4 bits are input port and upper 4 bits are output port. Lower 4 bits also serve as standby release input pin. (8 pins) SCK0 I/O Serial clock (CH0) I/O pin. SO0 Ouput Serial data (CH0) output pin. SI0 Input Serial data (CH0) input pin. CS0 Input Serial chip select (CH0) input pin. (Port E) 8-bit port. Lower 2 bits are input port and upper 6 bits are output port. (8 pins) PWM output pins. (2 pins) DA gate pulse output pins. (4 pins) –5– CXP871P40 Symbol I/O Description PG0/CFG Input/Input Capstan FG input pin. PG1/DFG Input/Input Drum FG input pin. PG2/DPG Input/Input Drum PG input pin. PG3/PBCTL Input/Input (Port G) 8-bit input port. (8 pins) Playback CTL pulse input pin. Measuring pulse signal input pin of pulse cycle measuring unit. PG4/SYNC0 /PMI Input/Input/Input PG5/SYNC1 Input/Input PG6/EXI0 Input/Input PG7/EXI1/ PMSK Input/Input/Input PH0 to PH7 Output PI0/PCK /OSCI Input/Input/Input PI1/PO I/O/Output PI2/PWM I/O/Output PI3/TO I/O/Output PI4/INT1 I/O/Input PI5/SCK1 I/O/I/O PI6/SO1 I/O/Output Serial data (CH1) output pin. PI7/SI1 I/O/Input Serial data (CH1) input pin. PJ0 to PJ7 I/O Composite sync signal input pin. External input pin to FRC capture unit. Measuring enable signal input pin of pulse cycle measuring unit. (Port H) 8-bit output port; large current, N-ch open drain output. (8 pins) (Port I) Lower 1 bit is input port (mask option) and upper 7 bits are I/O port. I/O port can be specified by bit unit. (8 pins) Connecting pin of crystal External clock input pin of general oscillation circuit for general purpose prescaler. purpose prescaler. (Mask option) General purpose prescaler output pin. 14-bit PWM output pin. Timer/counter output pin. (duty = 50%) Input pin to request external interruption. Active when falling edge. Serial clock (CH1) I/O pin. (Port J) 8-bit I/O port. Function as standby release input can be specified by bit unit. I/O can be specified by bit unit. (8 pins) –6– CXP871P40 Symbol I/O Description Connecting pin of crystal oscillation circuit for general purpose prescaler. (Mask opiton) PK0/OSCO Input/Output Input port. (Mask option) EXTAL Input XTAL Output Connecting pin of crystal oscillator for system clock. When supplying the external clock, input the external clock to EXTAL pin and input opposite phase clock to XTAL pin. RST I/O System reset pin of active "L" level. RST pin is I/O pin, which output "L" level by incorporated power on reset function when power on. (Mask option) MP Input Microprocessor mode input pin. Always connect to GND. Positive power supply pin of A/D converter. AVDD AVREF Input Reference voltage input pin of A/D converter. AVSS GND pin of A/D converter. VDD Positive power supply pin. Vpp Positive power supply pin for built-in PROM writing. Connect to VDD for normal operation. VSS GND pin. Connect two Vss pins to GND. –7– CXP871P40 Input/Output Circuit Format for Pins Pin PA0/PPO000 /PPO100 to PA7/PPO007 /PPO107 PB4/PPO012 /PPO112 to PB5/PPO013 /PPO113 10 pins Circuit format When reset Port A AA AA Port B AAAA AAAA PPO0 data PPO1 data Port A or Port B Data bus Hi-Z Output becomes active from high impedance by data writing to port register. RD Port B PB0/PPO008 to PB3/PPO011 PB6/PPO014 to PB7/PPO015 AAAA AAAA AA AA PPO0 data Port A or Port B Data bus Output becomes active from high impedance by data writing to port register. RD 6 pins Port C PC0/PPO016 to PC2/PPO018 PC3/RTO3 to PC7/RTO7 AAAA AAAA AAAA PPO, RTO data Port C data (Every bit) RD (Port C) Port D AAAA AAAA AAAA AAAA AA AA AA Large current 12mA Port D data IP Port D direction (Every 4 bits) PD0 to 3 PD4 to 7 Data bus 8 pins Hi-Z IP Port C direction 8 pins AA AA AA Input protection circuit Data bus PD0 to PD7 Hi-Z RD (Port D) –8– Hi-Z CXP871P40 Pin Circuit format Port E AAA Schmitt input IP PE1/EC/INT2 Hi-Z Data bus RD (Port E) 1 pin AA AA AA AA AA AAAA AAAA AA AA AA AAAA AA AAAA AAAA Port E PS1 MPX PE0/INT0 /XOUT When reset 1/2 OSCO Port E function select register AA AA IP Hi-Z Data bus 1 pin RD (Port E) Port E DA gate output or PWM output PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 MPX Hi-Z control Port E data To interruption circuit AA AA Hi-Z Port E function select register Data bus 4 pins RD (Port E) AA AA AA AAAA AAAA AAAA Port E DA gate output Hi-Z control PE6/DAB0 PE7/DAB1 MPX Port E data Port E function select register Data bus RD (Port E) 2 pins –9– AA H level CXP871P40 Pin Circuit format When reset AAA AN0 to AN3 Input multiplexer 4 pins Port F Hi-Z A/D converter IP AA A AAA Input multiplexer A/D converter IP PF0/AN4 to PF3/AN7 Hi-Z Data bus RD (Port F) 4 pins AAAA AAAAAAAA AAAA Port F PF4/AN8 to PF7/AN11 Port F data Data bus RD (Port F) 4 pins AA AA AA AA IP Port/AD select Hi-Z Input multiplexer A/D converter Port G PG0/CFG PG1/DFG PG2/DPG PG3/PBCTL PG4/SYNC0/PMI PG5/SYNC1 PG6/EXI0 PG7/EXI1/PMSK AAA Schmitt input Pulse cycle measuring unit input Servo input IP Data bus RD (Port G) Note) For PG4/SYNC0, PG5/SYNC1, CMOS schmitt input and TTL schmitt input can be selected with the mask option. 8 pins Port H PH0 to PH7 Hi-Z AA AA AAAA AAAA Port H data Data bus Large current output RD (Port H) 8 pins – 10 – Hi-Z CXP871P40 Pin Circuit format Port I When reset AAAA AA AAAAAA AAAA AA AAAA AA AAAA A A AA AA AAAA AAAA AAAA AAAA AA AA A A Port I function select PI1/PO PI2/PWM PI3/TO PI1: From general purpose prescaler PI2: From 14-bit PWM PI3: From timer/counter MPX Port I data Port I direction Data bus IP RD (Port I) 3 pins Port I Port I data PI4/INT1 PI7/SI1 Port I direction Hi-Z IP Data bus RD (Port I) 2 pins Hi-Z PI4: To interruption circuit PI7: To serial CH1 Schmitt input AAAA AAAA AAA AAAA AAA AA AAAA AAA AA AA AA AA AAAA AA AAA AAA AA AAA AA AA A Port I Port I function select From serial CH1 MPX PI5/SCK1 PI6/SO1 Port I data MPX Port I direction IP Note) PI5 is schmitt input PI6 is inverter input Data bus RD (Port I) 2 pins Hi-Z To serial CH1 Port J Port J data PJ0 to PJ7 Port J direction IP Data bus 8 pins RD (Port J) Standby release Edge detection – 11 – Hi-Z CXP871P40 Pin Circuit format When reset AA A AAA Schmitt input CS0 SI0 2 pins SO0 SO0 from SI0 1 pin SO0 output enable Internal serial clock from SI0 SCK0 External serial clock to SI0 1 pin Schmitt input AA A AA A AA AA AA AA AA AA AA AA AAAA AA A AA A AA AA AAAA AAAA EXTAL 2 pins XTAL AA AA AA AA AA AA Hi-Z Hi-Z IP SCK0 output enable EXTAL XTAL Hi-Z To SI0 IP IP • Shows the circuit composition during oscillation. • Feedback resistor is removed during stop. Oscillation Pull-up resistor Mask option Schmitt input OP RST L level IP From power on reset circuit (mask option) 1 pin MP IP 1 pin Port I Port K OSCI PI0/PCK/OSCI PK0/OSCO Hi-Z CPU mode IP Oscillation OSCO Fig. 1 PI0/PCK or PK0 2 pins IP Note) Circuit format of Fig. 1 or Fig. 2 can be selected with mask option. – 12 – Fig. 2 Data bus RD Port I Port K Hi-Z CXP871P40 Absolute Maximum Ratings Item (Vss = 0V reference) Rating Unit VDD –0.3 to +7.0 V Vpp –0.3 to +13.0 AVss to +7.0∗1 V V VIN –0.3 to +0.3 –0.3 to +7.0∗2 Output voltage VOUT –0.3 to +7.0∗2 V High level output current IOH –5 mA Total of output pins High level total output current ∑IOH –50 mA IOL 15 mA Other than large current output pins: per pin Large current output pin∗3: per pin IOLC 20 mA Total of output pins Low level total output current ∑IOL 130 mA Operating temperature Topr –10 to +75 °C Storage temperature Tstg –55 to +150 °C Allowable power dissipation PD Power supply voltage Symbol AVDD AVSS Input voltage Low level output current 600 380 Remarks Incorporated PROM V V mW QFP LQFP ∗1 AVDD and VDD should be set to the same voltage. ∗2 VIN and VOUT should not exceed VDD + 0.3V. (CS0, SI0, PG and PH excluded.) ∗3 The large current operation transistors are the N-CH transistors of the PD and PH ports. Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should better take place under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI. – 13 – CXP871P40 Recommended Operating Conditions Item Power supply voltage Symbol VDD Vpp Analog voltage High level input voltage (Vss = 0V reference) Min. Max. Unit Remarks 3.0 5.5 V Guaranteed range during high speed mode (1/2 dividing clock) operation 2.7 5.5 V Guaranteed range during low speed mode (1/16 dividing clock) operation 2.5 5.5 V Vpp = VDD V Guaranteed data hold operation range during stop ∗9 3.0 5.5 V ∗1 VIH 0.7VDD VDD V ∗2 VIHS 0.8VDD VDD V 5.5 V VIHTS 2.2 5.5 V AVDD VIHEX CMOS schmitt input∗3 and PE0/INT0 pins CMOS schmitt input∗4 V TTL schmitt input∗5, ∗8 EXTAL pin∗6 0.3VDD V ∗2, ∗8 0.2VDD V ∗2, ∗7 VDD + 0.4 VDD + 0.3 VIL 0 VILS 0 0.2VDD V VILTS 0 0.8 V CMOS schmitt input∗3, ∗4 and PE0/INT0 pins TTL schmitt input∗5, ∗8 VILEX –0.3 0.4 V EXTAL pin∗6 Operating temperature Topr –10 +75 °C Low level input voltage ∗1 ∗2 ∗3 ∗4 ∗5 ∗6 ∗7 ∗8 ∗9 AVDD and VDD should be set to the same voltage. Normal input port (each pin of PC, PD, PF0 to PF3, PI PJ, and PK), MP pin. Each pin of SCK0, RST, PE1/EC/INT2, PI1/PO, PI4/INT1, PI5/SCK1 and PI7/SI1. Each pin of CS0, SI0, and PG (When CMOS schmitt input is selected with mask option for PG4 and PG5) Each pin of PG4 and PG5 (When TTL schmitt input is selected with mask option) It specifies only when the external clock is input. In case of 3.0 to 3.6V supply voltage (VDD). In case of 4.5 to 5.5V supply voltage (VDD). Vpp and VDD should be set to the same voltage. – 14 – CXP871P40 Electrical Characteristics DC Characteristics Supply voltage (VDD) 4.5 to 5.5V Item High level output voltage Symbol VOH Low level output voltage VOL Pin I/O leakage current IILE Min. Typ. Max. Unit VDD = 4.5V, IOH = –0.5mA 4.0 V VDD = 4.5V, IOH = –1.2mA 3.5 V PD, PH EXTAL VDD = 4.5V, IOL = 1.8mA 0.4 V VDD = 4.5V, IOL = 3.6mA 0.6 V VDD = 4.5V, IOL = 12.0mA 1.5 V VDD = 5.5V, VIH = 5.5V 0.5 40 µA VDD = 5.5V, VIL = 0.4V –0.5 –40 µA IILR RST∗2 VDD = 5.5V, VIL = 0.4V –1.5 –400 µA IIZ PA to PK, MP, AN0 to AN3, CS, SI, SO, SCK, RST∗2 VDD = 5.5V, VI = 0, 5.5V ±10 µA 25 45 mA 1 5 mA 10 µA 20 pF Crystal oscillation (C1 = C2 = 15pF) of 16MHz IDD1 Supply current∗3 Condition PA to PE, PF4 to PF7, PH (VOL only) PI1 to PI7, PJ, SO, SCK, RST∗1 (VOL only) IIHE Input current (Ta = –10 to +75°C, Vss = 0V reference) IDDS1 VDD = 5V ± 10%∗4 VDD Sleep mode VDD = 5V ± 10% IDDS3 Stop mode VDD = 5.5V Input capacity CIN Other than VDD, Clock 1MHz Vss, AVDD, and 0V other than the measured pins AVss pins 10 ∗1 RST pin specifies only when the power on reset circuit has been selected with mask option. ∗2 RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current when non-resistance is selected. ∗3 When entire output pins are open. ∗4 When setting upper 2 bits (CPU clock selection) of clock control register CLC (address: 00FEH) to "00" and operating in high speed mode (1/2 dividing clock). – 15 – CXP871P40 Supply voltage (VDD) 3.0 to 3.6V Item High level output voltage Symbol VOH Low level output voltage VOL Pin I/O leakage current IILE Max. Unit V VDD = 3.0V, IOH = –0.5mA 2.3 V PD, PH EXTAL VDD = 3.0V, IOL = 1.2mA 0.3 V VDD = 3.0V, IOL = 1.6mA 0.5 V VDD = 3.0V, IOL = 5.0mA 1.0 V VDD = 3.6V, VIH = 3.6V 0.3 20 µA VDD = 3.6V, VIL = 0.3V –0.3 –20 µA –0.9 –200 µA ±10 µA 12 25 mA 0.5 2.5 mA 10 µA 20 pF RST∗2 VDD = 3.6V, VIL = 0.3V IIZ PA to PK, MP, AN0 to AN3, CS, SI, SO, SCK, RST∗2 VDD = 5.5V, VI = 0, 5.5V Crystal oscillation (C1 = C2 = 15pF) of 12MHz VDD = 3.3V ± 0.3V∗4 VDD Sleep mode VDD = 3.3V ± 0.3V IDDS3 Typ. 2.7 IILR IDDS2 Min. VDD = 3.0V, IOH = –0.15mA IDD2 Supply current∗3 Condition PA to PE, PF4 to PF7, PH (VOL only) PI1 to PI7, PJ, SO, SCK, RST∗1 (VOL only) IIHE Input current (Ta = –10 to +75°C, Vss = 0V reference) Stop mode VDD = 5.5V Input capacity CIN Other than VDD, Clock 1MHz Vss, AVDD, and 0V other than the measured pins AVss pins 10 ∗1 RST pin specifies only when the power on reset circuit has been selected with mask option. ∗2 RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current when non-resistor is selected. ∗3 When entire output pins are open. ∗4 When setting upper 2 bits (CPU clock selection) of clock control register CLC (address: 00FEH) to "00" and operating in high speed mode (1/2 dividing clock). – 16 – CXP871P40 AC Characteristics (1) Clock timing Item (Ta = –10 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V reference) Symbol Pin Condition fC XTAL EXTAL Fig. 1, Fig. 2 System clock input pulse width tXL, tXH XTAL EXTAL VDD = 4.5 to 5.5V Fig. 1, Fig. 2 External clock drive System clock input rising and falling times tCR, tCF tEL, tEH tER, tEF XTAL EXTAL Fig. 1, Fig. 2 External clock drive Event count clock input rising and falling times 1 16 1 12 28 MHz ns tsys × 4∗1 Fig. 3 PE1/EC Unit 37.5 200 Fig. 3 PE1/EC Max. VDD = 4.5 to 5.5V System clock frequency Event count clock input pulse width Min. ns ns 20 ms ∗1 tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") 1/fc VDD – 0.4V XTAL EXTAL 0.4V tXH tCF tXL tCR Fig. 1. Clock timing AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA Crystal oscillation Ceramic oscillation EXTAL C1 External clock EXTAL XTAL C2 XTAL 74HC04 Fig. 2. Clock applied condition 0.8VDD EC 0.2VDD tEH tEF tEL Fig. 3. Event count clock timing – 17 – tER CXP871P40 (2) Serial transfer (CH0) Item (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol Pin Condition Min. Max. Unit CS ↓ → SCK delay time tDCSK SCK0 Chip select transfer mode (SCK = output mode) tsys + 200 ns CS ↑ → SCK floating delay time tDCSKF SCK0 Chip select transfer mode (SCK = output mode) tsys + 200 ns CS ↓ → SO delay time tDCSO SO0 Chip select transfer mode tsys + 200 ns CS ↓ → SO floating delay time tDCSOF SO0 Chip select transfer mode tsys + 200 ns CS high level width tWHCS CS0 Chip select transfer mode tsys + 200 ns SCK cycle time Input mode SCK0 2tsys + 200 ns tKCY 8000/fc ns SCK high and low level widths tKH tKL tsys + 100 ns SCK0 Output mode 8000/fc – 100 ns SI input setup time (against SCK ↑) SCK input mode SI0 –tsys + 100 ns tSIK 200 ns SI input hold time (against SCK ↑) SI0 2tsys + 100 ns tKSI 100 ns SCK ↓ → SO delay time tKSO SO0 Output mode Input mode SCK output mode SCK input mode SCK output mode SCK input mode SCK output mode 2tsys + 200 ns 100 ns Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) CS, SCK, SI and SO means each pin of CS → CS0, SCK → SCK0, SI → SI0, and SO → SO0 respectively. Note 3) The load of SCK output mode and SO output delay time is 50pF + 1TTL. – 18 – CXP871P40 Serial transfer (CH0) Item (Ta = –10 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V reference) Symbol Pin Condition Min. Max. Unit CS ↓ → SCK delay time tDCSK SCK0 Chip select transfer mode (SCK = output mode) tsys + 250 ns CS ↑ → SCK floating delay time tDCSKF SCK0 Chip select transfer mode (SCK = output mode) tsys + 200 ns CS ↓ → SO delay time tDCSO SO0 Chip select transfer mode tsys + 250 ns CS ↓ → SO floating delay time tDCSOF SO0 Chip select transfer mode tsys + 200 ns CS high level width tWHCS CS0 Chip select transfer mode tsys + 200 ns SCK cycle time Input mode SCK0 2tsys + 200 ns tKCY 8000/fc ns SCK high and low level widths tKH tKL tsys + 100 ns SCK0 Output mode 8000/fc – 150 ns SI input setup time (against SCK ↑) SCK input mode SI0 –tsys + 100 ns tSIK 200 ns SI input hold time (against SCK ↑) SI0 2tsys + 100 ns tKSI 100 ns SCK ↓ → SO delay time tKSO SO0 Output mode Input mode SCK output mode SCK input mode SCK output mode SCK input mode SCK output mode 2tsys + 250 ns 125 ns Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) CS, SCK, SI and SO means each pin of CS → CS0, SCK → SCK0, SI → SI0, and SO → SO0 respectively. Note 3) The load of SCK output mode and SO output delay time is 50pF. – 19 – CXP871P40 tWHCS CS0 0.8VDD 0.2VDD tKCY tDCSK tKL tDCSKF tKH 0.8VDD 0.8VDD SCK0 0.2VDD tSIK tKSI 0.8VDD Input data SI0 0.2VDD tDCSO tKSO tDCSOF 0.8VDD SO0 Output data 0.2VDD Fig. 4. Serial transfer timing (CH0) – 20 – CXP871P40 Serial transfer (CH1) (SI0 mode) Item Symbol (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Pin SCK1 cycle time tKCY SCK1 SCK1 high and low level widths tKH tKL SCK1 SI1 input setup time (against SCK1 ↑) tSIK SI1 SI1 input hold time (against SCK1 ↑) tKSI SI1 SCK1 ↓ → SO1 delay time tKSO SO1 Condition Min. Max. Unit 2tsys + 200 ns 16000/fc ns tsys + 100 ns 8000/fc – 50 ns SCK1 input mode 100 ns SCK1 output mode 200 ns tsys + 200 ns 100 ns Input mode Output mode Input mode Output mode SCK1 input mode SCK1 output mode SCK1 input mode SCK1 output mode tsys + 200 ns 100 ns Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL. Serial transfer (CH1) (SI0 mode) Item Symbol (Ta = –10 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V reference) Pin Condition tKCY SCK1 SCK1 high and low level widths tKH tKL SCK1 SI1 input setup time (against SCK1 ↑) tSIK SI1 SI1 input hold time (against SCK1 ↑) tKSI SI1 SCK1 ↓ → SO1 delay time tKSO SO1 Max. Unit 2tsys + 200 ns 16000/fc ns tsys + 100 ns 8000/fc – 150 ns SCK1 input mode 100 ns SCK1 output mode 200 ns tsys + 200 ns 100 ns Input mode SCK1 cycle time Min. Output mode Input mode Output mode SCK1 input mode SCK1 output mode SCK1 input mode SCK1 output mode tsys + 250 ns 125 ns Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF. – 21 – CXP871P40 tKCY tKL tKH 0.8VDD SCK1 0.2VDD tSIK tKSI 0.8VDD SI1 Input data 0.2VDD tKSO 0.8VDD SO1 Output data 0.2VDD Fig. 5. Serial transfer CH1 timing (SI0 mode) – 22 – CXP871P40 (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Serial transfer (CH1) (Special mode) Item Symbol Pin Condition Min. Typ. Max. Unit SO1 cycle time tLCY SO1 SI1 SI1 data setup time tLSU tLHD SI1 2 µs SI1 2 µs SI1 data hold time 104 Note 1) µs Note 1) tLCY specifies only serial mode register (CH1) (SIOM1: Address 01FAH) lower 2 bits (SO1 clock selection) has been set at 104µs. Note 2) The load of SO1 pin is 50pF + 1TTL. (Ta = –10 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V reference) Serial transfer (CH1) (Special mode) Item Symbol Pin Condition Min. Typ. Max. Unit SO1 cycle time tLCY SO1 SI1 SI1 data setup time tLSU tLHD SI1 2 µs SI1 2 µs SI1 data hold time 104 Note 1) µs Note 1) tLCY specifies only serial mode register (CH1) (SIOM1: Address 01FAH) lower 2 bits (SO1 clock selection) has been set at 104µs. Note 2) The load of SO1 pin is 50pF. Fig. 6. Serial transfer CH1 timing (Special mode) tLCY SO1 tLCY Start bit 0.5VDD Output data bit tLCY/2 tLSU tLHD Input data bit SI1 – 23 – 0.8VDD 0.2VDD CXP871P40 (3) A/D converter characteristics (Ta = –10 to +75°C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V reference) Item Symbol Pin Condition Min. Typ. Resolution Only for A/D converter operation Ta = 25°C VDD = AVDD = AVREF = 5.0V VSS = AVSS = 0V Linearity error Absolute error tCONV tSAMP Conversion time Sampling time Reference input voltage VREF Analog input voltage AVREF current AVREF VIAN 8 Bits ±1 LSB ±2 LSB µs 12/fADC µs VDD = AVDD = 4.5 to 5.5V AVDD – 0.5 0 Operating mode AVREF = 4.0 to 5.5V AVREF Unit 160/fADC AN0 to AN11 IREF Max. 0.6 Sleep mode Stop mode AVDD V AVREF V 1.0 mA 10 µA A/D converter characteristics (Ta = –10 to +75°C, VDD = AVDD = 3.0 to 3.6V, AVREF = 2.7 to AVDD, Vss = AVSS = 0V reference) Item Symbol Pin Condition Min. Typ. Resolution Only for A/D converter operation Ta = 25°C VDD = AVDD = AVREF = 3.3V VSS = AVSS = 0V Linearity error Absolute error tCONV tSAMP Conversion time Sampling time Reference input voltage VREF Analog input voltage AVREF current VIAN IREF 0 Operating mode AVREF = 2.7 to 3.6V 0.4 Sleep mode Stop mode Digital conversion value operation clock (MSC: Address 01FFH bit 0). When PS2 is selected, fADC = fc/2 When PS1 is selected, fADC = fc 01H 00H VFT Analog input Fig. 7. Definitions of A/D converter terms – 24 – ±1 LSB ±2 LSB µs ∗ The value of fADC is as follows by selecting ADC VZT Bits 12/fADC FFH FEH Linearity error 8 µs AN0 to AN11 AVREF Unit 160/fADC VDD=AVDD=3.0 to 3.6V AVDD – 0.3 AVREF Max. AVDD V AVREF V 0.7 mA 10 µA CXP871P40 (4) Interruption, reset input (Ta = –10 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V reference) Item Symbol Pin Condition External interruption high and low level widths tIH tIL INT0 INT1 INT2 PJ0 to PJ7 Reset input low level width tRSL RST Min. Unit 1 µs 32/fc µs tIH INT0 INT1 INT2 PJ0 to PJ7 (During standby release input) (Falling edge) Max. tIL 0.8VDD 0.2VDD Fig. 8. Interruption input timing tRSL RST 0.2VDD Fig. 9. Reset input timing (5) Power on reset Power on reset∗ (Ta = –10 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V reference) Item Symbol Pin tR tOFF Power supply rising edge Power supply cut-off time VDD Condition Power on reset Repetitive power on reset Min. Max. Unit 0.05 30 ms 1 ms ∗ Specifies only when power on reset function is selected. 3.0V VDD 0.2V 0.2V tR tOFF The power supply should rise smoothly. Fig. 10. Power on reset – 25 – CXP871P40 (6) General purpose prescaler (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item Symbol Pin Condition External clock input frequency fPCK PCK External clock input pulse width tWH, tWL tR, tF tPLH tPHL tTLH tTHL PCK External clock input rising and falling times Prescaler output delay time (against PCK ↑) Prescaler output rising and falling times Min. Typ. Max. Unit 12 MHz 33 ns PCK 200 ns PO External clock input PCK tR = tF = 6ns 80 130 ns 60 100 ns PO External clock input PCK tR = tF = 6ns 50 100 ns 20 40 ns Note) The load of PO pin is 50pF. General purpose prescaler (Ta = –10 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V reference) Item Symbol Pin Condition External clock input frequency fPCK PCK External clock input pulse width tWH, tWL tR, tF tPLH tPHL tTLH tTHL PCK External clock input rising and falling times Prescaler output delay time (against PCK ↑) Prescaler output rising and falling times Min. Typ. PCK MHz 200 ns PO External clock input PCK tR = tF = 6ns 130 220 ns 90 150 ns PO External clock input PCK tR = tF = 6ns 100 280 ns 30 70 ns tF 0.8VDD 0.5VDD 0.2VDD tR tWL tPLH tPHL 0.8VDD PO 12 ns 1/fPCK PCK Unit 33 Note) The load of PO pin is 50pF. tWH Max. 0.5VDD 0.2VDD tTLH tTHL Fig. 11. General purpose prescaler timing – 26 – CXP871P40 (7) Others (Ta = –10 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V reference) Item Symbol tCFH tCFL tDFH DFG input tDFL high and low level widths DPG minimum pulse width tDPW CFG input high and low level widths DPG minimum removal time trem PBCTL input high and low level widths tCTH tCTL tEIH tEIL tPIH tPIL tPSH tPSL EXI input high and low level widths PMI input high and low level widths PMSK input high and low level widths Pin Condition Min. Max. Unit CFG tFRC × 24 + 200 ns DFG tFRC × 8 + 200 ns DPG 50 ns DPG 50 ns PBCTL tsys = 2000/fc tFRC × 8 + tsys + 200 ns EXI0 EXI1 tsys = 2000/fc tFRC × 8 + tsys + 200 ns PMI tsys + 200 ns PMSK tsys + 200 ns Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) The value of tFRC is as follows by selecting FRC clock (FRCS: 01EEH bit 7) When PS0 is selected, tFRC = 1000/fc [ns] When PS1 is selected, tFRC = 2000/fc [ns] – 27 – CXP871P40 tCFH tCFL 0.8VDD CFG 0.2VDD tDFH DFG tDFL 0.8VDD 0.2VDD trem tDPW trem 0.8VDD DPG tCTH tCTL 0.8VDD PBCTL 0.2VDD tEIH EXI0 EXI0 tEIL 0.8VDD 0.2VDD Fig. 12. Other timings – 28 – CXP871P40 tPIH PMI tPIL 0.8VDD 0.2VDD tPSH PMSK tPSL 0.8VDD 0.2VDD – 29 – CXP871P40 Supplement AAAAA AAAAA AAAAA Main clock EXTAL XTAL Rd C2 C1 Fig. 13. Recommended oscillation circuit Manufacturer RIVER ELETEC CORPORATION Model fc (MHz) C1 (pF) C2 (pF) 8.00 10 10 5 5 22 (15) 22 (15) 12.00 15 15 16.00 12 12 10.00 HC-49/U03 12.00 Rd (Ω) Circuit example 0 (i) 0 (i) 16.00 8.00 KINSEKI LTD. HC-49/U (-S) 10.00 Mask Option Table Item CXP871P40Q-1CXP871P40R-1- Mask CXP871P40Q-2CXP871P40R-2- Reset pin pull-up resistor Non-existent/existent Existent Existent Power on reset circuit Non-existent/existent Existent Existent Genaral purpose prescaler oscillation circuit Non-existent/existent Non-existent Existent CMOS schmitt /TTL schmitt CMOS schmitt TTL schmitt Input circuit format∗1 ∗1 In PG4/SYNC0/PMI pin and PG5/SYNC1 pin, the input circuit format can be selected every pin. – 30 – CXP871P40 Characteristics Curve IDD vs. VDD IDD vs. fc (fc = 16MHz, Ta = 25°C, Typical) (VDD = 5V, Ta = 25°C, Typical) 1/4 dividing mode 10.0 1/16 dividing mode 5.0 Sleep mode 1.0 0.5 25 IDD – Supply current [mA] IDD – Supply current [mA] 1/2 dividing mode 20.0 20 1/2 dividing mode 15 1/4 dividing mode 10 1/16 dividing mode 5 0.1 Sleep mode 2 3 4 5 6 7 1 VDD – Supply voltage [V] 5 IDD vs. VDD IDD vs. fc 25 1/2 dividing mode 1/16 dividing mode 5.0 Sleep mode 1.0 0.5 IDD – Supply current [mA] IDD – Supply current [mA] (VDD = 3.3V, Ta = 25°C, Typical) 1/4 dividing mode 10.0 15 fc – System clock [MHz] (fc = 12MHz, Ta = 25°C, Typical) 20.0 10 20 15 1/2 dividing mode 10 1/4 dividing mode 5 0.1 1/16 dividing mode Sleep mode 2 3 4 5 6 7 1 VDD – Supply voltage [V] 5 10 fc – System clock [MHz] – 31 – 15 CXP871P40 Unit: mm 100PIN QFP (PLASTIC) 23.9 ± 0.4 + 0.4 20.0 – 0.1 + 0.1 0.15 – 0.05 80 51 + 0.4 14.0 – 0.1 17.9 ± 0.4 15.8 ± 0.4 50 81 A 31 100 1 0.65 30 + 0.15 0.3 – 0.1 0.13 + 0.2 0.1 – 0.05 + 0.35 2.75 – 0.15 M 0° to 10° DETAIL A 0.8 ± 0.2 (16.3) 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE QFP-100P-L01 LEAD TREATMENT SOLDER PLATING EIAJ CODE QFP100-P-1420 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 1.7g JEDEC CODE 100PIN LQFP (PLASTIC) 16.0 ± 0.2 ∗ 14.0 ± 0.1 75 51 76 (15.0) 50 0.5 ± 0.2 A 26 (0.22) 100 1 0.5 + 0.08 0.18 – 0.03 25 + 0.2 1.5 – 0.1 0.13 M + 0.05 0.127 – 0.02 0.1 0.1 ± 0.1 0° to 10° 0.5 ± 0.2 Package Outline DETAIL A NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING SONY CODE LQFP-100P-L01 LEAD TREATMENT EIAJ CODE LQFP100-P-1414 LEAD MATERIAL 42 ALLOY PACKAGE MASS 0.8g JEDEC CODE – 32 –