CXP82800 CMOS 8-bit Single Chip Microcomputer Description The CXP82800 is a CMOS 8-bit single chip microcomputer of piggyback/evaluator combined type, which is developed for evaluating the function of the CXP82832/82840/82852/82860. Piggyback/evaluator 100 pin PQFP (Ceramic) Features • Wide-range instruction system (213 instructions) to cover various types of data — 16-bit operation/multiplication and division/ Boolean bit operation instructions • Minimum instruction cycle 400ns at 10MHz operation 122µs at 32kHz operation • Applicable EPROM LCC type 27C512 (Maximum 60K bytes are available.) • Incorporated RAM capacity 1536 bytes (Including fluorescent display data area) • Peripheral functions — A/D converter 8-bit, 8-channel, successive approximation method (Conversion time of 32µs/10MHz) — Serial interface Incorporated 8-bit, 8-stage FIFO (Auto transfer for 1 to 8 bytes), 1 channel 8-bit clock sync type, 1 channel — Timers 8-bit timer 8-bit timer/counter 19-bit time base timer 16-bit capture timer/counter 32kHz timer/counter — Fluorescent display panel controller/driver Supports the universal grid fluorescent display panel. High voltage drive output port of 56 pins (40V) Maximum of 640 segments display possible Display timing number of 1 to 20 Dimmer function Incorporated pull-down resistor (Mask option) Hardware key scan function (Maximum 16 × 8 key matrix compatible) — Remote control receiving circuit 8-bit pulse measurement counter with on-chip 6-stage FIFO — PWM output 14 bits, 1 channel • Interruption 16 factors, 15 vectors, multi-interruption possible • Standby mode SLEEP/STOP • Package 100-pin ceramic PQFP Note) Mask option depends on the type of the CXP82800. Refer to the Products List for details. Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E96529-ST CXP82800 A20 A19 A18 A17 A16 G15/A15 G14/A14 VDD G13/A13 G12/A12 G11/A11 G10/A10 G9/A9 G8/A8 G7/A7 G6/A6 G5/A5 G4/A4 G3/A3 G2/A2 Pin Configuration in Piggyback Mode 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 2 79 A22 NC 3 78 A23 PE0/EC0/INT0 4 77 PH7/A24 PE1/EC1/INT1 5 76 PH6/A25 PE2/INT2 6 75 PH5/A26 PE3/INT3/NMI 7 74 PH4/A27 PE4/RMC 8 PE5 9 PE6/PWM 10 PE7/TO/ADJ 11 PC0/KR0 12 PC1/KR1 13 PC2/KR2 14 PC3/KR3 15 PC4/KR4 16 PC5/KR5 17 PC6/KR6 18 A12 NC 32 31 30 1 2 3 4 A13 G0/A0 A14 A21 VDD 80 A15 1 A7 G1/A1 A6 5 29 A8 A5 6 28 A9 A4 7 27 A11 A3 8 26 NC A2 9 25 OE A1 10 24 A10 A0 11 23 CE NC 12 22 D7 D0 13 21 D6 73 PH3/A28 72 PH2/A29 71 PH1/A30 70 PH0/A31 69 PG7/A32 68 PG6/A33 67 PG5/A34 66 PG4/A35 65 PG3/A36 64 PG2/A37 63 PG1/A38 62 PG0/A39 PC7/KR7 19 PB0/CINT 20 61 PF7/A40 PB1/CS0 21 60 PF6/A41 PB2/SCK0 22 59 PF5/A42 PB3/SI0 23 58 PF4/A43 D5 D4 D3 NC GND D2 D1 14 15 16 17 18 19 20 PB4/SO0 24 57 PF3/A44 PB5/SCK1 25 56 PF2/A45 PB6/SI1 26 55 PF1/A46 PB7/SO1 27 54 PF0/A47 AVREF 28 53 PD7/A48 PA0/AN0 29 52 PD6/A49 PA1/AN1 30 51 PD5/A50 PD4/A51 PD3/A52 PD2/A53 PD1/A54 PD0/A55 VFDP VDD TEX TX Vss XTAL EXTAL RST AVSS PA7/AN7 PA6/AN6 PA5/AN5 PA4/AN4 PA3/AN3 PA2/AN2 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note) 1. NC (Pin 3) is always connected to VDD. 2. VDD (Pins 44 and 89) are both connected to VDD. –2– CXP82800 A20 A19 A18 A17 A16 G15/A15 G14/A14 G13/A13 VDD G12/A12 G11/A11 G10/A10 G9/A9 G8/A8 G7/A7 G6/A6 G5/A5 G4/A4 G3/A3 G2/A2 Pin Configuration in Evaluator Mode 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 G1/A1 1 80 A21 G0/A0 2 79 A22 A23 77 PH7/A24 PE1/EC1/INT1 5 76 PH6/A25 PE2/INT2 6 75 PH5/A26 PE3/NT3/NMI 7 74 PH4/A27 A14 VDD NC A12 A13 78 A15 3 4 A7/D7 NC PE0/EC0/INT0 PE4/RMC 8 73 PH3/A28 PE5 9 72 PH2/A29 71 PH1/A30 PE6/PWM 10 PE7/TO/ADJ 11 PC0/KR0 12 PC1/KR1 13 PC2/KR2 14 PC3/KR3 15 PC4/KR4 16 PC5/KR5 17 PC6/KR6 18 1 2 3 4 32 31 30 A6/D6 5 29 A8 A5/D5 6 28 A9 A4/D4 7 27 A11 A3/D3 8 26 NC A2/D2 9 25 HALT A1/D1 10 24 A10 A0/D0 11 23 E/P NC 12 22 I/T RD 13 21 MON 70 PH0/A31 69 PG7/A32 68 PG6/A33 67 PG5/A34 66 PG4/A35 65 PG3/A36 64 PG2/A37 63 PG1/A38 62 PG0/A39 PC7/KR7 19 PB0/CINT 20 61 PF7/A40 PB1/CS0 21 60 PF6/A41 RST C1 C2 NC GND SYNC WR 14 15 16 17 18 19 20 PB2/SCK0 22 59 PF5/A42 PB3/SI0 23 58 PF4/A43 PB4/ SO0 24 57 PF3/A44 PB5/SCK1 25 56 PF2/A45 PB6/SI1 26 55 PF1/A46 PB7/SO1 27 54 PF0/A47 AVREF 28 53 PD7/A48 PA0/AN0 29 52 PD6/A49 PA1/AN1 30 51 PD5/A50 PD4/A51 PD3/A52 PD2/A53 PD1/A54 PD0/A55 VFDP VDD TEX TX Vss XTAL EXTAL RST AVSS PA7/AN7 PA6/AN6 PA5/AN5 PA4/AN4 PA3/AN3 PA2/AN2 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note) 1. NC (Pin 3) is always connected to VDD. 2. VDD (Pins 44 and 89) are both connected to VDD. –3– CXP82800 EPROM Read Timing (Ta = –20 to +75°C, Vcc = 4.5 to 5.5V, Vss = 0V reference) Item Symbol Pins Address → Data input delay time tACC A0 to A15 D0 to D7 Address → Data hold time tIH A0 to A15 D0 to D7 Min. Max. Unit 120 ns 0 ns 0.8VDD A0 to A15 Address data 0.2VDD tACC tIH 0.8VDD D0 to D7 Input data 0.2VDD Products List Products Option item Package ROM capacitance Mask Piggyback/evaluator CXP82832 CXP82840 CXP82852 CXP82860 CXP82800-U01Q 100-pin plastic QFP 32K bytes 40K bytes 52K bytes 60K bytes 100-pin ceramic PQFP EPROM 60K bytes Pull-up resistance for reset pin Existent/Non-existent Existent Pull-down resistance for high voltage drive pin Existent/Non-existent Existent: G0/A0 to A23 Non-existent: PD0/A55 to PH7/A24 –4– CXP82800 Piggyback mode/evaluator mode can be switched as shown below. Piggyback mode Piggyback/evaluator product Evaluator mode Pin 1 marking LCC type EPROM Pin 1 marking Pin 1 index Note) CPU Probe Note) Evaluation cap should be connected to CPU probe. –5– 24.7 INDEX PIN NO. 1 INDEX 22.3 ± 0.25 3.57 ± 0.36 30 1 31 100 15.58 ± 0.2 11.66 9.48 4.5 16.3 ± 0.2 18.7 50 81 51 80 100PIN PQFP (CERAMIC) 12.02 0.50 ± 0.25 Unit: mm 14.22 10.44 MAX 1.27 ± 0.13 0.3 + 0.05 0.15 – 0.02 –6– 1.0 0.45 JEDEC CODE AQFP100-C-0000-A 50 EIAJ CODE 51 80 81 PQFP-100C-L01 0.7 SONY CODE 1.3 ± 0.3 30 1 PIN No. 1 INDEX GOLD PLATING PACKAGE WEIGHT 5.7g 42 ALLOY LEAD TREATMENT LEAD MATERIAL CERAMIC PACKAGE MATERIAL PACKAGE STRUCTURE 31 100 0.65 ± 0.05 0.3 ± 0.08 18.12 ± 0.2 Package Outline CXP82800 6.0