CXP87800 CMOS 8-bit Single Chip Microcomputer Description The CXP87800 is a CMOS 8-bit single chip microcomputer of piggyback/evaluator combined type, which is developed for evaluating the function of the CXP87852/87860. Piggyback/ evaluator type 100 pin PQFP (Ceramic) Features • A wide instruction set (213 instructions) which QFP supported cover various types of data. — 16-bit operation/multiplication and division/ boolean bit operation instructions • Minimum instruction cycle 250ns at 16MHz operation (4.5 to 5.5V) • Applicable EPROM LCC type 27C512 (Maximum 60K bytes are available.) • Incorporated RAM capacity 2048 bytes • Peripheral functions — A/D converter 8-bit, 12-channel, successive approximation method (Conversion time of 20µs/16MHz) — Serial interface Buffer RAM 1 channel (Auto transfer for 1 to 32 bytes) 8-bit and 8-stage FIFO 1 channel (Auto transfer for 1 to 8 bytes) Incorporated two-wire 8-bit and 8-stage FIFO 1 channel (Auto transfer for 1 to 8 bytes) — Timer 8-bit timer, 8-bit timer/counter 19-bit time base timer, 32kHz timer/counter — High precision timing pattern generator PPG 19-pin, 32-stage programmable RTG 5 pins, 2 channels — PWM/DA gate output PWM output 12 bits, 2 channels (Repetitive frequency of 62.5kHz/16MHz) DA gate pulse output 13 bits, 4channels — Servo input control Capstan FG, drum FG/PG, CTL input — VSYNC separator — FRC capture unit Incorporated 26-bit and 8-stage FIFO — PWM output 14 bits — VISS/VASS circuit Pulse duty auto detection circuit — Remote control receiving circuit 8-bit pulse measurement counter with on-chip 6-stage FIFO — General purpose prescaler 7 bits (SYNC1 input frequency division, FRC capture possible.) — HSYNC counter 12-bit event counter (SYNC1 input count) • Interruption 23 factors, 15 vectors, multi-interruption possible • Standby mode SLEEP/STOP • Package 100-pin ceramic PQFP Note) Mask option depends on the type of the CXP87800. Refer to the Products List for details. Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E96213-PS CXP87800 PI5/SCK1 PI4/INT1/NMI PI3/TO/DDO/ADJ PI2/PWM PI1/RMC TEX TX Vss VDD NC PA7/PPO7 PA6/PPO6 PA5/PPO5 PA4/PPO4 PA3/PPO3 PA2/PPO2 PA1/PPO1 PA0/PPO0 PB7/PPO15 PB6/PPO14 Pin Assignment in Piggyback Mode (QFP package) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PB5/PPO13 1 80 PI6/SO1 PB4/PPO12 2 79 PI7/SI1 PB3/PPO11 3 78 PE0/INT0/CKOUT PB0/PPO8 6 75 PE3/PWM1 PC7/RTO7 7 74 PE4/DAA0 73 PE5/DAA1 VDD 8 A7 PC6/RTO6 A13 PE2/PWM0 A14 PE1/EC/INT2/HCOUT 76 NC 77 5 A15 4 PB1/PPO9 A12 PB2/PPO10 PC5/RTO5 9 72 PE6/DAB0 PC4/RTO4 10 71 PE7/DAB1 70 PG0/CFG 69 PG1/DFG 68 PG2/DPG 67 PG3/PBCTL 66 PG4/SYNC0 65 PG5/SYNC1 PC3/RTO3 11 PC2/PPO18 12 PC1/PPO17 13 PC0/PPO16 14 PJ7 15 PJ6 16 PJ5 17 PJ4 18 PJ3 4 2 1 32 31 30 A6 5 29 A8 A5 6 28 A9 A4 7 27 A11 A3 8 26 NC 25 9 A2 OE A1 10 24 A10 A0 11 23 CE NC 19 3 22 12 13 D0 D7 21 D6 64 PG6/EXI0 63 PG7/EXI1 62 AN0 PJ2 20 61 AN1 PJ1 21 60 AN2 PJ0 22 59 AN3 PD7 23 58 PF0/AN4 57 PF1/AN5 PD6 D5 D4 D3 NC GND D2 D1 14 15 16 17 18 19 20 24 PD5 25 56 PF2/AN6 PD4 26 55 PF3/AN7 PD3/SDA1 27 54 AVDD PD2/SDA0 28 53 AVREF PD1/SCL1 29 52 AVss PD0/SCL0 30 51 PF4/AN8 PF5/AN9 PF6/AN10 PF7/AN11 SO0 SCK0 SI0 CS0 EXTAL XTAL Vss RST MP PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note) 1. NC (Pin 90) is always connected to VDD. 2. VSS (Pins 41 and 88) are both connected to GND. 3. MP (Pin 39) is always connected to GND. –2– CXP87800 PI5/SCK1 PI4/INT1/NMI PI3/TO/DDO/ADJ PI2/PWM PI1/RMC TEX TX Vss VDD NC PA7/PPO7 PA6/PPO6 PA5/PPO5 PA4/PPO4 PA3/PPO3 PA2/PPO2 PA1/PPO1 PA0/PPO0 PB7/PPO15 PB6/PPO14 Pin Assignment in Evaluator Mode (QFP package) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PI6/SO1 79 PI7/SI1 PB3/PPO11 3 78 PE0/INT0/CKOUT PB2/PPO10 4 77 PE1/EC/INT2/HCOUT PB1/PPO9 5 76 PE2/PWM0 PB0/PPO8 6 75 PE3/PWM1 PC7/RTO7 7 74 PE4/DAA0 PC6/RTO6 8 73 PE5/DAA1 A14 VDD NC A12 A13 80 2 A15 1 PB4/PPO12 A7/D7 PB5/PPO13 PC5/RTO5 9 72 PE6/DAB0 PC4/RTO4 10 71 PE7/DAB1 70 PG0/CFG 69 PG1/DFG 68 PG2/DPG 67 PG3/PBCTL 66 PG4/SYNC0 65 PG5/SYNC1 11 PC2/PPO18 12 PC1/PPO17 13 PC0/PPO16 14 PJ7 15 PJ6 16 PJ5 17 PJ4 18 A6/D6 2 3 4 PC3/RTO3 1 32 31 30 29 5 6 A5/D5 A8 28 A9 A4/D4 7 27 A11 A3/D3 8 26 NC 25 9 A2/D2 HALT A1/D1 10 24 A10 A0/D0 11 23 E/P NC 22 12 I/T 64 PG6/EXI0 63 PG7/EXI1 62 AN0 61 AN1 PJ3 19 PJ2 20 PJ1 21 60 AN2 59 AN3 58 PF0/AN4 57 PF1/AN5 RST C1 C2 NC 24 GND PD6 MON 21 14 15 16 17 18 19 20 SYNC 22 23 13 WR PJ0 PD7 RD PD5 25 56 PF2/AN6 PD4 26 55 PF3/AN7 PD3/SDA1 27 54 AVDD PD2/SDA0 28 53 AVREF PD1/SCL1 29 52 AVss 30 51 PF4/AN8 PF5/AN9 PF6/AN10 PF7/AN11 SCK0 SI0 SO0 CS0 XTAL EXTAL Vss RST MP PH0 PH1 PH2 PH3 PH4 PH5 PH6 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PH7 PD0/SCL0 Note) 1. NC (Pin 90) is always connected to VDD. 2. VSS (Pins 41 and 88) are both connected to GND. 3. MP (Pin 39) is always connected to GND. –3– CXP87800 EPROM Read Timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Item Symbol Pin Min. Address → data input delay time tACC A0 to A15 D0 to D7 Address → data hold time tIH A0 to A15 D0 to D7 Max. 100∗1 75∗2 0 Unit ns ns ∗1 At 12MHz operation (VDD = 4.5 to 5.5V) ∗2 At 16MHz operation (VDD = 4.5 to 5.5V) 0.8VDD A0 to A15 Address data 0.2VDD tACC tIH 0.8VDD D0 to D7 Input data 0.2VDD Products List Products Option item Mask product CXP87852 Package ROM capacity Pull-up resistor for reset pin Input circuit format∗1 Piggyback/evaluator product CXP87860 CXP87800-U01Q 100-pin plastic QFP 52K bytes 100-pin ceramic PQFP EPROM 60K bytes 60K bytes 27C512 × 1 Existent/Non-existent Existent CMOS schmitt/TTL schmitt TTL schmitt ∗1 The input circuit format can be selected to PG4/SYNC0 and PG5/SYNC1, respectively. –4– CXP87800 Piggyback mode/evaluator mode can be switched as shown below. Piggyback mode Evaluator mode Piggyback/evaluator product Pin 1 marking LCC type EPROM Pin 1 marking Pin 1 index Note) CPU probe Note) Evaluation cap should be connected to CPU probe. –5– –6– 24.7 INDEX 22.3 ± 0.25 3.57 ± 0.36 30 1 31 100 15.58 ± 0.2 11.66 9.48 4.5 16.3 ± 0.2 18.7 50 81 51 80 100PIN PQFP (CERAMIC) 12.02 0.50 ± 0.25 PIN NO. 1 INDEX 14.22 10.44 MAX JEDEC CODE AQFP100-C-0000-A 0.45 EIAJ CODE 50 PQFP-100C-L01 0.7 SONY CODE 51 80 81 30 1 PIN No. 1 INDEX GOLD PLATING PACKAGE WEIGHT 5.7g 42 ALLOY LEAD TREATMENT LEAD MATERIAL CERAMIC PACKAGE MATERIAL PACKAGE STRUCTURE 31 100 0.65 ± 0.05 0.3 ± 0.08 18.12 ± 0.2 Unit: mm 1.0 1.3 ± 0.3 1.27 ± 0.13 0.3 + 0.05 0.15 – 0.02 Package Outline CXP87800 6.0