CXP84500 CMOS 8-bit Single Chip Microcomputer Description The CXP84500 is a CMOS 8-bit single chip microcomputer of piggyback/evaluator combined type, which is developed for evaluating the function of the CXP84540/84548. Piggyback/ evaluator 80 pin PQFP (Ceramic) Features • A wide instruction set (213 instructions) which covers verious types of data. – 16-bit operation/multiplication and division/Boolean bit operation instructions • Minimum instruction cycle 143ns at 28MHz operation (4.5 to 5.5V) 200ns at 20MHz (3.0 to 5.5V) • Applicable EPROM LCC type 27C512 (Maximum 60K bytes are available) • Incorporated RAM capacity 1472 bytes • Peripheral functions – A/D converter 8 bits, 8 channels, successive approximation method (Conversion time of 1.93µs at 28MHz/4.5 to 5.5V, 2.6µs at 20MHz/3.0 to 5.5V) – Serial interface Incorporated 8-bit, 8-stage FIFO (Auto transfer for 1 to 8 bytes,latch output function, MSB/LSB first selectable), 1 channel 8-bit clock sync type, 1 channel – Timer 8-bit timer/counter 19-bit time base timer 16-bit capture timer/counter – PWM output 8 bits, 2 channels • Interruption 14 factors, 14 vectors, multi-interruption possible • Standby mode SLEEP/STOP • Package 80-pin ceramic PQFP Note) Mask option depends on the type of the CXP84500. Refer to the Products List for details. Structure Silicon CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E96907A82 CXP84500 PI5 PI6 PI7 PG0 PG1 PG2 PG3 VDD NC PG4 PG5 PG6 PG7 PF0 PF1 PF2 Pin Assignment in Piggyback Mode 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 PI4 PF4 2 63 PI3/INT3 PF5 3 62 PI2/INT2 PF6 4 61 PI1/INT1 PF7 5 60 PI0/INT0 PD0 6 59 PE5/TO/PWM1 PD1 7 58 PE4/PWM0 PD2 8 PD3 9 A6 5 PD4 10 A5 PD5 11 PD6 12 PD7 13 A2 PC0 14 PC1 A14 VDD NC A12 A7 A13 1 A15 PF3 57 PE3/NMI 29 A8 56 PE2/CINT 6 28 A9 55 PE1/EC1 A4 7 27 A11 54 PE0/EC0 A3 8 26 NC 53 PB7/SO1 9 25 OE 52 PB6/SI1 A1 10 24 A10 51 PB5/SCK1 15 A0 11 23 CE 50 PB4/SO0 PC2 16 NC 12 22 D7 49 PB3/SI0 PC3 17 21 D6 48 PB2/SCK0 PC4 18 47 PB1/CS0 PC5 19 46 PB0/LAT0 PC6 20 45 PA7/AN7 PC7 21 44 PA6/AN6 PH0 22 43 PA5/AN5 PH1 23 42 PA4/AN4 PH2 24 41 PA3/AN3 4 D0 32 31 30 1 2 3 13 D5 D4 D3 NC GND D2 D1 14 15 16 17 18 19 20 PA2/AN2 PA1/AN1 PA0/AN0 AVREF AVSS PE7 PE6 VSS XTAL RST EXTAL PH7 PH6 PH5 PH4 PH3 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Note) NC (pin 73) is left open. However, this pin is used for the Flash EEPROM incorporated version (CXP845F60). –2– CXP84500 PI5 PI6 PI7 PG0 PG1 PG2 PG3 VDD NC PG4 PG5 PG6 PG7 PF0 PF1 PF2 Pin Assignment in Evaluator Mode 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 PI3/INT3 PF5 3 62 PI2/INT2 PF6 4 61 PI1/INT1 PF7 5 60 PI0/INT0 PD0 6 59 PE5/TO/PWM1 PD1 7 58 PE4/PWM0 57 PE3/NMI VDD A13 63 A14 2 NC PI4 PF4 A15 64 A12 1 A7/D7 PF3 PD2 8 PD3 9 A6/D6 5 29 A8 56 PE2/CINT PD4 10 A5/D5 6 28 A9 55 PE1/EC1 PD5 11 A4/D4 7 27 A11 54 PE0/EC0 PD6 12 A3/D3 8 26 NC 53 PB7/SO1 PD7 13 A2/D2 9 25 HALT 52 PB6/SI1 PC0 14 A1/D1 10 24 A10 51 PB5/SCK1 PC1 15 A0/D0 11 23 E/P 50 PB4/SO0 PC2 22 I/T 49 PB3/SI0 21 MON 48 PB2/SCK0 47 PB1/CS0 4 1 2 3 32 31 30 16 NC 12 PC3 17 RD 13 PC4 18 PC5 19 46 PB0/LAT0 PC6 20 45 PA7/AN7 PC7 21 44 PA6/AN6 PH0 22 43 PA5/AN5 PH1 23 42 PA4/AN4 PH2 24 41 PA3/AN3 RST C1 C2 NC GND SYNC WR 14 15 16 17 18 19 20 PA2/AN2 PA1/AN1 PA0/AN0 AVREF PE7 AVSS PE6 VSS XTAL EXTAL RST PH7 PH6 PH5 PH4 PH3 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Note) NC (pin 73) is left open. However, this pin is used for the Flash EEPROM incorporated version (CXP845F60). –3– CXP84500 EPROM Read Timing (Ta = –20 to +75°C, VDD = 3.0 to 5.5V, VSS = 0V reference) Item Symbol Pin Address → data input delay time tACC A0 to A15 D0 to D7 Address → data hold time tIH A0 to A15 D0 to D7 Min. Max. 60∗1 Unit ns 40∗2 0 ns ∗1 At 20MHz operation (VDD = 4.5 to 5.5V). The CXP27C700K is recommended. ∗2 At 20MHz operation (VDD = 3.0 to 5.5V) and 28MHz operation (VDD = 4.5 to 5.5V). The CXP27V700K is recommended. 0.8VDD A0 to A15 Address data 0.2VDD tACC tIH 0.8VDD D0 to D7 Input data 0.2VDD Product List Products Mask Piggyback/evaluator Option item CXP84540 Package ROM capacity CXP84548 80-pin plastic QFP 40K bytes 48K bytes Reset pin pull-up resistor Existent/Non-existent Power-on reset circuit Existent/Non-existent CXP84500-U01Q CXP84500-U01R∗1 80-pin ceramic PQFP EPROM 60K bytes Existent Existent∗2 ∗1 LQFP package conversion adopter used.(SEK-80Q-65MM; attached for piggyback/evaluator) ∗2 Take the reset time which is more than the oscillation stabilization time by the external reset circuit because the power-on reset operation cannot be guaranteed for VDD = 3.0 to 4.5V. –4– CXP84500 Piggyback mode/evaluator mode can be switched as shown below. Piggyback mode Evaluator mode Piggyback/evaluator product Pin 1 marking Pin 1 index LCC type EPROM Pin 1 marking Note) CPU probe Note) Evaluation cap should be connected to CPU probe. Package Outline Unit: mm 80PIN PQFP (CERAMIC) PIN No. 1 INDEX 18.7 16.3 ± 0.2 INDEX 80 65 65 64 PIN No. 1 INDEX 1 64 0.8 ± 0.05 1 80 0.4 ± 0.08 14.22 18.12 ± 0.2 1.27 ± 0.13 12.02 0.7 1.0 0.3 6.0 24 40 9.48 24 41 1.3 ± 0.3 41 25 40 25 0.6 11.66 15.58 ± 0.2 PACKAGE STRUCTURE PACKAGE MATERIAL + 0.05 0.15 – 0.02 9.59 MAX –5– CERAMIC SONY CODE PQFP-80C-L01 LEAD TREATMENT GOLD PLATING EIAJ CODE AQFP080-C-0000-A LEAD MATERIAL 42 ALLOY PACKAGE WEIGHT 5.7g JEDEC CODE 3.57 ± 0.36 24.7 22.3 ± 0.25 4.5