SONY CXP5080

CXP5080
Piggyback/
CMOS 4-bit Single Chip Microcomputer
evaluator type
For the availability of this product, please contact the sales office.
Description
CXP5080 is a CMOS 4-bit single chip microcomputer
of piggyback/evaluator combined type which has
been developed for functional evaluation of the
CXP5084/5086.
64 pin PSDIP (Ceramic)
64 pin PQFP (Ceramic)
Features
• Instruction cycle
•
•
•
•
•
•
•
•
•
•
•
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3.8µs/4.19MHz (CXP5080)
1.9µs/4.19MHz (CXP5080H)
ROM capacity
Maximum 8K bytes (EPROM 27C64, LCC/DIP type 27C64)
RAM capacity
400 × 4 bits (Including stack, display area)
32 general purpose I/O ports
16 large current output ports
LCD controller/driver (Enables to direct drive)
— Enables to specify the segment output of 24, 20 and 16 optionally
— Enables to select program of the duty, 1/2, 1/3 and 1/4
— 1/3 bias
2 external interruption input pins
8-bit timer, 8-bit timer/event counter and 18-bit time base timer, independently controlled
Arithmetic and logical operations possible between the entire RAM area, l/O area and the accumulator by
means of memory mapped I/O
Reference to the entire ROM area is possible with the table look-up instruction
2 kinds of power down modes of sleep and stop
Power on reset circuit (mask option)
The oscillation circuit may be optionally specified as the crystal oscillation type or the CR oscillation type
64-pin ceramic SDIP/QFP
Note) Mask options are determined according to the CXP5080 category.
For details refer to the product list.
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E61113A7Z-PS
CXP5080
Block Diagram
(Enables to specify
the I/O with bit unit)
Port A
(Enables to specify
the I/O with port unit)
Port B
(Combined use of mask
with segment output, optional.)
4
4
4
4
Port C
Port D
Port E
Port F
Register
Program
counter (13)
ALU
Accumulator
Flag
Data memory
Address buffer
400 × 4
bits
13
Timer (8)
A0 to A12
I0 to I7
8
Stack
Timer/counter (8)
Serial I/O (8)
Data memory
Instruction
input buffer
Interruption control
Instruction control
Time base timer (18)
LCD
controller/driver
VL
VLC1
VLC2
VLC3
EXTAL
Port X
XTAL
(Combined use of serial I/O)
–2–
RST
VSS
VDD
WP
INT1
PY0
PY1
PY2/INT2
PX3/EC
PX0/SC
SEG16 SEG0 COM0
to
to
to
SEG23 SEG15 COM3
PX2/SOA
4
PX1/SOB
16
PX3/SI
8
Clock control
Port Y
CXP5080
Pin Assignment 1 (Top View) 64 pin PSDIP Package
Note)
VL
1
64
VDD
XTAL
2
63
VLC3
EXTAL
3
62
VLC2
RST
4
61
VLC1
WP
5
60
COM0
INT1
6
59
COM1
PY0
7
58
COM2
PY1
8
57
COM3
PY2/INT2
9
56
SEG0
PY3/EC
10
55
SEG1
PX0/SC
11
54
SEG2
PX1/SOB
12
53
SEG3
PX2/SOA
13
52
SEG4
PX3/SI
14
51
SEG5
PD0
15
50
SEG6
PD1
16
49
SEG7
PD2
17
48
SEG8
47
SEG9
46
SEG10
1
VDD
VDD 28
2
A12
VDD 27
3
A7
VDD 26
4
A6
A8 25
5
A5
A9 24
6
A4
A11 23
7
A3
VSS 22
8
A2
A10 21
9
A1
VSS 20
10 A0
I7 19
11 I0
I6 18
12 I1
I5 17
13 I2
I4 16
PD3
18
PC0
19
PC1
20
45
SEG11
PC2
21
44
SEG12
PC3
22
43
SEG13
PB0
23
42
SEG14
PB1
24
41
SEG15
PB2
25
40
SEG16/PF0
PB3
26
39
SEG17/PF1
PA0
27
38
SEG18/PF2
PA1
28
37
SEG19/PF3
PA2
29
36
SEG20/PE0
PA3
30
35
SEG21/PE1
PESEL
31
34
SEG22/PE2
VSS
32
33
SEG23/PE3
14 VSS
I3 15
PESEL pin serves to switch the I/O signal of the socket on top of the package from interface with the
evaluator (Eva mode) to interface with EPROM (Piggyback mode).
Setting PESEL pin to H Ievel brings Eva mode to enable the connection with the evaluator. Setting it to
L level brings piggyback mode to enable the mounting of EPROM. For QFP piggyback, it is necessary
only to exchange EVACAP (or EPROM) for EPROM (or EVACAP) and no other special measures are
required.
–3–
CXP5080
COM2
COM1
COM0
VLC1
VLC3
VLC2
VL
VDD
XTAL
EXTAL
RST
WP
INT1
Pin Assignment 2 (Top View) 64 pin PQFP Package
64 63 62 61 60 59 58 57 56 55 54 53 52
PY2/INT2
3
49
SEG1
PY3/EC
4
48
SEG2
3
2
1 32 31 30
VDD
4
VDD
PESEL
SEG0
PESEL
COM3
50
VDD
51
2
A12
1
PY1
A7
PY0
PX0/SC
5
47
SEG3
PX1/SOB
6
A6 5
29 A8
46
SEG4
PX2/SOA
7
A5 6
28 A9
45
SEG5
PX3/SI
8
A4 7
27 A11
44
SEG6
PD0
9
A3 8
26 NC
43
SEG7
PD1
10
A2 9
25 VSS
42
SEG8
PD2
11
A1 10
24 A10
41
SEG9
PD3
12
A0 11
23 VSS
40
SEG10
PC0
13
NC 12
22 I7
39
SEG11
PC1
14
I0 13
21 I6
38
SEG12
PC2
15
37
SEG13
PC3
16
PB0
17
PB1
PB2
14 15 16 17 18 19 20
I5
SEG17/PF1
I4
SEG16/PF0
33
I3
34
19
NC
18
VSS
SEG15
I2
SEG14
35
I1
36
SEG18/PF2
SEG19/PF3
SEG20/PE0
SEG21/PE1
SEG22/PE2
SEG23/PE3
NC
VSS
PA3
PA2
PA1
PA0
PB3
20 21 22 23 24 25 26 27 28 29 30 31 32
Note 1) PESEL pin serves to switch the I/O signal of the socket on top of the package from interface with the
evaluator (Eva mode) to interface with EPROM (Piggyback mode).
Setting PESEL pin to H Ievel brings Eva mode to enable the connection with the evaluator. Setting it to
L level brings piggyback mode to enable the mounting of EPROM. For QFP piggyback, it is necessary
only to exchange EVACAP (or EPROM) for EPROM (or EVACAP) and no other special measures are
required.
Note 2) Do not make any connections to NC pin.
–4–
CXP5080
EPROM read timing
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, VSS = 0V reference)
Item
Min.
Pin
Symbol
Address → Data
input delay time
tACC
A0 to A12
I0 to I7
Address → input
holding time
tIH
A0 to A12
I0 to I7
Max.
Unit
300
ns
0
ns
0.8VDD
A0 to A12
Address data
0.2VDD
tACC
tIH
0.8VDD
I0 to I7
Input data
0.2VDD
Products List
Optional item
Mask ROM
CXP5086
CXP5080HU02AS CXP5080HU03AS CXP5080HU04AS
CXP5080HU02AQ CXP5080HU03AQ CXP5080HU04AQ
Package
64-pin plastic
SDIP/QFP
64-pin ceramic
PSDIP/PQFP
64-pin ceramic
PSDIP/PQFP
64-pin ceramic
PSDIP/PQFP
ROM capacity
6K byte
EPROM 8K byte
EPROM 8K byte
EPROM 8K byte
Speed
Standard/High speed
High speed
High speed
High speed
Oscillation type
Crystal/CR
Crystal
Crystal
Crystal
Segment output
16/20/24
20
24
16
Output type
Tri-state/
Pull-up resistance/
Open drain
Tri-state
Tri-state
Tri-state
PY0 and PY1
output type
Pull-up resistance/
Inverter
Pull-up resistance
Pull-up resistance
Pull-up resistance
Output state during
Holding state/Hi-Z
standby
Hi-Z
Hi-Z
Hi-Z
Pull-up resistance
of reset pin
Existent/non-existent
Existent
Existent
Existent
Incorporated power
Existent/non-existent
on reset circuit
Existent
Existent
Existent
SOA pin output
Normal/Input
Input
Input
Input
SOB pin output
Normal/Input
Normal
Normal
Normal
Note) All of the above products are combined chips of piggyback and evaluator.
–5–
CXP5080
Package Outline
Unit: mm
64PIN PSDIP (CERAMIC) 750mil
+ 0.74
57.0 – 0.53
0° to 9°
33
32
0.25 ±
0.05
1
19.05 ± 0.3
15.24
18.76 ± 0.29
64
0.48 ± 0.1
3.4 ± 0.3
1.27 ± 0.25
10.16 MAX
2.54 ± 0.25
1.778 ± 0.2
0.9 ± 0.2
SONY NAME
PSDIP-64C-021
EIAJ NAME
ADIP064-C-0750-AF
JEDEC CODE
64PIN PQFP (CERAMIC)
PIN No.1 INDEX
18.7
16.3 ± 0.2
INDEX
64
PIN No.1 INDEX
52
52
64
51
1
1
1.0 ± 0.05
51
0.4 ± 0.08
14.22
18.12 ± 0.2
1.27 ± 01.3
12.02
1.0
0.3
6.0
20
1.3 ± 0.3 1.5
33
19
32
9.48
33
19
32
20
0.7
11.66
SONY NAME
PQFP-64C-L01
EIAJ NAME
AQFP054-C-0000-A
JEDEC CODE
9.32 MAX
+ 0.05
0.15 – 0.02
15.58 ± 0.2
3.07 ± 0.3
24.7
22.3 ± 0.3
4.5
–6–