CXP84220/84224 CMOS 8-bit Single Chip Microcomputer Description The CXP84220/84224 is a CMOS 8-bit single chip microcomputer integrating on a single chip an A/D converter, serial interface, timer/counter, time base timer, capture timer counter, remote control reception circuit besides the basic configurations of 8-bit CPU, ROM, RAM, and l/O port. The CXP84220/84224 also provides a power-on reset function and a sleep/stop function that enables lower power consumption. 64 pin SDIP (Plastic) Features • Wide-range instruction system (213 instructions) to cover various types of data —16-bit arithmetic/multiplication and division/Boolean bit operation instructions • Minimum instruction cycle 400ns at 10MHz operation • Incorporated ROM capacity 20K bytes (CXP84220) 24K bytes (CXP84224) • Incorporated RAM capacity 624 bytes • Peripheral functions —A/D converter 8-bit, 8-channel, successive approximation method (Conversion time of 32µs/10MHz) —Serial interface SIO with 8-bit, 8-stage FIFO incorporated for data use (Auto transfer for 1 to 8 bytes), 1 channel 8-bit standard SIO, 1 channel —Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer, 16-bit capture timer/counter —Remote control reception circuit Incorporated noise elimination circuit Incorporated 8-bit, 6-stage FIFO for measurement data —PWM output circuit 14 bits, 1 channel • Interruption 13 factors, 14 vectors, multi-interruption possible • Standby mode Sleep/stop • Package 64-pin plastic SDIP • Piggyback/evaluation chip CXP84200 64-pin ceramic SDIP Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E93236A81-PS –2– PE5/TO PB0/CINT PE1/EC1 16 BIT CAPTURE TIMER/COUNTER 2 8 BIT TIMER 1 PE0/EC0 FIFO FIFO 8 BIT TIMER/COUNTER 0 SERIAL INTERFACE UNIT 0 REMOCON 14 BIT PWM GENERATOR A/D CONVERTER AVss SERIAL INTERFACE UNIT 1 8 2 2 2 PI0/INT0 PI1/INT1 PI2/INT2 PI3/INT3 2 INTERRUPT CONTROLLER AVREF PB6/SI1 PB7/SO1 PB5/SCK1 PB1/CS0 PB3/SI0 PB4/SO0 PB2/SCK0 PE2/RMC PE4/PWM PA0/AN0 to PA7/AN7 PRESCALER / TIME BASE TIMER ROM 20K/24K BYTES SPC700 CPU CORE RST VDD Vss EXTAL XTAL RAM 624 BYTES CLOCK GEN./ SYSTEM CONTROL PORT G PORT F PORT E PORT D PORT C PORT B PORT A PORT I Block Diagram PE4 to PE5 PF0 to PF7 PG0 to PG2 2 8 3 PI0 to PI6 PE0 to PE3 4 7 PD0 to PD7 PC0 to PC7 PB7 PB0 to PB6 PA0 to PA7 8 8 7 8 CXP84220/84224 PE3/NMI CXP84220/84224 Pin Assignment (Top View) NC 1 64 VDD PG0 2 63 PI6 PG1 3 62 PI5 PG2 4 61 PI4 PF0 5 60 PI3/INT3 PF1 6 59 PI2/INT2 PF2 7 58 PI1/INT1 PF3 8 57 PI0/INT0 PF4 9 56 PE5/TO PF5 10 55 PE4/PWM PF6 11 54 PE3/NMI PF7 12 53 PE2/RMC PD0 13 52 PE1/EC1 PD1 14 51 PE0/EC0 PD2 15 50 PB7/SO1 PD3 16 49 PB6/SI1 PD4 17 48 PB5/SCK1 PD5 18 47 PB4/SO0 PD6 19 46 PB3/SI0 PD7 20 45 PB2/SCK0 PC0 21 44 PB1/CS0 PC1 22 43 PB0/CINT PC2 23 42 PA7/AN7 PC3 24 41 PA6/AN6 PC4 25 40 PA5/AN5 PC5 26 39 PA4/AN4 PC6 27 38 PA3/AN3 PC7 28 37 PA2/AN2 RST 29 36 PA1/AN1 XTAL 30 35 PA0/AN0 EXTAL 31 34 AVREF Vss 32 33 AVss Note) NC (Pin 1) is always connected to VDD. –3– CXP84220/84224 Pin Description Pin code I/O PA0/AN0 to PA7/AN7 I/O/Analog input PB0/CINT I/O/Input PB1/CS0 I/O/Input PB2/SCK0 I/O/I/O PB3/SI0 I/O/Input PB4/SO0 I/O/Output PB5/SCK1 I/O/I/O PB6/SI1 I/O/Input PB7/SO1 Output/Output Description (Port A) 8-bit l/O port. l/O can be set in a unit of single bit. Incorporation of the pull- Analog inputs to A/D converter. up resistance can be set (8 pins) through the software in a unit of 4 bits. (8 pins) (Port B) 7-bit l/O port in which l/O can be set in a unit of single bit. Also, an uppermost bit (PB7) exclusively for output. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) External capture input to 16-bit timer/counter. Chip select input for serial interface (CH0). Serial clock l/O (CH0). Serial data input (CH0). Serial data output (CH0). Serial clock l/O (CH1). Serial data input (CH1). Serial data output (CH1). I/O (Port C) 8-bit l/O port. l/O can be set in a unit of single bit. Capable of driving 12mA sink current. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) PD0 to PD7 I/O (Port D) 8-bit l/O port. l/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits. (8 pins) PE0/EC0 Input/Input PE1/EC1 Input/Input PE2/RMC Input/Input PE3/NMI Input/Input PE4/PWM Output/Output PE5/TO Output/Output PC0 to PC7 PF0 to PF7 PG0 to PG2 External event inputs for timer/counter. (2 pins) (Port E) 6-bit port. Lower 4 bits are for inputs; upper 2 bits are for outputs. (6 pins) Remote control reception circuit input. Non-maskable interruption request input. 14-bit PWM output. Rectangular wave output for 16-bit timer/counter. I/O (Port F) 8-bit output port. I/O can be set in a unit of single bit. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) I/O (Port G) 8-bit I/O port. I/O can be set in a unit of single bit. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (3 pins) –4– CXP84220/84224 Pin code Description I/O (Port l) External 7-bit output ports. I/O can be set in a unit of single bit. interruption Incorporation of pull-up resistor can be set through request inputs. the software in a unit of 4 bits. (7 pins) PI0/INT0 to PI3/INT3 I/O/Input PI4 to PI6 I/O EXTAL Input XTAL Output Crystal connectors for system clock oscillation. When the clock is supplied externally, input to EXTAL; opposite phase clock should be input to XTAL. RST I/O Low-level active, system reset. NC. Under normal operating conditions, connect to VDD. NC AVREF Input Reference voltage input for A/D converter. AVss A/D converter GND. VDD Positive power supply. Vss GND –5– CXP84220/84224 Input/Output Circuit Formats for Pins Pin Port A AAA AAA AAA AAA AAA AAA AAA Circuit format When reset ∗ Pull-up resistance "0" when reset AA AA AA Port A data PA0/AN0 to PA7/AN7 Port A direction Input protection circuit IP "0" when reset Data bus Hi-Z RD (Port A) Port A input selection "0" when reset 8 pins Port B Input multiplexer A/D converter AAA AAA AAA AAA AAA ∗ Pull-up transistors approx. 10kΩ ∗ Pull-up resistance "0" when reset AA AA AA Port B data PB0/CINT PB1/CS0 PB3/SI0 PB6/SI1 Port B direction IP "0" when reset Hi-Z Schmitt input Data bus RD (Port B) CINT CS0 SI0 SI1 4 pins Port B AAAA AAAA AAAA AAAA AAAA AAAA AAAA ∗ Pull-up transistors approx. 10kΩ ∗ Pull-up resistance "0" when reset SCK OUT Output enable AA AA AA Port B output selection PB2/SCK0 PB5/SCK1 "0" when reset IP Port B data Port B direction "0" when reset Data bus Schmitt input RD (Port B) 2 pins SCK in –6– ∗ Pull-up transistors approx. 10kΩ Hi-Z CXP84220/84224 Pin Port B AAAA AAAA AAAA AAAA AAAA AAAA AAAA Circuit format When reset ∗ Pull-up resistance SO Output enable AA AA AA Port B output selection "0" when reset PB4/SO0 IP Port B data Port B direction Hi-Z "0" when reset Data bus RD (Port B) ∗ Pull-up transistors approx. 10kΩ 1 pin Port B Internal reset signal SO AAAA AAAA AAAA AA Output enable PB7/SO1 ∗ Port B output selection "1" when reset High level Port B data ∗ Pull-up transistors approx. 200kΩ Data bus 1 pin RD (Port B) Port C AAAA AAAA AAAA AAAA AAAA ∗2 Pull-up resistance "0" when reset Port C data PC0 to PC7 ∗1 Port C direction "0" when reset Data bus AA A AA A IP RD (Port C) 8 pins ∗1 Large current drive of ∗2 Pull-up transistors 12mA possible approx. 10kΩ –7– Hi-Z CXP84220/84224 Pin Circuit format Port E PE0/EC0 PE1/EC1 PE2/RMC PE3/NMI AA AA AAAA AAAA AAAA AAAA AAAA When reset Schmitt input EC0 EC1 RMC/NMI IP 4 pins Port E RD (Port E) PWM Port E output selection PE4/PWM "0" when reset Port E data 1 pin "1" when reset Data bus Hi-Z Data bus AA AA High level RD (Port E) Port E AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA Output enable TO PE5/TO Port E output selection Port E output selection "00" when reset Port E output selection "0" when reset AA AA Port E data 1 pin "1" when reset Data bus RD (Pot E) Port D ∗ Pull-up resistance Port F "0" when reset Port G PD0 to PD7 PF0 to PF7 PG0 to PG2 PI4 to PI6 High level Port data Port I Port direction "0" when reset Data bus A AA A AA IP RD ∗ Pull-up transistors approx. 10kΩ 22 pins –8– Hi-Z CXP84220/84224 Pin AAAA AAAA AAAA AAAA AAAA A A AA AA INT0 INT1 INT2 INT3 ∗ Pull-up transistors approx. 10kΩ When reset Circuit format Port I ∗ Pull-up resistance "0" when reset Port data PI0 to PI3 Port direction IP "0" when reset Data bus RD 4 pins EXTAL XTAL 2 pins AA AA AA AA EXTAL AA AA AA AA IP IP • Diagram shows circuit composition during oscillation • Feedback resistor is removed during stop. Oscillation XTAL Pull-up resistor AA Mask option OP RST Hi-Z AA IP Schmitt input Power-on reset function (Mask option) 1 pin –9– Low level CXP84220/84224 Absolute Maximum Ratings Item Supply voltage (VSS = 0V reference) Symbol Rating Unit VDD –0.3 to +7.0 V AVSS V Remarks Input voltage VIN –0.3 to +0.3 –0.3 to +7.0∗1 Output voltage VOUT –0.3 to +7.0∗1 V High level output current IOH –5 mA Output per pin –50 mA Total for all output pins IOL 15 mA IOLC 20 mA Value per pin, excluding large current outputs Value per pin∗2 for large current outputs Low level total output current ∑IOL 100 mA Total for all output pins High level total output current ∑IOH Low level output current V Operating temperature Topr –20 to +75 °C Storage temperature Tstg –55 to +150 °C Allowable power dissipation PD 1000 mW ∗1 VIN and VOUT must not exceed VDD + 0.3V. ∗2 The large current drive transistor is the N-ch transistor of Port C (PC). Note) Usage exceeding absolute maximum ratings may permanently impair the LSl. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI. Recommended Operating Conditions Item Supply voltage High level input voltage Symbol VDD Operating temperature Min. Max. 4.5 5.5 V 5.5 2.5 5.5 VIH 0.7VDD VDD V VIHS 0.8VDD VDD V VDD – 0.4 VDD + 0.3 Remarks Unit 3.5 VIHEX Low level input voltage (VSS = 0V reference) High-speed mode guaranteed operation range∗1 Low-speed mode guaranteed operation range∗1 Guaranteed data hold range during stop ∗2 V Hysteresis input∗3 EXTAL∗4 ∗2 VIL 0 0.3VDD V VILS 0 0.2VDD V VILEX –0.3 0.4 V Topr –20 +75 °C Hysteresis input∗3 EXTAL∗4 ∗1 High-speed mode is 1/2 frequency demultiplication clock selection; Iow-speed mode is 1/16 frequency demultiplication clock selection. ∗2 Value for each pin of normal input ports (PA, PB3, PB4, PB6, PC, PD, PF, PG, PI4 to PI6). ∗3 Value of the following pins: RST, CINT, CS0, SCK0, SCK1, EC0, EC1, RMC, NMI, INT0, INT1, INT2, INT3. ∗4 Specifies only during external clock input. – 10 – CXP84220/84224 Electrical Characteristics (Ta = –20 to +75°C, Vss = 0V reference) DC Characteristics Item Symbol High level VOH output voltage Low level output voltage Pins PA to PD, PE4, PE5, PF, PG, PI VOL PC IIHE IILE Input current I/O leakage current EXTAL Conditions Min. VDD = 4.5V, IOH = –0.5mA 4.0 V VDD = 4.5V, IOH = –1.2mA 3.5 V 0.4 V VDD = 4.5V, IOL = 3.6mA 0.6 V VDD = 4.5V, IOL = 12.0mA 1.5 V VDD = 5.5V, VIH = 5.5V 0.5 40 µA VDD = 5.5V, VIL = 0.4V –0.5 –40 µA VDD = 5.5V VIL = 0.4V –1.5 –400 µA –2.0 mA RST∗1 IIL PA to PD∗2, PF, PG, PI∗2 VDD = 4.5V, VIL = 4.0V PE0 to PE3, RST∗1 Supply current∗3 –10 µA VDD = 5.5V VI = 0, 5.5V High-speed mode operation (1/2 frequency demultiplier clock) IDD1 Max. Unit VDD = 4.5V, IOL = 1.8mA IILR IIZ Typ. VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF) ±10 µA 18 40 mA 1.1 8 mA 10 µA 20 pF Sleep mode IDDS1 VDD VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF) Stop mode IDDS3 Input capacity CIN VDD = 5.5V, termination of 10MHz crystal oscillation Pins other than PB7, PE4, PE5, AVREF, AVss, VDD, VSS Clock 1MHz 0V for all pins excluding measured pins 10 ∗1 RST specifies the input current when pull-up resistance has been selected; Ieakage current wnen no resistance has been selected. ∗2 Pins PA to PD, and PF, PG, Pl specify the input current when pull-up resistance has been selected; leakage current when no resistance has been selected. (Excludes output PB7) ∗3 When all pins are open. – 11 – CXP84220/84224 AC Characteristics (1) Clook timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item Symbol System clock frequency Pins fC tXL tXH System clock input rise time, tCR fall time tCF Event count input clock pulse tEH width tEL Event count input clock rise time, tER fall time tEF System clock input pulse width Conditions Min. XTAL EXTAL Fig. 1, Fig. 2 EXTAL Fig. 1, Fig. 2 External clock drive EXTAL Fig. 1, Fig. 2 External clock drive EC0 EC1 Fig. 3 EC0 EC1 Fig. 3 Typ. 1 Max. Unit 10 MHz ns 37.5 200 tsys + 50∗1 ns ns 20 ms ∗1 tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock control register (address: 00FEH). tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”) 1/fc VDD – 0.4V EXTAL 0.4V tXH tCF tXL tCR Fig. 1. Clock timing AAAAA AAAAA AAAAA AAAA AAAA AAAA Crystal oscillation Ceramic oscillation EXTAL C1 External clock EXTAL XTAL C2 XTAL 74HC04 Fig. 2. Clock applied condition 0.8VDD EC0 EC1 0.2VDD tEH tEF tEL Fig. 3. Event count clock timing – 12 – tER CXP84220/84224 (2) Serial transfer (CH0) Item (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol Condition Pin Min. Max. Unit CS0 ↓ → SCK0 delay time tDCSK SCK0 Chip select transfer mode (SCK0 = output mode) tsys + 200 ns CS0 ↑ → SCK0 float delay time tDCSKF SCK0 Chip select transfer mode (SCK0 = output mode) tsys + 200 ns CS0 ↓ → SO0 delay time tDCSO SO0 Chip select transfer mode tsys + 200 ns CS0 ↑ → SO0 float delay time tDCSOF SO0 Chip select transfer mode tsys + 200 ns CS0 High level width tWHCS CS0 Chip select transfer mode SCK0 cycle time tKCY SCK0 tKH tKL SCK0 SI0 input setup time (for SCK0 ↑ ) tSIK SI0 SI0 input hold time (for SCK0 ↑ ) tKSI SCK0 ↓ → SO0 delay time tKSO SCK0 High, Low level width SI0 SO0 tsys + 200 2tsys + 200 ns 16000/fc ns tsys + 100 ns 8000/fc – 50 ns SCK0 input mode 100 ns SCK0 output mode 200 ns tsys + 200 ns 100 ns Input mode Output mode Input mode Output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode ns tsys + 200 ns 100 ns Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock control register (address: 00FEH). tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”) Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL. – 13 – CXP84220/84224 tWHCS CS0 0.8VDD 0.2VDD tKCY tDCSK tKL tDCSKF tKH 0.8VDD 0.8VDD SCK0 0.2VDD tSIK tKSI 0.8VDD SI0 Input data 0.2VDD tDCSO tKSO tDCSOF 0.8VDD SO0 Output data 0.2VDD Fig. 4. Serial transfer CH0 timing – 14 – CXP84220/84224 Serial transfer (CH1) Item (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol Pin tKCY SCK1 tKH tKL SCK1 SI1 input setup time (for SCK1 ↑) tSIK SI1 SI1 input hold time (for SCK1 ↑) tKSI SI1 SCK1 ↓ → SO1 delay time tKSO SO1 SCK1 cycle time SCK1 High, Low level width Condition Min. Max. 1000 ns 16000/fc ns 400 ns 8000/fc – 50 ns SCK1 input mode 100 ns SCK1 output mode 200 ns SCK1 input mode 200 ns SCK1 output mode 100 ns Input mode Output mode Input mode Output mode SCK1 input mode 200 ns SCK1 output mode 100 ns Note) The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL. tKCY tKL tKH SCK1 0.8VDD 0.2VDD tSIK tKSI 0.8VDD Input data SI1 Unit 0.2VDD tKSO 0.8VDD Output data SO1 0.2VDD Fig. 5. Serial transfer CH1 timing – 15 – CXP84220/84224 (3) A/D converter characteristics (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V reference) Pin Condition Min. Max. Unit Resolution 8 Bits Linearity error ±3 LSB Item Symbol Zero transition voltage VZT∗1 Full-scale transition voltage VFT∗2 Conversion time tCONV tSAMP Sampling time Reference input voltage VREF Analog input voltage VIAN Ta = 25°C VDD = 5.0V VSS = AVSS = 0V –10 70 150 mV 4930 5050 5120 mV 160/fADC∗3 12/fADC∗3 AVREF AN0 to AN7 IREF µs VDD V 0 AVREF V 1.0 mA 10 µA Sleep mode Stop mode IREFS µs VDD – 0.5 Operation mode AVREF AVREF current Typ. 0.6 Digital conversion value FFH FEH ∗1 VZT: Value at which the digital conversion value changes from 00H to 01H and vice versa. ∗2 VFT: Value at which the digital conversion value changes from FEH to FFH and vice versa. ∗3 fADC indicates the below values due to ADC operation clock selection. During PS2 selection, fADC = fc/2 During PS1 selection, fADC = fc Linearity error 01H 00H VFT VZT Analog input Fig. 6. Definition of A/D converter terms – 16 – CXP84220/84224 (4) Interruption, reset input (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item Symbol Pin External interruption High, Low level width tIH tIL INT0 INT1 INT2 INT3 NMI Reset input Low level width tRSL RST Condition Min. Max. Unit 1 µs 8/fc µs tIH tIL 0.8VDD INT0 INT1 INT2 INT3 NMI (NMI specifies only for the falling edge) 0.2VDD tIL tIH Fig. 7. Interruption input timing tRSL RST 0.2VDD Fig. 8. RST input timing (5) Power-on reset Power-on reset∗ (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, VSS = 0V reference) Item Symbol tR Power supply cut-off time tOFF Power supply rising time Pin VDD Condition Power-on reset Min. Max. Unit 0.05 50 ms Repetitive power-on reset ms 1 ∗ Specifies only when power-on reset function is selected. VDD 4.5V 0.2V 0.2V tR tOFF The power supply should be rise smoothly. Fig. 9. Power-on reset – 17 – CXP84220/84224 Appendix AAAA AAAA AAAA AAAA AAAA AAAA (ii) Main clock (i) Main clock EXTAL EXTAL XTAL Rd Rd C1 XTAL C2 C1 C2 Fig. 10. SPC700 Series recommended oscillation circuit Manufacturer MURATA MFG CO., LTD. Model fc (MHz) CSA4.19MG 4.19 CSA8.00MTZ 8.00 CSA10.0MTZ 10.00 CST4.19MGW∗ CST8.00MTW∗ CST10.0MTW∗ RIVER ELETEC CORPORATIO N C1 (pF) Rd (Ω) Circuit example (i) 30 4.19 30 0 (ii) 8.00 10.00 4.19 HC-49/U03 8.00 12 12 0 10.00 (i) 4.19 KINSEKI LTD. C2 (pF) HC-49/U (-S) 8.00 10.00 27 27 20 20 0 Those marked with an asterisk (∗) signify types with built-in ground capacitance (C1, C2). Mask option table Item Content Reset pin pull-up resistance Non-existent Existent Power-on reset circuit Non-existent Existent – 18 – CXP84220/84224 Unit: mm + 0.1 0.05 0.25 – 64PIN SDIP (PLASTIC) + 0.4 57.6 – 0.1 64 19.05 + 0.3 17.1 – 0.1 33 1 0° to 15° 32 0.5 MIN + 0.4 4.75 – 0.1 1.778 3.0 MIN Package Outline 0.5 ± 0.1 0.9 ± 0.15 PACKAGE STRUCTURE SONY CODE SDIP-64P-01 EIAJ CODE SDIP064-P-0750 JEDEC CODE PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT SOLDER PLATING LEAD MATERIAL 42 ALLOY PACKAGE MASS 8.6g – 19 –