CXP85632/85640 CMOS 8-bit Single Chip Microcomputer For the availability of this product, please contact the sales office. Description The CXP85632/85640 is a CMOS 8-bit microcomputer which consists of A/D converter, serial interface, timer/counter, time-base timer, closed caption decoder, data slicer, on-screen display function, I2C bus interface, PWM output, remote control receiver, HSYNC counter and watchdog timer as well as basic configuration like 8-bit CPU, ROM, RAM and I/O port. Also this IC provides power-on reset function and sleep function which enables to lower power consumption. 64 pin SDIP (PIastic) 64 pin QFP (PIastic) Structure Silicon gate CMOS IC Features • A wide instruction set (213 instructions) to cover various types of data. — 16-bit arithmetic/multiplication and division/boolean bit operation instructions • Minimum instruction cycle 333ns at 12MHz operation • Incorporated ROM 32K bytes (CXP85632) 40K bytes (CXP85640) • Incorporated RAM 1888 bytes (excluding the closed caption decoder and on-screen display VRAM) • Peripheral functions — A/D converter 8 bits, 6 channels, successive approximation method (Conversion time of 26.7µs/12MHz) — Serial interface 8-bit clock, sync type, 1 channel — Timer 8-bit timer, 8-bit timer/counter, 19-bit time-base timer — Closed caption decoder Incorporated decode slicer, conforming to FCC, 8 × 13 dots, 192 character types, 15 character colors, 4 lines of 34 characters, italic, underline, vertical scroll, 15 frame background colors/half blanking — On-screen display (OSD) function 12 × 16 dots, 128 character types, 15 character colors, 4 lines of 24 characters, 8 frame background colors/half blanking, edging per line (half dot), vertical scroll jitter elimination circuit — I2C bus interface — PWM output 8 bits, 4 channels — Remote control receiver circuit Incorporated 6-stage FIFO 8-bit pulse measurement counter — HSYNC counter 2 channels — Watchdog timer • Interruption 15 factors, 15 vectors, multi-interruption possible • Standby mode SLEEP • Package 64-pin plastic SDIP/QFP • Piggyback/evaluation chip CXP85690 64-pin ceramic PSDIP (accommodates custom font) Purchase of Sony's I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conform to the I2C Standard Specifications as defined by Philips. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E95510-PS Rex Cap 8BIT TIMER/COUNTER 0 8BIT TIMER 1 EC TO REMOCON HSYNC COUNTER 0 HSYNC COUNTER 1 A/D CONVERTER 6CH RMC HSC0 HSC1 AN0 to AN5 FIFO SERIAL INTERFACE UNIT ON SCREEN DISPLAY 2 3 INT0 INT1 INT2 INTERRUPT CONTROLLER CVDD CVss SI SO SCK VSYNC B I YS YM HSYNC XLC EXLC R G Vss MP VDD RST XTAL RAM 1888 BYTES CLOCK GENERATOR/ SYSTEM CONTROL EXTAL 8BIT PWM 4CH WATCHDOG TIMER PRESCALER/ TIME BASE TIMER ROM 32K/40K BYTES SPC700 CPU CORE I2C BUS INTERFACE UNIT SDA0 CC DECODER SCL0 2 SDA1 DATA SLICER SCL1 VIN PWM0 to PWM3 8 8 8 8 3 8 PORT A PORT B PORT C PORT D PORT E –2– PORT F Block Diagram PF0 to PF7 PE0 to PE2 PD0 to PD7 PC0 to PC7 PB0 to PB7 PA0 to PA7 CXP85632/85640 CXP85632/85640 Pin Assignment (Top View) 64-pin SDIP PC3 1 64 PC4 PC2 2 63 PC5 PC1 3 62 PC6 PC0 4 61 PC7 EC/PD7 5 60 PF0/PWM0 RMC/PD6 6 59 PF1/PWM1 HS1/PD5 7 58 PF2/PWM2 HS0/PD4 8 57 PF3/PWM3 SI/PD3 9 56 PF4/SCL0 SO/PD2 10 55 PF5/SCL1 SCK/PD1 11 54 PF6/SDA0 12 53 PF7/SDA1 13 52 PE0/TO VSYNC/PA6 14 51 PE1 RST 15 50 PE2/INT0 MP Vss INT2/PD0 HSYNC/PA7 Vss 16 49 XTAL 17 48 EXTAL 18 47 VDD PA5/AN5 19 46 NC PA4/AN4 20 45 EXLC PA3/AN3 21 44 XLC PA2/AN2 22 43 YM PA1/AN1 23 42 YS PA0/AN0 24 41 I CVss 25 40 B Cap 26 39 G Rex 27 38 R VIN 28 37 PB0 CVDD 29 36 PB1 INT1/PB7 30 35 PB2 PB6 31 34 PB3 PB5 32 33 PB4 Note) 1. NC (Pin 46) must be connected to VDD. 2. Vss (Pins 16 and 48) must be connected to GND. 3. MP (Pin 49) must be connected to GND. 4. Cap (Pin 26) must be connected to CVSS via a capacitor. 5. Rex (Pin 27) must be connected to CVDD via a resistor of 33kΩ. –3– CXP85632/85640 PF2/PWM2 PF1/PWM1 PC7 PF0/PWM0 PC5 PC6 PC4 PC3 PC2 PC1 PC0 PD7/EC PD6/RMC Pin Assignment (Top View) 64-pin QFP 64 63 62 61 60 59 58 57 56 55 54 53 52 HS1/PD5 1 51 PF3/PWM3 HS0/PD4 2 50 PF4/SCL0 SI/PD3 3 49 PF5/SCL1 S0/PD2 4 48 PF6/SDA0 SCK/PD1 5 47 PF7/SDA1 INT2/PD0 6 46 PE0/TO HSYNC/PA7 7 45 PE1 VSYNC/PA6 8 44 PE2/INT0 RST 9 43 MP Vss 10 42 Vss VDD XTAL 11 41 EXTAL 12 40 NC PA5/AN5 13 39 EXLC PA4/AN4 14 38 XLC PA3/AN3 15 37 YM PA2/AN2 16 36 YS PA1/AN1 17 35 I PA0/AN0 18 34 B 19 33 G CVss R PB0 PB1 PB3 PB2 PB4 PB5 PB6 INT1/PB7 VIN CVDD Rex Cap 20 21 22 23 24 25 26 27 28 29 30 31 32 Note) 1. NC (Pin 40) must be connected to VDD. 2. Vss (Pins 10 and 42) must be connected to GND. 3. MP (Pin 43) must be connected to GND. 4. Cap (Pin 20 ) must be connected to CVSS via a capacitor. 5. Rex (Pin 21) must be connected to CVDD via a resistor of 33kΩ. –4– CXP85632/85640 Pin Functions I/O Pin name Functions PA0/AN0 to PA5/AN5 I/O/Analog input PA6/VSYNC I/O/Input PA7/HSYNC I/O/Input PB0 to PB6 I/O PB7/INT1 I/O/Input PC0 to PC7 I/O PD0/INT2 I/O/Input PD1/SCK I/O/I/O PD2/SO I/O/Output PD3/SI I/O/Input PD4/HS0 I/O/Input PD5/HS1 I/O/Input PD6/RMC I/O/Input Remote control receiver circuit input. PD7/EC I/O/Input External event input for timer/counter. PE0/TO I/O/Output PE1 I/O PE2/INT0 I/O/Input PF0/PWM0 to PF3/PWM3 Output/Output PF4/SCL0 PF5/SCL1 Output/I/O PF6/SDA0 PF7/SDA1 Output/I/O R, G, B, I, YS, YM Output (Port A) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) Analog inputs to A/D converter. (6 pins) OSD display vertical sync signal input. OSD display horizontal sync signal input. (Port B) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) Input for external interruption request. Active at the falling edge. (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) Input for external interruption request. Active at the falling edge. (Port D) 8-bit I/O port. I/O can be set in a unit of single bits. Capable of driving 12mA sync current. (8 pins) (Port E) 3-bit I/O port. I/O can be set in a unit of single bits. (3 pins) (Port F) 8-bit output port with large current (12mA) N-ch open drain output. Lower 4 bits are 12V drive and upper 4 bits are 5V drive. Serial clock I/O. Serial data output. Serial data input. HSYNC counter (CH0) input. HSYNC counter (CH1) input. Rectangular wave output for timer/counter. Input for external interruption request. Active at the falling edge. 8-bit PWM outputs. (4 pins) Transfer clock I/O for I2C bus interface. (2 pins) Transfer data I/O for I2C bus interface. (2 pins) OSD display 6-bit outputs. (6 pins) –5– CXP85632/85640 Pin name I/O EXLC Input XLC Output VIN Input Functions OSD display clock oscillation I/O. Oscillator frequency is determined by external L and C. Input of external composite video signal. Input a 2Vp-p signal via a capacitor. Cap — Capacitor connection for the data slicer. Connect a capacitor between Cap and CVSS. Rex — Resistor connection for the data slicer. Connect a 33kΩ resistor between Rex and CVDD. CVDD Positive power supply for data slicer. CVSS GND for data slicer. EXTAL Input XTAL Output RST I/O Low level active system reset. This pin acts as I/O pin and outputs low level through incorporated power-on reset function when the power turned on. (Mask option) MP Input Test mode input. Must be connected to GND. System clock oscillator crystal connection. When using an external clock, input to EXTAL pin and leave XTAL pin open. NC Not connected. Under normal conditions, connect to VDD. VDD Positive power supply. Vss GND. Connect two VSS pins to GND. –6– CXP85632/85640 I/O Circuit Format for Pins Pin Circuit format When reset Port A AA AA Port A data Port A direction PA0/AN0 to PA5/AN5 Input protection circuit IP “0” when reset Data bus Hi-Z RD (Port A) Port A function selection “0” when reset A/D converter Input multiplexer 6 pins Port A Port A data A Port A direction IP PA6/VSYNC PA7/HSYNC Hi-Z Data bus RD (Port A) Schmitt input VSYNC, HSYNC Input polarity 2 pins "0" when reset Port B Port C AA AA Port B, C data PB0 to PB6 PB7/INT1 PC0 to PC7 Port B, C direction IP “0” when reset Data bus RD (Port B, C) INT1 16 pins –7– Schmitt input Hi-Z CXP85632/85640 Pin Circuit format When reset Port D Port D data PD0/INT2 PD3/SI PD4/HS0 PD5/HS1 PD6/RMC PD7/EC Port D direction “0” when reset AA AA ∗ IP Hi-Z Schmitt input Data bus RD (Port D) 6 pins INT2, SI, HS0, HS1, RMC, EC ∗ Large current 12mA Port D SCK, SO Serial output enable A Port D data PD1/SCK PD2/SO ∗ Port D direction “0” when reset IP Hi-Z Schmitt input Data bus RD (Port D) SCK only ∗ Large current 12mA 2 pins Port E TO Port E function selection “1” when reset PE0/TO PE1 PE2/INT0 Port E data AA “1” when reset for PE0, 1 Port E direction IP “1” when reset for PE0, 1 “0” when reset for PE2 Schmitt input only for PE2 Data bus 3 pins RD (Port E) INT0 –8– PE0, PE1: High PE2: Hi-Z CXP85632/85640 Pin Circuit format Port F When reset PWM0 to PWM3 PF0/PWM0 to PF3/PWM3 Port F selection “0” when reset Port F data “1” when reset Hi-Z ∗ ∗ 12V drive voltage Large current 12mA 4 pins AA AA Port F SCL, SDA I2C output enable PF4/SCL0 PF5/SCL1 PF6/SDA0 PF7/SDA1 AAAAA ∗ AA Port F data “1” when reset SCL, SDA (I2C circuit) Hi-Z IP Schmitt input BUS SW To internal I2C pins (To SCL1 for SCL0) ∗ Large current 12mA 4 pins R G B I YS YM 6 pins EXLC XLC 2 pins AAAA AAAA AA A AA A AA AA AA AA AA AA R, G, B, I, YS, YM Output polarity “0” when reset Output becomes active by data writing to output polarity register. EXLC XLC IP IP –9– Hi-Z Oscillator control Oscillation halted OSD display clock CXP85632/85640 Pin EXTAL XTAL Circuit format AA AA AA AA AA AA EXTAL When reset • Diagram indicates equivalent circuit during oscillation. IP • Feedback resistor is disconnected during STOP. (This device does not enter in the STOP mode.) Oscillation XTAL 2 pins AA Pull-up resistor Mask option RST 1 pin Schmitt input OP Low level From power-on reset circuit (Mask option) – 10 – CXP85632/85640 Absolute Maximum Ratings (Vss = 0V reference) Item Symbol Ratings Unit V Remarks Supply voltage VDD Input voltage VIN –0.3 to +7.0 –0.3 to +7.0∗1 Output voltage VOUT –0.3 to +7.0∗1 V Medium voltage tolerance output voltage VOUTP –0.3 to +15.0 V High level output current IOH –5 mA High level total output current ΣIOH –50 mA Total of all output pins IOL 15 mA Excludes large current output port (value per pin) IOLC 20 mA Large current output port (value per pin∗2) Low level total output current ΣIOL 100 mA Total of all output pins Operating temperature Topr –20 to +75 °C Storage temperature Tstg –55 to +150 °C Allowable power dissipation PD 1000 mW SDIP 600 mW QFP V Low level output current PF0 to PF3 pins ∗1 VIN and VOUT should not exceed VDD + 0.3V. ∗2 The large current output port is Port D (PD) and Port F (PF). Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should better take place under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI. Recommended Operating Conditions Item Supply voltage Data slicer supply voltage High level input voltage Low level input voltage Operating temperature ∗1 ∗2 ∗3 ∗4 ∗5 Symbol (Vss = 0V reference) Min. Max. Unit 4.5 5.5 V Guaranteed operation range for 1/2 or 1/4 frequency dividing mode 3.5 5.5 V Guaranteed operation range for 1/16 frequency dividing or SLEEP mode 2.5 5.5 V Guaranteed data hold range for STOP mode∗1 4.5 5.5 V ∗5 VIH 0.7VDD VDD V ∗2 VIHS 0.8VDD VDD V ∗3 VIHEX VDD – 0.4 VDD + 0.3 V VIL 0 0.3VDD V EXTAL pin∗4 ∗2 VILS 0 0.2VDD V ∗3 VILEX –0.3 0.4 V EXTAL pin∗4 Topr –20 +75 °C VDD CVDD Remarks This device does not enter in the STOP mode. PA, PB, PC, PE0, PE1, SCL0, SCL1, SDA0, SDA1 pins. INT2, SCK, SO, SI, HS0, HS1, RMC, EC, INT1, HSYNC, VSYNC, RST pins. Specifies only during external clock input. CVDD and VDD should be set to the same voltage. – 11 – CXP85632/85640 DC Characteristics Item High level output voltage Low level output voltage (Ta = –20 to +75°C, Vss = 0V reference) Symbol Pin Condition Min. VOH PA to PD, PE, R, G, B, I, YS, YM VDD = 4.5V, IOH = –0.5mA 4.0 V VDD = 4.5V, IOH = –1.2mA 3.5 V PA to PD, PE, R, G, B, I, YS, YM, PF0 to PF3, RST∗1 VDD = 4.5V, IOL = 1.8mA 0.4 V VDD = 4.5V, IOL = 3.6mA 0.6 V PD, PF VDD = 4.5V, IOL = 12.0mA 1.5 V PF4 to PF7 (SCL0, SCL1, SDA0, SDA1) VDD = 4.5V, IOL = 3.0mA 0.4 V VDD = 4.5V, IOL = 4.0mA 0.6 V VOL IIHE Input current EXTAL IIHL Typ. Max. Unit VDD = 5.5V, VIH = 5.5V 0.5 40 µA VDD = 5.5V, VIL = 0.4V –0.5 –40 µA –1.5 –400 µA IILR RST∗2 VDD = 5.5V, VIL = 0.4V I/O leakage current IIZ PA to PE, HSYNC, VSYNC, R, G, B, I, YS, YM, RST∗2 VDD = 5.5V, VI = 0, 5.5V ±10 µA Open drain output leak current (N-ch Tr off case) PF0 to PF3 VDD = 5.5V, VOH = 12.0V 50 µA ILOH PF4 to PF7 VDD = 5.5V, VOH = 5.5V 10 µA I2C bus switch connection impedance (Output Tr off case) RBS SCL0: SCL1 SDA0: SDA1 VDD = 4.5V VSCL0 = VSCL1 = 2.25V VSDA0 = VSDA1 = 2.25V 120 Ω 18 30 mA 0.9 3 mA — — — µA — 5.0 10.0 mA 10 20 pF 1/2 frequency dividing mode VDD = 5.5V 12MHz crystal oscillation (C1 = C2 = 15pF) IDD Supply current IDDSL VDD∗3 IDDST Input capacitance SLEEP mode VDD = 5.5V, 12MHz crystal oscillation (C1 = C2 = 15pF) STOP mode∗4 VDD = 5.5V, termination of 12MHz oscillation ICVDD CVDD CIN PA to PE, SCL, SDA, 1MHz clock EXLC, EXTAL, VIN, 0V for all pins excluding measured pins RST VDD = 5.5V ∗1 RST pin is specified only when the power-on reset circuit is selected with mask option. ∗2 In RST pin, the input current is specified when the pull-up resistor is selected; the leakage current when no resistor is selected. ∗3 When all pins are open. Specifies only when the OSD oscillation stops. ∗4 This device does not enter in the STOP mode. – 12 – CXP85632/85640 AC Characteristics (1) Clock timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item System Pin Condition Min. System clock frequency fC XTAL EXTAL Fig. 1, Fig. 2 System clock input pulse width tXL, tXH EXTAL Fig. 1, Fig. 2 External clock drive System clock rise and fall times tCR, tCF tEH, tEL tER, tEF EXTAL Fig 1, Fig 2 External clock drive EC Fig. 3 EC Fig. 3 Event counter input clock pulse widtth Event counter input clock rise and fall times ∗1 Typ. Max. 12.0 Unit MHz ns 37.5 200 tsys∗1 + 50 ns ns 20 ms tsys indicates three values according to the contents of the clock control register (CLC: 00FEH) upper 2 bits. (CPU clock selection) tsys (ns) = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Fig. 1. Clock timing 1/fc VDD – 0.4V EXTAL 0.4V tXH tCF Fig. 2. Clock applied condition AAAA AAAA AAAA External clock EXTAL XTAL C1 tCR AAAA AAAA AAAA Crystal oscillator Ceramic oscillator EXTAL tXL C2 XTAL OPEN Fig. 3. Event count clock timing 0.8VDD EC 0.2VDD tEH tEF – 13 – tEL tER CXP85632/85640 (2) Serial transfer Item (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) System Pin tKCY SCK SCK high and low level widths tKH tKL SCK SI input set-up time (for SCK↑) tSIK SI SI input hold time (for SCK↑) tKSI SI SCK ↓ → SO delay time tKSO SO SCK cycle time Condition Min. Input mode Max. 1000 ns 8000/fc ns 400 ns 4000/fc – 50 ns SCK input mode 100 ns SCK output mode 200 ns SCK input mode 200 ns SCK output mode 100 ns Output mode SCK input mode SCK output mode SCK input mode 200 ns SCK output mode 100 ns Note) The load condition for the SCK output mode, SO output delay time is 50pF + 1TTL. Fig. 4. Serial transfer timing tKCY tKL tKH 0.8VDD SCK 0.2VDD tSIK tKSI 0.8VDD SI Unit Input data 0.2VDD tKSO 0.8VDD SO Output data 0.2VDD – 14 – CXP85632/85640 (3) A/D converter characteristics Item Symbol (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Max. Unit Resolution 8 Bits Linearity error ±1 LSB Zero transition voltage VZT∗1 Full-scale transition voltage VFT∗2 Conversion time Sampling time tCONV tSAMP Analog input voltage VIAN Pin Condition Min. Ta = 25°C VDD = 5.0V Vss = 0V Typ. –50 10 70 mV 4910 4970 5030 mV 160/fADC∗3 12/fADC∗3 AN0 to AN5 0 µs µs VDD V Fig. 5. Definitions for A/D converter terms Digital conversion value FFH FEH ∗1 VZT: Digital conversion values change between 00H←→01H. ∗2 VFT: Digital conversion values change between 0EH←→0FH. ∗3 fADC indicates the below values due to the bit 6 (CKS) of A/D control registor (ADC: 00F9H) and the bit 7 (PCK1) and bit 6 (PCK0) of clock control registor (CLC: 00FEH) Linearity error 01H 00H CKS 0 (φ/2 selection) 1 (φ selection) 00 (φ = fEX/2) fADC = fC/2 fADC = fC 01 (φ = fEX/4) fADC = fC/4 fADC = fC/2 11 (φ = fEX/16) fADC = fC/16 fADC = fC/8 PCK1, 0 VZT VFT Analog input – 15 – CXP85632/85640 (4) Interrupt, reset input (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item Symbol Pin Condition Min. Max. Unit External interrupt high and low level widths tIH tIL INT0 INT1 INT2 1 µs Reset input low level width tRSL RST 32/fc µs Fig. 6. Interrupt input timing tIH INT0 INT1 INT2 (falling edge) tIL 0.8VDD 0.2VDD Fig. 7. RST input timing tRSL RST 0.2VDD (5) Power-on reset∗1 (Ta = –20 to +75°C, Vss = 0V reference) Item Symbol Power supply rise time Power supply cutt-off time tR tOFF Pin VDD Condition Power-on reset Repeated power-on reset Min. Max. Unit 0.05 50 ms 1 ms ∗1 Specified only when power-on reset function is selected. Fig. 8. Power-on reset VDD 4.5V 0.2V 0.2V tR tOFF Take care when turning on power. – 16 – CXP85632/85640 (6) I2C bus timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item Symbol Pin Condition Min. Max. Unit 0 100 kHz SCL clock frequency fSLC SCL Bus-free time before starting transfer tBUF tHD; STA tLOW tHIGH tSU; STA tHD; DAT tSU; DAT tR tF tSU; STO SDA, SCL 4.7 µs SDA, SCL 4.0 µs SCL 4.7 µs SCL 4.0 µs SDA, SCL µs SDA, SCL 4.7 0∗1 SDA, SCL 250 ns Hold time for starting transfer Clock low level width Clock high level width Set-up time for repeated transfers Data hold time Data set-up time SDA, SCL rise time SDA, SCL fall time Set-up time for transfer completion µs SDA, SCL 1 µs SDA, SCL 300 ns SDA, SCL 4.7 µs ∗1 For data hold time, the SCL rise time is not taken into account so that 300ns must be exceeded. Fig. 9. I2C bus transfer data timing SDA tBUF tR tF tHD; STA SCL tHD; STA tSU; STA P S tLOW tHD; DAT tHIGH St tSU; DAT tSU; STO P Fig. 10. I2C device recommended circuit I2C device RS I2C device RS RS R S RP RP SDA0 (or SDA1) SCL0 (or SCL1) • A pull-up resistor must be connected to SDA0 (or SDA1), and SCL0 (or SCL1). • The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance (Rs = 300Ω or less) can be used to reduce spike noise caused by CRT flashover. – 17 – CXP85632/85640 (7) OSD (On Screen Display) timing Item (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Pin Symbol Condiiton Min. Max. Unit 16.5 MHz OSD clock frequency fOSC EXLC XLC Fig. 12 4 HSYNC pulse width tHWD HSYNC Fig. 11 1.2 HSYNC after-write rise and fall times tHCG HSYNC Fig. 11 200 ns VSYNC before-write rise and fall times tVCG VSYNC Fig. 11 1.0 µs µs Fig. 11. OSD timing tHCG tHWD HSYNC For OPOL register (01FDH) bit 7 at “0” 0.8VDD 0.2VDD tVCG VSYNC For OPOL register (01FDH) bit 6 at “0” 0.8VDD 0.2VDD Fig. 12. LC oscillator circuit connection EXLC XLC R∗1 L C1 C2 ∗1 The XLC series resistor can reduce the occurrence of undersired radiation. – 18 – CXP85632/85640 (8) Data slicer external circuit Item (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol Pin Min. Typ. Max. Unit Remarks VIN pin coupling capacitor CVIN VIN 0.47 µF B or more of temperature characteristics is recommended. Cap pin capacitor Ccap Cap 4700 pF B or more of temperature characteristics is recommended. Rex pin pull-up resistor Rrex Rex 33 kΩ Composite video signal input Video In VIN 2.0 Vp-p Fig. 13. Data slicer external recommeded circuit 5.0V CVDD Rrex Rex CVIN R1 VIN Video In R2 C1 Cap Ccap CVss [Recommended Constant] R1 = 100Ω (error: 5%; allowable power dissipation: 1/8 W or more) R2 = 1MΩ (error: 5%; allowable power dissipation: 1/8 W or more) C1 = 820pF (ceramic), B or more of temperature characteristics is recommended. – 19 – CXP85632/85640 Supplement Fig. 14. SPC700 Series recommended oscillation circuit AAAA AAAA AAAA (i) EXTAL XTAL Rd C1 Manufacturer C2 Model fc (MHz) C1 (pF) C2 (pF) Rd (Ω) Circuit example RIVER ELETEC CO., LTD. HC-49/U03 12.0 5 5 0∗1 (i) KINSEKI LTD. HC-19/U (-S) 12.0 15 15 0∗1 (i) ∗1 The XTAL series resistor can reduce the effect of electrostatic discharge noise. Mask Option Table Item Inclusion Reset pin pull-up resistor Non-existent Existent Power-on reset circuit Non-existent Existent – 20 – CXP85632/85640 Fig. 15. Characteristics curves IDD vs. VDD IDD vs. fc (fc = 12MHz, Ta = 25°C, Typical) (VDD = 5V, Ta = 25°C, Typical) 100 50 1 frequency 2 dividing mode 45 1 frequency 4 dividing mode 1 frequency 2 dividing mode 40 35 IDD – Supply current [mA] IDD – Supply current [mA] 10 1 frequency 16 dividing mode 1 30 25 20 1 frequency 4 dividing mode SLEEP mode 15 1 frequency 16 dividing mode 10 5 2 3 4 5 0 6 VDD – Supply voltage [V] 4 8 12 fc – System clock [MHz] Parameter curve for OSD oscillation L vs. C (theoretically calculated value) 100 L – Inductance [µH] 0.1 SLEEP mode 10 10MHz 12MHz 14MHz 16MHz fOSC = 0 1 2π LC C = C1 // C2 50 C1, C2 – Capacitance [pF] – 21 – 100 16 CXP85632/85640 Unit: mm + 0.1 0.05 0.25 – 64PIN SDIP (PLASTIC) 750mil + 0.4 57.6 – 0.1 64 19.05 + 0.3 17.1 – 0.1 33 1 0° to 15° 32 3 MIN 0.5 MIN + 0.4 4.75 – 0.1 1.778 0.5 ± 0.1 0.9 ± 0.15 PACKAGE STRUCTURE MOLDING COMPOUND EPOXY / PHENOL RESIN SONY CODE SDIP-64P-01 LEAD TREATMENT SOLDER PLATING EIAJ CODE SDIP064-P-0750-A LEAD MATERIAL 42 ALLOY PACKAGE WEIGHT 8.6g JEDEC CODE 64PIN QFP(PLASTIC) 23.9 ± 0.4 + 0.4 20.0 – 0.1 + 0.1 0.15 – 0.05 51 0.15 32 64 20 1 16.3 52 17.9 ± 0.4 33 + 0.4 14.0 – 0.1 + 0.2 0.1 – 0.05 19 + 0.35 2.75 – 0.15 + 0.15 0.4 – 0.1 1.0 0.8 ± 0.2 Package Outline ± 0.12 M PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE QFP–64P–L01 LEAD TREATMENT EIAJ CODE ∗ QFP064–P–1420 LEAD MATERIAL SOLDER/PALLADIUM PLATING COPPER /42 ALLOY PACKAGE WEIGHT 1.5g JEDEC CODE – 22 –