CXP85840A/85848A/85856A CMOS 8-bit Single Chip Microcomputer Description The CXP85840A/85848A/85856A are the CMOS 8-bit microcomputer integrating on a single chip an A/D converter, serial interface, timer/counter, time-base timer, closed caption decoder, data slicer, on-screen display function, I2C bus interface, PWM output, remote control reception circuit, HSYNC counter and watchdog timer, besides the basic configurations of 8-bit CPU, ROM, RAM, I/O ports. The CXP85840A/85848A/85856A also provide a power-on reset function and sleep function that enables to lower the power consumption. 64 pin SDIP (Plastic) 64 pin QFP (Plastic) Structure Features Silicon gate CMOS IC • A wide instruction set (213 instructions) which covers various types of data – 16-bit operation/multiplication and division/Boolean bit operation instructions • Minimum instruction cycle 333ns at 12MHz operation • Incorporated ROM 40K bytes (CXP85840A) 48K bytes (CXP85848A) 56K bytes (CXP85856A) • Incorporated RAM 2176 bytes (Excludes closed caption decoder and VRAM for on-screen display) • Peripheral functions – A/D converter 8-bit 6-channel successive approximation method (Conversion time of 26.7µs at 12MHz) – Serial interface 8-bit clock sync type, 1 channel – Timer 8-bit timer 8-bit timer/counter 19-bit time-base timer – Closed caption decoder Data slicer Corresponds to FCC (EDS supported), 8 × 13 dots, 192 character types 15 character colors, 4 lines × 34 characters frame background 15 colors/ half blanking italic, underline, vertical scrolling – On-screen display (OSD) function 12 × 16 dots, 192 character types, 15 character colors 2 lines × 24 characters frame background 8 colors/ half blanking background on full screen 15 colors/ half blanking edging and vertical scrolling for every line jitter elimination circuit sprite OSD, 12 × 16 dots, 1 screen, 8 colors for every dot – I2C bus interface – PWM output 8 bits, 8 channels – Remote control reception circuit 8-bit pulse measurement counter, 6-stage FIFO – HSYNC counter 2 channels – Watchdog timer • Interruption 15 factors, 15 vectors, multi-interruption possible • Standby mode Sleep • Package 64-pin plastic SDIP/QFP • Piggyback/evaluator CXP85890A 64-pin ceramic PSDIP (Supports custom font) Perchase of Sony's I2C components conveys a licence under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E97739A86 LFC1 8BIT TIMER/COUNTER 0 8BIT TIMER 1 EC TO HSYNC COUNTER 1 HSC1 A/D CONVERTER HSYNC COUNTER 0 HSC0 AN0 to AN5 REMOCON RMC FIFO SERIAL INTERFACE UNIT 6 LFC2 Cap ON SCREEN DISPLAY 2 3 INT0 INT1 INT2 INTERRUPT CONTROLLER CVDD CVss SI SO SCK VSYNC B I YS YM HSYNC XLC EXLC R G 8 Vss MP VDD RST XTAL RAM 2176 BYTES CLOCK GENERATOR/ SYSTEM CONTROL EXTAL 8BIT PWM WATCHDOG TIMER PRESCALER/ TIME BASE TIMER ROM 40K/48K/56K BYTES SPC700 CPU CORE I2C BUS INTERFACE UNIT SDA0 CC DECODER SCL0 2 SDA1 DATA SLICER SCL1 PB0 to PB6 PC0 to PC7 7 8 8 3 8 PF0 to PF7 PE0 to PE2 PD0 to PD7 PA0 to PA7 8 PORT B VIN PWM0 to PWM7 PORT A PORT C PORT D PORT E –2– PORT F Block Diagram CXP85840A/85848A/85856A CXP85840A/85848A/85856A Pin Assignment (Top View) 64-pin SDIP PC3 1 64 PC4 PC2 2 63 PC5 PC1 3 62 PC6 PC0 4 61 PC7 EC/PD7 5 60 PF0/PWM0 RMC/PD6 6 59 PF1/PWM1 HS1/PD5 7 58 PF2/PWM2 HS0/PD4 8 57 PF3/PWM3 SI/ PD3 9 56 PF4/SCL0/PWM4 SO/PD2 10 55 PF5/SCL1/PWM5 SCK/PD1 11 54 PF6/SDA0/PWM6 INT2/PD0 HSYNC/PA7 12 53 PF7/SDA1/PWM7 13 52 PE0/TO VSYNC/PA6 14 51 PE1 RST 15 50 PE2/INT0 Vss 16 49 MP XTAL 17 48 Vss EXTAL 18 47 VDD PA5/AN5 19 46 NC PA4/AN4 20 45 EXLC PA3/AN3 21 44 XLC PA2/AN2 22 43 YM PA1/AN1 23 42 YS PA0/AN0 24 41 I CVss 25 40 B LFC2 26 39 G LFC1 27 38 R VIN 28 37 PB0 CVDD 29 36 PB1 Cap 30 35 PB2 INT1/PB6 31 34 PB3 PB5 32 33 PB4 Note) 1. NC (Pin 46) is always connected to VDD. 2. Vss (Pins 16 and 48) are both connected to GND. 3. MP (Pin 49) is always connected to GND. –3– CXP85840A/85848A/85856A PF2/PWM2 PF1/PWM1 PC7 PF0/PWM0 PC5 PC6 PC4 PC3 PC1 PC2 PC0 PD7/EC PD6/RMC Pin Assignment (Top View) 64-pin QFP 64 63 62 61 60 59 58 57 56 55 54 53 52 PF3/PWM3 HS1/PD5 1 51 HS0/PD4 2 50 PF4/SCL0/PWM4 SI/PD3 3 49 PF5/SCL1/PWM5 SO/PD2 4 48 PF6/SDA0/PWM6 SCK/PD1 5 47 PF7/SDA1/PWM7 INT2/PD0 6 46 PE0/TO HSYNC/PA7 7 45 PE1 VSYNC/PA6 8 44 PE2/INT0 RST 9 43 MP Vss 10 42 Vss XTAL 11 41 VDD EXTAL 12 40 NC PA5/AN5 13 39 EXLC PA4/AN4 14 38 XLC PA3/AN3 15 37 YM PA2/AN2 16 36 YS PA1/AN1 17 35 I PA0/AN0 18 34 B 19 33 G R PB0 PB1 PB3 PB2 PB4 PB5 Cap INT1/PB6 VIN CVDD LFC1 20 21 22 23 24 25 26 27 28 29 30 31 32 LFC2 CVss Note) 1. NC (Pin 40) is always connected to VDD. 2. Vss (Pins 10 and 42) are both connected to GND. 3. MP (Pin 43) is always connected to GND. –4– CXP85840A/85848A/85856A Pin Description Symbol I/O Description PA0/AN0 to PA5/AN5 I/O/ Analog input PA6/VSYNC I/O/Input PA7/HSYNC I/O/Input PB0 to PB5 I/O PB6/INT1 I/O/Input PC0 to PC7 I/O PD0/INT2 I/O/Input PD1/SCK I/O/I/O PD2/SO I/O/Output PD3/SI I/O/Input PD4/HS0 I/O/Input PD5/HS1 I/O/Input PD6/RMC I/O/Input Remote control reception circuit input. PD7/EC I/O/Input External event input for timer/counter. PE0/TO I/O/Output PE1 I/O PE2/INT0 I/O/Input PF0/PWM0 to PF3/PWM3 Output/Output PF4/SCL0/PWM4 PF5/SCL1/PWM5 Output/I/O PF6/SDA0/PWM6 PF7/SDA1/PWM7 Output/I/O R, G, B, I, YS, YM Output (Port A) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) Analog inputs to A/D converter. (6 pins) OSD display vertical sync signal input. OSD display horizontal sync signal input. (Port B) 7-bit I/O port. I/O can be set in a unit of single bits. (7 pins) External interruption request input. Active at the falling edge. (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) External interruption request input. Active at the falling edge. (Port D) 8-bit I/O port. I/O can be set in a unit of single bits. Can drive 12mA synk current. (8 pins) (Port E) 3-bit I/O port. I/O can be set in a unit of single bits. (3 pins) (Port F) 8-bit output port and large current (12mA) N-channel open drain output. Lower 4 bits are medium drive voltage (12V); upper 4 bits are 5V drive. (8 pins) Serial clock I/O. Serial data output. Serial data input. HSYNC counter (CH0) input. HSYNC counter (CH1) input. Rectangular wave output for timer/counter External interruption request input. Active at the falling edge. 8-bit PWM output. (8 pins) I2C bus interface transfer clock I/O. (2 pins) I2C bus interface transfer data I/O. (2 pins) 6-bit OSD display output. (6 pins) –5– CXP85840A/85848A/85856A Symbol I/O EXLC Input XLC Output VIN Input Description OSD display clock oscillation I/O. Oscillation frequency is determined by the external L and C. External composite video signal input. Input the 2Vp-p signal via a capacitor. Cap — Connects a data slicer capacitor between Cap and CVss. LFC1, LFC2 — Connects a low-pass filter capacitor for PLL circuit between LFC1 and LFC2. CVDD Positive power supply for data slicer. CVss GND for data slicer. EXTAL Input XTAL Output RST I/O System reset; active at Low level. I/O pin. Outputs a Low level when the power is turned on and the internal power-on reset function operates. (Mask option) MP Input Test mode pin. Always connect to GND. Connects a crystal for system clock oscillation. When a clock is supplied externally, input it to EXTAL and leave XTAL open. NC No connected. Under normal operation, connect to VDD. VDD Positive power supply. Vss GND. Connect two Vss pins to GND. –6– CXP85840A/85848A/85856A Input/Output Circuit Formats for Pins Pin Circuit format When reset Port A A A Port A data Port A direction PA0/AN0 to PA5/AN5 IP “0” when reset Data bus Input protection circuit Hi-Z RD (Port A) Port A function selection “0” when reset A/D converter Input multiplexer 6 pins Port A Port A data A A Port A direction IP “0” when reset PA6/VSYNC PA7/HSYNC Data bus RD (Port A) Hi-Z Schmitt input VSYNC, HSYNC Input polarity 2 pins “0” when reset Port B Port C Ports B, C data PB0 to PB5 PB6/INT1 PC0 to PC7 A A Ports B, C direction IP “0” when reset Data bus RD (Ports B, C) Schmitt input INT1 15 pins –7– Hi-Z CXP85840A/85848A/85856A Pin Circuit format When reset Port D Port D data PD0/INT2 PD3/SI PD4/HS0 PD5/HS1 PD6/RMC PD7/EC Port D direction “0” when reset AA ∗ IP Hi-Z Schmitt input Data bus RD (Port D) 6 pins INT2, SI, HS0, HS1, RMC, EC ∗ Large current 12mA Port D SCK, SO Serial output enable Port D data PD1/SCK PD2/SO AA ∗ Port D direction “0” when reset IP Hi-Z Schmitt input Data bus RD (Port D) ∗ Large current 12mA SCK only 2 pins Port E TO Port E function selection “1” when reset PE0/TO PE1 PE2/INT0 AA AA Port E data “1” when reset for PE0 and 1 Port E direction IP “1” when reset for PE0 and 1 “0” when reset for PE2 Schmitt input only for PE2 Data bus RD (Port E) 3 pins INT0 –8– PE0, PE1: High level PE2: Hi-Z CXP85840A/85848A/85856A Pin Circuit format When reset Port F PWM0 to PWM3 PF0/PWM0 to PF3/PWM3 Port F data ∗ “1” when reset Port F function selection ∗ 12V drive voltage Large current 12mA “0” when reset 4 pins Hi-Z Port F SCL, SDA ∗ I2C output enable PF4/PWM4/SCL0 PF5/PWM5/SCL1 PF6/PWM6/SDA0 PF7/PWM7/SDA1 A A PWM4 to PWM7 IP Port F data “1” when reset Port F function selection “0” when reset R G B I YS YM ∗ Large current 12mA AAAA AAAA 2 pins AA R, G, B, I, YS, YM Output polarity “0” when reset 6 pins EXLC XLC BUS SW To other I2C pins (SCL1 for SCL0) Schmitt input SCL, SDA (I2C circuit) 4 pins Hi-Z Writing data to output polarity register brings output to active. AA AA AA AA AA A AA A EXLC XLC Hi-Z IP IP –9– Oscillation control Oscillation halted OSC display clock CXP85840A/85848A/85856A Pin EXTAL XTAL 2 pins AA AA AA AA EXTAL Circuit format AA When reset • Diagram shows the circuit composition during oscillation. IP • Feedback resistor is removed during stop mode. (This device does not enter the stop mode.) Oscillation XTAL Pull-up resistor RST 1 pin AA AA OP Mask option Schmitt input From power-on reset circuit (Mask option) – 10 – Low level CXP85840A/85848A/85856A Absolute Maximum Ratings Item (Vss = 0V reference) Symbol Ratings Unit V Remarks Supply voltage VDD Input voltage VIN –0.3 to +7.0 –0.3 to +7.0∗1 Output voltage VOUT –0.3 to +7.0∗1 V Medium drive output voltage VOUTP –0.3 to +15.0 V High level output current IOH –5 mA High level total output current ∑IOH –50 mA Total of all output pins IOL 15 mA Ports excluding large current outputs (value per pin) IOLC 20 mA Large current output ports (value per pin∗2) Low level total output current ∑IOL 100 mA Total of all output pins Operating temperature Topr –20 to +75 °C Storage temperature Tstg –55 to +150 °C Allowable power dissipation PD 1000 mW SDIP-64P-01 600 mW GFP-64P-L01 V PF0 to PF3 pins Low level output current ∗1 VIN and VOUT should not exceed VDD + 0.3V. ∗2 The large current output port is Port D (PD) and Port F (PF). Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI. Recommended Operating Conditions Item Supply voltage Data slicer supply voltage High level input voltage Symbol Min. Max. Unit 4.5 5.5 V Guaranteed operation range for 1/2 and 1/4 frequency dividing clocks 3.5 5.5 V Guaranteed operation range for 1/16 frequency dividing clock or sleep mode 2.5 5.5 V 4.5 5.5 V Guaranteed data hold range for stop mode∗1 ∗5 VIH 0.7VDD VDD V ∗2 VIHS 0.8VDD VDD V ∗3 VDD CVDD Operating temperature ∗1 ∗2 ∗3 ∗4 ∗5 Remarks VIL 0 0.3VDD V EXTAL pin∗4 ∗2 VILS 0 0.2VDD V ∗3 VILEX –0.3 0.4 V EXTAL pin∗4 Topr –20 +75 °C VIHEX Low level input voltage (Vss = 0V reference) VDD – 0.4 VDD + 0.3 V This device does not enter the stop mode. PA, PB, PC, PE0 to PE1, SCL0 to 1, SDA0 to 1 pins. INT2, SCK, SO, SI, HS0, HS1, RMC, EC, INT1, HSYNC, VSYNC, RST pins. Specifies only during external clock input. CVDD and VDD should be set to the same voltage. – 11 – CXP85840A/85848A/85856A Electrical Characteristics DC characteristics Item High level output voltage Low level output voltage Symbol VOH VOL IIHE Input current (Ta = –20 to +75°C, Vss = 0V reference) Pins Conditions Min. PA to PD, PE R, G, B, I, YS, YM VDD = 4.5V, IOH = –0.5mA 4.0 V VDD = 4.5V, IOH = –1.2mA 3.5 V PA to PD, PE R, G, B, I, YS, YM, PF0 to PF3, RST∗1 VDD = 4.5V, IOL = 1.8mA 0.4 V VDD = 4.5V, IOL = 3.6mA 0.6 V PD, PF VDD = 4.5V, IOL = 12.0mA 1.5 V PF4 to PF7 (SCL0, SCL1, SDA0, SDA1) VDD = 4.5V, IOL = 3.0mA 0.4 V VDD = 4.5V, IOL = 4.0mA 0.6 V EXTAL IIHL Typ. Max. Unit VDD = 5.5V, VIH = 5.5V 0.5 40 µA VDD = 5.5V, VIL = 0.4V –0.5 –40 µA –1.5 –400 µA IILR RST∗2 VDD = 5.5V, VIL = 0.4V I/O leakage current IIZ PA to PE, HSYNC, VSYNC, R, G, B, I, YS, YM, RST∗2 VDD = 5.5V, VI = 0, 5.5V ±10 µA Open drain I/O leakage current (in N-ch Tr OFF state) PF0 to PF3 VDD = 5.5V, VOH = 12.0V 50 µA ILOH PF4 to PF7 VDD = 5.5V, VOH = 5.5V 10 µA SCL0: SCL1 SDA0: SDA1 VDD = 4.5V VSCL0 = VSCL1 = 2.25V VSDA0 = VSDA1 = 2.25V 120 Ω I2C bus switch connection impedance RBS (in output Tr OFF state) IDD Supply current IDDSL VDD∗3 IDDST Input capacitance 1/2 frequency dividing clock operation VDD = 5.5V, 12MHz crystal oscillation (C1 = C2 = 15pF) 37 50 mA Sleep mode VDD = 5.5V, 12MHz crystal oscillation (C1 = C2 = 15pF) 2.5 5 mA Stop mode∗4 VDD = 5.5V, termination of 12MHz oscillation — — — µA VDD = 5.5V — 5.0 10.0 mA 10 20 pF ICVDD CVDD CIN PA to PE, SCL, Clock 1MHz SDA, EXLC, EXTAL, 0V for no-measured pins VIN, RST ∗1 Specifies RST pin only when the power-on reset circuit is selected with mask option. ∗2 For RST pin, specifies the input current when pull-up resistor is selected, and specifies the leakage current when non-resistor is selected. ∗3 When all output pins are left open. Specifies only when the OSD oscillation is halted. ∗4 This device does not enter the stop mode. – 12 – CXP85840A/85848A/85856A AC Characteristics (1) Clock timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item Symbol Pins Conditions Typ. Min. System clock frequency fC XTAL EXTAL Fig. 1, Fig. 2 System clock input pulse width tXL, tXH EXTAL Fig. 1, Fig. 2 External clock drive System clock input rise and fall times tCR, tCF EXTAL Fig. 1, Fig. 2 External clock drive Event count input clock pulse width tEH, tEL EC Fig. 3 Event count input clock rise and fall times tER, tEF EC Fig. 3 Max. Unit MHz 12.0 ns 37.5 200 tsys∗1 + 50 ns ns 20 ms ∗1 Indicates three values according to the contents of the clock control register (CLC: 00FEh) upper 2 bits (CPU clock selection). tsys (ns) = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”) Fig. 1. Clock timing 1/fc VDD – 0.4V EXTAL 0.4V tXH tCF tXL tCR Fig. 2. Clock applied conditions AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA Crystal oscillation Ceramic oscillation EXTAL C1 External clock EXTAL XTAL C2 XTAL OPEN Fig. 3. Event count clock timing 0.8VDD EC 0.2VDD tEH tEF – 13 – tEL tER CXP85840A/85848A/85856A (2) Serial transfer Item (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol Pins tKCY SCK SCK High and Low level widths tKH tKL SCK SI input setup time (for SCK ↑) tSIK SI SI hold time (for SCK ↑) tKSI SI SCK ↓ → SO delay time tKSO SO SCK cycle time Conditions Min. Input mode Max. 1000 ns 8000/fc ns 400 ns 4000/fc – 50 ns SCK input mode 100 ns SCK output mode 200 ns SCK input mode 200 ns SCK output mode 100 ns Output mode SCK input mode SCK output mode SCK input mode 200 ns SCK output mode 100 ns Note) The load of SCK output mode and SO output delay time is 50 pF + 1TTL. Fig. 4. Serial transfer timing tKCY tKL tKH 0.8VDD SCK 0.2VDD tSIK tKSI 0.8VDD Input data SI Unit 0.2VDD tKSO 0.8VDD SO Output data 0.2VDD – 14 – CXP85840A/85848A/85856A (3) A/D converter Item (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol Max. Unit Resolution 8 Bits Linearity error ±3 LSB Zero transition voltage VZT∗1 Full-scale transition voltage VFT∗2 Conversion time Sampling time tCONV tSAMP Analog input voltage VIAN Pins Conditions Min. Ta = 25°C VDD = 5.0V Vss = 0V Typ. –10 10 70 mV 4910 4970 5030 mV 160/fADC∗3 12/fADC∗3 AN0 to AN5 0 µs µs VDD V Fig. 5. Definitions of A/D converter terms FFh FEh Digital conversion value ∗1 VZT: Value at which the digital conversion value changes from 00H to 01H and vice versa. ∗2 VFT: Value at which the digital conversion value changes from FEh to FFh and vice versa. ∗3 fADC indicates the below values due to the contents of bit 6 (CKS) of the A/D control register (ADC: 00F9h) and bits 7 (PCK1) and 6 (PCK0) of the clock control register (CLC: 00FEh). Linearity error 01h 00h VZT VFT CKS 0 (φ/2 selection) 1 (φ selection) 00 (φ = fEX/2) fADC = fC/2 fADC = fC 01 (φ = fEX/4) fADC = fC/4 fADC = fC/2 11 (φ = fEX/16) fADC = fC/16 fADC = fC/8 PCK1, 0 Analog input – 15 – CXP85840A/85848A/85856A (4) Interruption, reset input (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item Symbol Pins Conditions Min. Max. Unit External interruption High and Low level widths tIH tIL INT0 INT1 INT2 1 µs Reset input Low level width tRSL RST 32/fc µs Fig. 6. Interruption input timing tIH INT0 INT1 INT2 (falling edge) tIL 0.8VDD 0.2VDD Fig. 7. RST input timing tRSL RST 0.2VDD (5) Power-on reset∗1 (Ta = –25 to +75°C, Vss = 0V reference) Item Symbol tR Power supply cut-off time tOFF Power supply rise time Pins VDD Conditions Power-on reset Repeated power-on reset Min. Max. Unit 0.05 50 ms 1 ms ∗1 Specifies only when the power-on reset function is selected. Fig. 8. Power-on reset VDD 4.5V 0.2V 0.2V tR tOFF Take care when turning the power on. – 16 – CXP85840A/85848A/85856A (6) I2C bus timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item Symbol Pins Conditions Min. Max. Unit 0 100 kHz SCL clock frequency fSLC SCL Bus-free time before starting transfer tBUF tHD; STA tLOW tHIGH tSU; STA tHD; DAT tSU; DAT tR tF tSU; STO SDA, SCL 4.7 µs SDA, SCL 4.0 µs SCL 4.7 µs SCL 4.0 µs SDA, SCL µs SDA, SCL 4.7 0∗1 SDA, SCL 250 ns Hold time for starting transfer Clock Low level width Clock High level width Setup time for repeated transfers Data hold time Data setup time SDA, SCL rise time SDA, SCL fall time Setup time for transfer completion µs SDA, SCL 1 µs SDA, SCL 300 ns SDA, SCL 4.7 µs ∗1 The data hold time should be 300ns or more because the SCL rise time (300ns Max.) is not included in it. Fig. 9. I2C bus transfer timing SDA tBUF tR tF tHD; STA SCL tHD; STA tSU; STA P S tLOW tHD; DAT tHIGH St tSU; DAT tSU; STO P Fig. 10. I2C bus device recommended circuit I2C device RS I2C device RS RS R S RP RP SDA0 (or SDA1) SCL0 (or SCL1) • A pull-up resistor (Rp) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1). • The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance (Rs = 300Ω or less) can be used to reduce the spike noise caused by CRT flashover. – 17 – CXP85840A/85848A/85856A (7) OSD timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item Symbol Pins Conditions Min. Max. Unit 16.5 MHz EXLC XLC Fig. 12 4 tHWD tVWD HSYNC Fig. 11 1.2 µs VSYNC Fig. 11 1 H* HSYNC after-write rise and fall times tHCG HSYNC Fig. 11 200 ns VSYNC before-write rise and fall times tVCG VSYNC Fig. 11 1.0 µs OSD clock frequency fOSC HSYNC pulse width VSYNC pulse width * H indicates 1HSYNC period. Fig. 11. OSD timing tHCG tHWD 0.8VDD HSYNC For OSD I/O polarity register (OPOL: 01FDh) bit 7 at “0” 0.2VDD tVCG tVWD 0.8VDD VSYNC For OSD I/O polarity register (OPOL: 01FDh) bit 6 at “0” 0.2VDD Fig. 12. LC oscillation circuit connection EXLC XLC R∗1 L C2 C1 ∗1 The XLC series resistor can reduce the frequency of occurrence of the undesired radiation. – 18 – CXP85840A/85848A/85856A (8) Data slicer external circuit Item Symbol (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Pin Min. Typ. Max. Unit Remarks VIN 0.1 µF The B characteristics or more of temperature characteristics is recommended. Cap pin capacitance Ccap Cap 4700 pF The B characteristics or more of temperature characteristics is recommended. PLL low-pass filter capacitance CLPF LFC1, LFC2 0.47 µF The B characteristics or more of temperature characteristics is recommended. Composite video signal input Video In VIN 2.0 Vp-p VIN pin coupling capacitance CVIN Fig. 13. Data slicer external recommended circuit 5.0V CVDD LFC2 CLPF LFC1 CVIN R1 VIN Video In C1 R2 Cap Ccap CVss [Recommended Constant] R1 = 220Ω (error: 5%; allowable power dissipation: 1/8W or more) R2 = 1MΩ (error: 5%; allowable power dissipation: 1/8W or more) C1 = 1200pF (ceramic), the B characteristics or more of temperature characteristics is recommended. – 19 – CXP85840A/85848A/85856A Appendix Fig. 14. SPC 700 Series recommended oscillation circuit AAAAA AAAAA AAAAA (i) EXTAL XTAL Rd C1 Manufacture C2 Model fc (MHz) C1 (pF) C2 (pF) RIVER ELETEC CO., LTD. HC-49/U03 12.0 5 5 Rd (Ω) 0∗1 KINSEKI LTD. HC-19/U (-S) 12.0 15 15 0∗1 Circuit example ∗1 The XTAL series resistor can reduce the effect of the noise caused by the electrostatic discharge. Mask Option Table Item Content Reset pin pull-up resistor Non-existent Existent Power-on reset circuit Non-existent Existent – 20 – (i) (i) CXP85840A/85848A/85856A Fig. 15. Characteristic curves IDD vs. VDD IDD vs. fc (fc = 12MHz, Ta = 25°C, Typical) (VDD = 5V, Ta = 25°C, Typical) 50 100 1/2 dividing mode 45 1/4 dividing mode 1/2 dividing mode 1/16 dividing mode 35 IDD – Supply current [mA] 10 Sleep mode 1 30 25 1/4 dividing mode 20 15 10 1/16 dividing mode 5 0 0.1 3 4 5 Sleep mode 4 6 8 12 fc – System clock [MHz] VDD – Supply voltage [V] Parameter curve for OSD oscillation L vs. C (theoretically calculated value) 100 L – Inductance [µH] IDD – Supply current [mA] 40 10 10MHz 12MHz 14MHz 16MHz fOSC = 0 1 2π LC C = C1 // C2 50 C1, C2 – Capacitance [pF] – 21 – 100 16 CXP85840A/85848A/85856A Unit: mm + 0.1 0.05 0.25 – 64PIN SDIP (PLASTIC) 750mil + 0.4 57.6 – 0.1 64 19.05 + 0.3 17.1 – 0.1 33 1 0° to 15° 32 3 MIN 0.5 MIN + 0.4 4.75 – 0.1 1.778 0.5 ± 0.1 0.9 ± 0.15 PACKAGE STRUCTURE MOLDING COMPOUND EPOXY / PHENOL RESIN SONY CODE SDIP-64P-01 LEAD TREATMENT SOLDER PLATING EIAJ CODE SDIP064-P-0750-A LEAD MATERIAL 42 ALLOY PACKAGE WEIGHT 8.6g JEDEC CODE 64PIN QFP(PLASTIC) 23.9 ± 0.4 + 0.4 20.0 – 0.1 + 0.1 0.15 – 0.05 51 0.15 32 64 20 1 16.3 52 17.9 ± 0.4 33 + 0.4 14.0 – 0.1 + 0.2 0.1 – 0.05 19 + 0.35 2.75 – 0.15 + 0.15 0.4 – 0.1 1.0 0.8 ± 0.2 Package Outline ± 0.12 M PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER/PALLADIUM PLATING SONY CODE QFP–64P–L01 LEAD TREATMENT EIAJ CODE QFP064–P–1420 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 1.5g JEDEC CODE – 22 –