SONY CXP82900

CXP82900
CMOS 8-bit Single Chip Microcomputer
Description
The CXP82900 is a CMOS 8-bit single chip microcomputer of piggyback/evaluator combined type,
which is developed for evaluating the function of the
CXP82940/82948/82952/82960.
Piggyback/
evaluator type
80 pin PQFP (Ceramic)
Features
• Wide-range instruction system (213 instructions)
to cover various types of data
— 16-bit operation/multiplication and division/
Boolean bit operation instructions
• Minimum instruction cycle
250ns at 16MHz operation
122µs at 32kHz operation
• Applicable EPROM
LCC type 27C512 (Maximum 60K bytes are available.)
• Incorporated RAM capacity 2048 bytes (Including fluorescent display data area.)
• Peripheral functions
— A/D converter
8-bit, 8-channel, successive approximation method
(Conversion time of 20µs/16MHz)
— Serial interface
Incorporated buffer RAM (Auto transfer for 1 to 32bytes), 1 channel
Incorporated 8-bit, 8-stage FIFO (Auto transfer for 1 to 8 bytes), 1 channel
— Timer
8-bit timer
8-bit timer/counter
19-bit time base timer
32kHz timer/counter
— Fluorescent display panel controller/driver
Maximum 196-segment display possible
1 to 16-digit dynamic display
Dimmer function
High voltage drive output (40V)
Pull-down function
Hardware key scan function (Maximum 12 × 8 key matrix compatible)
2
— I C bus interface
— Remote control transmission circuit
Auto transmission for 1 to 32 bytes, restart function, carrier output function
— Remote control reception circuit
8-bit pulse measurement counter with on-chip 6-stage FIFO
• Interruption
16 factors, 15 vectors, multi-interruption possible
• Standby mode
SLEEP/STOP
• Package
80-pin ceramic QFP
Note) Mask option depends on the type of the CXP82900. Refer to the Products List for details.
Structure
Silicon gate CMOS IC
Perchase of Sony's I2C components conveys a licence under the Philips I2C Patent Rights to use these components
in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E95613-PP
CXP82900
T6
T5
T4
T3
T2
T1
T0
VDD
TX
TEX
NC
PG0
PG1
PG2
PG3
PE0/EC/INT0
Pin Configuration in Piggyback Mode
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
T8/S19
PE3/INT3/NMI
3
62
T9/S18
PE4/RMC
4
61
T10/S17
PE5
5
60
T11/S16
PE6/RMCO
6
59
T12/S15
PE7/TO/ADJ
7
58
T13/S14
57
T14/S13
A13
63
A14
2
VDD
PE2/INT2
NC
T7
A15
64
A12
1
A7
PE1/INT1
PB0
8
PB1/CS0
9
A6
5
29
A8
56
T15/S12
PB2/SCK0
10
A5
6
28
A9
55
S11
PB3/SI0
11
A4
7
27
A11
54
S10
4
1
2
3
32 31 30
PB4/SO0
12
A3
8
26
NC
53
S9
PB5/SCK1
13
A2
9
25
OE
52
S8
PB6/SI1
14
A1
10
24
A10
51
PD7/S7
PB7/SO1
15
A0
11
23
CE
50
PD6/S6
PA0/AN0
16
NC
12
22
D7
49
PD5/S5
PA1/AN1
17
D0
13
21
D6
48
PD4/S4
PA2/AN2
18
47
PD3/S3
PA3/AN3
19
46
PD2/S2
PA4/AN4
20
45
PD1/S1
PA5/AN5
21
44
PD0/S0
PA6/AN6
22
43
VFDP
PA7/AN7
23
42
PC7/KR7
AVDD
24
41
PC6/KR6
D5
D4
D3
NC
GND
D2
D1
14 15 16 17 18 19 20
Note) NC (Pin 75) is always connected to VDD.
–2–
PC5/KR5
PC4/KR4
PC3/KR3
PC2/KR2
PC1/KR1
PC0/KR0
VSS
RST
XTAL
EXTAL
AVSS
PF3/SDA1
PF2/SDA0
PF1/SCL1
AVREF
PF0/SCL0
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
CXP82900
T6
T5
T4
T3
T2
T1
T0
VDD
TX
TEX
NC
PG0
PG1
PG2
PG3
PE0/EC/INT0
Pin Configuration in Evaluator Mode
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
3
62
T9/S18
PE4/RMC
4
61
T10/S17
PE5
5
PE6/RMCO
6
PE7/TO/ADJ
7
PB0
8
4
1
2
3
A13
PE3/INT3/NMI
A14
T8/S19
VDD
63
NC
T7
2
A15
64
PE2/INT2
A12
1
A7/D7
PE1/INT1
32 31 30
60
T11/S16
59
T12/S15
58
T13/S14
57
T14/S13
PB1/CS0
9
A6/D6
5
29
A8
56
T15/S12
PB2/SCK0
10
A5/D5
6
28
A9
55
S11
PB3/SI0
11
A4/D4
7
27
A11
54
S10
PB4/SO0
12
A3/D3
8
26
NC
53
S9
PB5/SCK1
13
A2/D2
9
25
HALT
52
S8
PB6/SI1
14
A1/D1
10
24
A10
51
PD7/S7
PB7/SO1
15
A0/D0
11
23
E/P
50
PD6/S6
PA0/AN0
16
NC
12
22
I/T
49
PD5/S5
PA1/AN1
17
RD
13
21
MON
48
PD4/S4
47
PD3/S3
14 15 16 17 18 19 20
20
45
PD1/S1
PA5/AN5
21
44
PD0/S0
PA6/AN6
22
43
VFDP
PA7/AN7
23
42
PC7/KR7
AVDD
24
41
PC6/KR6
RST
PA4/AN4
C1
PD2/S2
C2
46
NC
19
GND
PA3/AN3
SYNC
18
WR
PA2/AN2
Note) NC (Pin 75) is always connected to VDD.
–3–
PC5/KR5
PC4/KR4
PC3/KR3
PC2/KR2
PC1/KR1
PC0/KR0
RST
VSS
XTAL
EXTAL
AVSS
PF3/SDA1
PF2/SDA0
PF1/SCL1
PF0/SCL0
AVREF
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
CXP82900
EPROM Read Timing
(Ta = –20 to +75°C, Vcc = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pins
Min.
Address → Data
Input delay time
tACC
A0 to A15
D0 to D7
Address → Data
Hold time
tIH
A0 to A15
D0 to D7
Max.
Unit
75
ns
0
ns
0.8VDD
A0 to A15
Address data
0.2VDD
tACC
tIH
0.8VDD
D0 to D7
Input
data
0.2VDD
Products List
Products
Option item
Mask type
Piggyback/evaluator product
CXP82940 CXP82948 CXP82952 CXP82960
CXP82900-U01Q
80-pin plastic QFP
80-pin ceramic QFP
40K bytes 48K bytes 52K bytes 60K bytes
EPROM 60K bytes
Pull-up resistance for
reset pin
Existent/Non-existent
Existent
Pull-down resistance for
high voltage drive pin
Existent/Non-existent
Existent: T0 to T7, S8 to T8/S19
Non-existent: PD0/S0 to PD7/S7
Package
ROM capacitance
–4–
CXP82900
Piggyback mode/evaluator mode can be switched as shown below.
Piggyback mode
Piggyback/evaluator product
Evaluator mode
Pin 1 marking
Pin 1 index
LCC type EPROM
Pin 1 marking
Note)
CPU Probe
Note) Evaluation cap should be
connected to CPU probe.
Package Outline
Unit: mm
80PIN PQFP (CERAMIC)
PIN No. 1 INDEX
18.7
16.3 ± 0.2
INDEX
80
65
65
64
PIN No. 1 INDEX
1
64
0.8 ± 0.05
1
80
0.4 ± 0.08
14.22
18.12 ± 0.2
1.27 ± 0.13
12.02
0.7
1.0
0.3
6.0
24
40
9.48
24
41
1.3 ± 0.3
41
25
40
25
0.6
11.66
15.58 ± 0.2
PACKAGE STRUCTURE
PACKAGE MATERIAL
+ 0.05
0.15 – 0.02
9.59 MAX
–5–
CERAMIC
SONY CODE
PQFP-80C-L01
LEAD TREATMENT
GOLD PLATING
EIAJ CODE
AQFP080-C-0000-A
LEAD MATERIAL
42 ALLOY
PACKAGE WEIGHT
5.7g
JEDEC CODE
3.57 ± 0.36
24.7
22.3 ± 0.25
4.5