SONY CXP921000A

CXP921000A
CMOS 16-bit Single Chip Microcomputer
Description
The CXP921000A is a CMOS 16-bit single chip
microcomputer of piggyback/evaluator combined
type, which is developed for evaluating the function
of the CXP921064A.
Piggy/
evaluation type
100 pin PQFP (Ceramic)
Features
(LQFP supported)
(QFP supported)
• An efficient instruction set as a controller
– Direct addressing, numerous abbreviated forms,
multiplication and division instructions
• Instruction sets for C Ianguage and RTOS
– Highly quadratic instruction system,
general-purpose register of eight 16-bit × 16-bank configuration
• Minimum instruction cycle time 100ns at 20MHz operation (2.7 to 3.3V)
61µs at 32kHz operation (2.2 to 3.3V)
• Incorporated EPROM
CXP27V1000K
• Incorporated RAM capacity
10K bytes
• Peripheral functions
— A/D converter
8-bit 12 analog input, 2 channels successive approximation system,
automatic scanning function, (Conversion time: 3.4µs at 20MHz)
— Serial interface
128 -byte buffer RAM, 3 channels
8-stage FIFO, 1 channel (supports special mode master/slave)
— I2C bus interface
64-byte buffer RAM , 2 channels
(supports master/slave and automatic transfer mode)
— Timers
8-bit timer/counter, 2 channels (with timing output)
16-bit timer, 3 channels
— Real-time pulse generator
5-bit output, 1 channel (2-stage FIFO)
— Clock prescaler
— Remote control receive circuit 8-bit pulse measurement counter, 8-stage FIFO
• Interruption
30 factors, 30 vectors, multi-interruption and priority selection possible
• Standby mode
Sleep/stop
• Package
100-pin Ceramic PQFP
• Mask ROM
CXP921064A
• FLASH EEPROM incorporated type CXP921F064A
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E99X11-PS
CXP921000A
PJ1/AN5/KS9
PJ2/AN6/KS10
PJ3/AN7/KS11
PJ4/AN8/KS12
PJ5/AN9/KS13
PJ6/AN10/KS14
PJ7/AN11/KS15
NC
VSS
VDD
PA0/AN12
PA1/AN13
PA2/AN14
PA3/AN15
PA4/AN16
PA5/AN17
PA6/AN18
PA7/AN19
PB0/AN20
PB1/AN21
Pin Assignment in Piggyback Mode (Top View) 100-pin QFP package
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
PB2/AN22
1
80
PJ0/AN4/KS8
PB3/AN23
2
79
AVDD
PB4/SI3
3
78
AVREF1
PB5/SO3
4
77
AVREF0
PB6/SCK3
5
76
AVss
PB7/RMC
6
75
AN3
PC0/SDA0
7
74
AN2
PC1/SCL0
8
73
AN1
PC2/SDA1
9
72
PI7/AN0
PC3/SCL1
10
71
PI6/NMI
70
PI5/INT7
69
PI4/INT6
68
PI3/INT5
PC4
11
PC5
12
PC6
13
PC7
14
VSS
15
A10
1
24
VDD
A23
25
48
VDD
A9
2
23
A11
A22
26
47
CE
A8
3
22
A12
A21
27
46
NC
A7
4
21
D7
A20
28
45
D15
A6
5
20
D6
A19
29
44
D14
67
PI2/INT4
A5
6
19
D5
A18
30
43
D13
66
PI1/INT3
7
18
D4
A17
31
42
D12
PD0/KS0
16
A4
65
PI0/INT2
PD1/KS1
17
A3
8
17
D3
A16
32
41
D11
64
PH7/INT1
PD2/KS2
18
A2
9
16
D2
A15
33
40
D10
63
PH6/INT0
PD3/KS3
19
A1
10
15
D1
A14
34
39
D9
62
PH5/XOUT
PD4/KS4
20
A0
11
14
D0
A13
35
38
D8
61
PH4/RTO4
PD5/KS5
21
Vss
12
13
Vss
Vss
36
37
Vss
60
PH3/RTO3
PD6/KS6
22
59
PH2/RTO2
PD7/KS7
23
58
PH1/RTO1
PE0
24
57
PH0/RTO0
PE1
25
56
Vss
PE2
26
55
TX
PE3
27
54
TEX
PE4
28
53
VDD
PE5
29
52
PG7/SCK2
PE6
30
51
PG6/SO2
PG5/SI2
PG4/CS2
PG3/SCK1
PG2/SO1
PG1/SI1
VDD
PG0/CS1
EXTAL
XTAL
VSS
RST
PF6/TO
PF7/TMO
PF5/SCK0
PF4/SO0
PF3/SI0
PF1/EC
PF2/CS0
PF0
PE7
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note) 1. NC (Pin 88) must be left open. However, use this pin for FLASH EEPROM
incorporated version.
2. Vss (Pins 15, 41, 56 and 90) must be connected to GND.
3. VDD (Pins 44, 53 and 89) must be connected to VDD.
4. A20 to A23 are always high level output.
–2–
CXP921000A
PJ1/AN5/KS9
PJ2/AN6/KS10
PJ3/AN7/KS11
PJ4/AN8/KS12
PJ5/AN9/KS13
PJ6/AN10/KS14
PJ7/AN11/KS15
NC
VDD
VSS
PA0/AN12
PA1/AN13
PA2/AN14
PA3/AN15
PA4/AN16
PA5/AN17
PA6/AN18
PA7/AN19
PB0/AN20
PB1/AN21
Pin Assignment in Evaluator Mode (Top View) 100-pin QFP package
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
PB2/AN22
1
80
PJ0/AN4/KS8
PB3/AN23
2
79
AVDD
PB4/SI3
3
78
AVREF1
PB5/SO3
4
77
AVREF0
PB6/SCK3
5
76
AVss
PB7/RMC
6
75
AN3
PC0/SDA0
7
74
AN2
PC1/SCL0
8
73
AN1
PC2/SDA1
9
72
PI7/AN0
PC3/SCL1
10
71
PI6/NMI
PC4
11
70
PI5/INT7
PC5
12
69
PI4/INT6
68
PI3/INT5
67
PI2/INT4
PC6
13
PC7
14
VSS
15
PD0/KS0
16
PD1/KS1
17
PD2/KS2
18
AD10
1
24
VDD
AD9
2
23
AD8
3
AD7
A23
25
48
VDD
AD11
A22
26
47
E/P
22
AD12
A21
27
46
ST0
4
21
I/T
A20
28
45
ST1
AD6
5
20
MON
A19
29
44
ST2
AD5
6
19
ERST
A18
30
43
ST3
66
PI1/INT3
AD4
7
18
C1
A17
31
42
PI0/INT2
AD3
8
17
C2
A16
32
41
AD2
9
16
QS0
AD15
33
40
10
15
QS1
AD14
34
39
WTACK 65
JRQH
64
JRQL
63
ENMI
62
AD13
35
38
MS
61
PH4/RTO4
Vss
36
37
Vss
60
PH3/RTO3
PH7/INT1
PH6/INT0
PD3/KS3
19
AD1
PD4/KS4
20
AD0
11
14
QS2
PD5/KS5
21
Vss
12
13
Vss
PD6/KS6
22
59
PH2/RTO2
PD7/KS7
23
58
PH1/RTO1
PE0
24
57
PH0/RTO0
PE1
25
56
Vss
PE2
26
55
TX
PE3
27
54
TEX
PE4
28
53
VDD
PE5
29
52
PG7/SCK2
PE6
30
51
PG6/SO2
PH5/XOUT
PG5/SI2
PG4/CS2
PG2/SO1
PG3/SCK1
PG1/SI1
PG0/CS1
VDD
XTAL
EXTAL
VSS
RST
PF7/TMO
PF6/TO
PF5/SCK0
PF4/SO0
PF3/SI0
PF2/CS0
PF1/EC
PF0
PE7
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note) 1. NC (Pin 88) must be left open. However, use this pin for FLASH EEPROM
incorporated version.
2. Vss (Pins 15, 41, 56 and 90) must be connected to GND.
3. VDD (Pins 44, 53 and 89) must be connected to VDD.
–3–
CXP921000A
AVREF1
AVDD
PJ0/AN4/KS8
PJ1/AN5/KS9
PJ2/AN6/KS10
PJ3/AN7/KS11
PJ4/AN8/KS12
PJ5/AN9/KS13
PJ6/AN10/KS14
PJ7/AN11/KS15
NC
VSS
VDD
PA0/AN12
PA1/AN13
PA2/AN14
PA3/AN15
PA4/AN16
PA5/AN17
PA6/AN18
PA7/AN19
PB0/AN20
PB1/AN21
PB2/AN22
PB3/AN23
Pin Assignment in Piggyback Mode (Top View) 100-pin LQFP package
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
PB4/SI3
1
75
AVREF0
PB5/SO3
2
74
AVss
PB6/SCK3
3
73
AN3
PB7/RMC
4
72
AN2
PC0/SDA0
5
71
AN1
PC1/SCL0
6
70
PI7/AN0
7
A10
1
24
VDD
A23
25
48
VDD
69
PI6/NMI
PC3/SCL1
8
A9
2
23
A11
A22
26
47
CE
68
PI5/INT7
PC4
9
A8
3
22
A12
A21
27
46
NC
67
PI4/INT6
PC5
10
A7
4
21
D7
A20
28
45
D15
66
PI3/INT5
PC6
11
A6
5
20
D6
A19
29
44
D14
65
PI2/INT4
PC7
12
A5
6
19
D5
A18
30
43
D13
64
PI1/INT3
VSS
13
A4
7
18
D4
A17
31
42
D12
63
PI0/INT2
PD0/KS0
14
A3
8
17
D3
A16
32
41
D11
62
PH7/INT1
PD1/KS1
15
A2
9
16
D2
A15
33
40
D10
61
PH6/INT0
PD2/KS2
16
A1
15
D1
A14
39
D9
60
PH5/XOUT
PD3/KS3
17
A0
11
14
D0
A13
35
38
D8
59
PH4/RTO4
PD4/KS4
18
Vss
12
13
Vss
Vss
36
37
Vss
58
PH3/RTO3
PD5/KS5
19
57
PH2/RTO2
PD6/KS6
20
56
PH1/RTO1
PD7/KS7
21
55
PH0/RTO0
PE0
22
54
Vss
PE1
23
53
TX
PE2
24
52
TEX
PE3
25
51
VDD
10
34
PG7/SCK2
PG6/SO2
PG5/SI2
PG4/CS2
PG2/SO1
PG3/SCK1
PG1/SI1
PG0/CS1
VDD
XTAL
EXTAL
VSS
RST
PF7/TMO
PF6/TO
PF5/SCK0
PF4/SO0
PF3/SI0
PF2/CS0
PF1/EC
PF0
PE7
PE6
PE5
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
PE4
PC2/SDA1
Note) 1. NC (Pin 86) must be left open. However, use this pin for FLASH EEPROM
incorporated version.
2. Vss (Pins 13, 39, 54 and 88) must be connected to GND.
3. VDD (Pins 42, 51 and 87) must be connected to VDD.
4. A20 to A23 are always high level output.
–4–
CXP921000A
AVREF1
AVDD
PJ0/AN4/KS8
PJ1/AN5/KS9
PJ2/AN6/KS10
PJ3/AN7/KS11
PJ4/AN8/KS12
PJ5/AN9/KS13
PJ6/AN10/KS14
PJ7/AN11/KS15
NC (PWE)
VDD
VSS
PA0/AN12
PA1/AN13
PA2/AN14
PA3/AN15
PA4/AN16
PA5/AN17
PA6/AN18
PA7/AN19
PB0/AN20
PB1/AN21
PB2/AN22
PB3/AN23
Pin Assignment in Evaluator Mode (Top View) 100-pin LQFP package
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
PB4/SI3
1
75
AVREF0
PB5/SO3
2
74
AVss
PB6/SCK3
3
73
AN3
PB7/RMC
4
72
AN2
PC0/SDA0
5
71
AN1
PC1/SCL0
6
70
PI7/AN0
7
AD10
1
24
VDD
A23
25
48
VDD
69
PI6/NMI
PC3/SCL1
8
AD9
2
23
AD11
A22
26
47
E/P
68
PI5/INT7
PC4
9
AD8
3
22
AD12
A21
27
46
ST0
67
PI4/INT6
PC5
10
AD7
4
21
I/T
A20
28
45
ST1
66
PI3/INT5
PC6
11
AD6
5
20
MON
A19
29
44
ST2
65
PI2/INT4
PC7
12
AD5
6
19
ERST
A18
30
43
ST3
64
PI1/INT3
VSS
13
AD4
7
18
C1
A17
31
42
WTACK
63
PI0/INT2
PD0/KS0
14
AD3
8
17
C2
A16
32
41
JRQH
62
PH7/INT1
PD1/KS1
15
AD2
9
16
QS0
AD15
33
40
JRQL
61
PH6/INT0
PD2/KS2
16
AD1
15
QS1
AD14
39
ENMI
60
PH5/XOUT
PD3/KS3
17
AD0
11
14
QS2
PH4/RTO4
PD4/KS4
18
Vss
12
13
Vss
PD5/KS5
PD6/KS6
PC2/SDA1
10
34
AD13
35
38
MS
59
Vss
36
37
Vss
58
PH3/RTO3
19
57
PH2/RTO2
20
56
PH1/RTO1
PD7/KS7
21
55
PH0/RTO0
PE0
22
54
Vss
PE1
23
53
TX
PE2
24
52
TEX
PE3
25
51
VDD
PG7/SCK2
PG6/SO2
PG5/SI2
PG4/CS2
PG2/SO1
PG3/SCK1
PG1/SI1
PG0/CS1
VDD
EXTAL
VSS
XTAL
RST
PF7/TMO
PF6/TO
PF4/SO0
PF5/SCK0
PF3/SI0
PF2/CS0
PF1/EC
PF0
PE7
PE6
PE5
PE4
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note) 1. NC (Pin 86) must be left open. However, use this pin for FLASH EEPROM
incorporated version.
2. Vss (Pins 13, 39, 54 and 88) must be connected to GND.
3. VDD (Pins 42, 51 and 87) must be connected to VDD.
–5–
CXP921000A
EPROM Read Timing
(Ta = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V)
Item
Symbol
Pins
Min.
Address → data
Input delay time
tACC
A0 to A23
D0 to D15
Address → data
hold time
tIH
A0 to A23
D0 to D15
Max.
Unit
50
ns
0
ns
0.8VDD
A0 to A23
Address data
0.2VDD
tACC
tIH
0.8VDD
D0 to D15
Input data
0.2VDD
Product List
Products
Optional item
Piggy/evaluation chip
Mask ROM
CXP921000A-U01Q
CXP921064A
Package
ROM capacity
Reset pin pull-up resistor
100-pin plastic QFP/LQFP 100-pin ceramic PQFP
104-pin plastic LFLGA
(QFP supported)
CXP921000A-U01R
100-pin ceramic PQFP
(LQFPsupported)
256K bytes
EPROM 256K bytes
Existent/Non-existent
Existent
–6–
CXP921000A
Switching of Piggyback Mode and Evaluator Mode
Piggyback mode can be used by setting two LCC-type EPROM (for upper bytes, for lower byte) and connecting
to the connector of top of the chip.
Evaluator mode can be used by connecting in-circuit emulator CPU probe to the connector of top of the chip.
Piggyback mode
Pin 1 marking
0
For lower bytes
1
For upper bytes
LCC-type PROM
EPROM adaptor
Chip
Evaluator mode
CPU probe
Chip
Notes on PF7 Usage
FLASH EEPROM incorporated PF7 is also used as flash mode setting function. Note the followings:
1. "H" is output to PF7 during a reset. That is driven at comparatively high impedance (approximately 150kΩ),
and take care that VOH should not fall under 0.7VDD by the partial pressure with external circuit load
impedance.
2. When using software reset functions, PF7 may not rise enough during a reset. Switching PF7 to "H" output
prior to software reset execution or connecting pull-up resistor is recommended.
RST
Normal operation
PF7
Flash mode
Keep PF7 above 0.7 VDD during
this period.
Mask ROM and piggy/evaluation chip do not have flash mode setting function. Considering that EEPROM
incorporated type is used, above countermeasure should be performed.
–7–
CXP921000A
Package Outline
Unit: mm
100PIN PQFP(CERAMIC)
24.7 ± 0.5
22.3 ± 0.25
16.3 ± 0.2
0.8 ± 0.1
30
INDEX
0.5 ± 0.25
+ 0.05
0.15 – 0.02
8.6 MAX
1
INDEX
0.65 ± 0.05
31
PACKAGE STRUCTURE
PACKAGE MATERIAL
SONY CODE
EIAJ CODE
CERAMIC
PQFP-100C-L04
LEAD TREATMENT
GOLD PLATING
AQFP100-C-0000
LEAD MATERIAL
42 ALLOY
PACKAGE MASS
4.9g
JEDEC CODE
–8–
0.3 ± 0.08
100
13.9
50
1.5 ± 0.05
81
3.2 ± 0.2
51
3.57 ± 0.36
18.7 ± 0.5
80
18.0
CXP921000A
100PIN PQFP(CERAMIC)
16.0 ± 0.5
51
50
100
26
25
INDEX
+ 0.15
0.2 – 0.13
0.8 ± 0.1
+ 0.05
0.127 – 0.02
1
INDEX
3.2 ± 0.2
+ 0.08
0.18 – 0.03
1.5 ± 0.05
76
8.0 MAX
75
12.4
3.32 ± 0.33
12.0 ± 0.15
0.5± 0.05
14.0 ± 0.2
PACKAGE STRUCTURE
PACKAGE MATERIAL
CERAMIC
SONY CODE
PQFP-100C-L03
LEAD TREATMENT
GOLD PLATING
EIAJ CODE
AQFP100-C-0000
LEAD MATERIAL
42 ALLOY
PACKAGE MASS
2.7g
JEDEC CODE
–9–