CXP922000 Piggy/ CMOS 16-bit Single Chip Microcomputer evaluation type For the availability of this product, please contact the sales office. Description The CXP922000 is a CMOS 16-bit single chip microcomputer of piggyback/evaluator combined type, which is developed for evaluating the function of the CXP922032. 100 pin PQFP (Ceramic) Features • An efficient instruction set as a controller ( QFP supported ) – Direct addressing, numerous abbreviated forms, multiplication and division instructions • Instruction sets for C Ianguage and RTOS – Highly quadratic instruction system, general-purpose register of eight 16-bit × 16-bank configuration • Minimum instruction cycle time 100ns at 20MHz operation (3.0 to 5.5V) 167ns at 12MHz operation (2.7 to 5.5V) • Incorporated EPROM CXP27V1000K • Incorporated RAM capacity 7680 bytes • Peripheral functions – A/D converter 8-bit 8 analog input, successive approximation system (Conversion time: 12.4µs at 20MHz) – Serial interface Asynchronous serial interface (Simple UART) 128-byte buffer RAM, 3 channels – Timers 8-bit timer/counter, 2 channels (with timing output) 16-bit capture timer/counter (with timing output) 16-bit timer, 4 channels – Remote control receive circuit 8-bit pulse measurement counter, 8-stage FIFO – PWM output circuit 14-bit, 1 channel • Interruption 24 factors, 24 vectors, multi-interruption and priority selection possible • Standby mode Sleep/stop • Package 100-pin ceramic PQFP • Mask ROM CXP922032 • One time PROM incorporated type CXP922P032 Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E98Z32B9X-PS CXP922000 PJ0/KS0 PJ1/KS1 PJ2/KS2 PJ3/KS3 PJ4/KS4 PJ5/KS5 PJ6/KS6 NC VDD Vss PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 Pin Assignment in Piggyback Mode 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PB2 1 80 PI7/RMC PB3 2 79 PI6/CINT PB4 3 78 PI5/EC1 PB5 4 77 PI4/EC0 PB6 5 76 PI3 PB7 6 75 PI2 PC0 7 74 PI1/RxD PC1 8 73 PI0/TxD PC2 9 72 PH7/SCK2 PC3 10 A10 1 24 VDD A23 25 48 VDD 71 PH6/SO2 PC4 11 A9 2 23 A11 A22 26 47 CE 70 PH5/SI2 PC5 12 A8 3 22 A12 A21 27 46 NC 69 PH4/CS2 PC6 13 A7 4 21 D7 A20 28 45 D15 68 PH3/SCK1 PC7 14 A6 5 20 D6 A19 29 44 D14 67 PH2/SO1 6 19 D5 A18 30 43 D13 Vss 15 A5 66 PH1/SI1 PD0 16 A4 7 18 D4 A17 31 42 D12 65 PH0/CS1 PD1 17 A3 8 17 D3 A16 32 41 D11 64 Vss PD2 18 A2 9 16 D2 A15 33 40 D10 63 SCK0 PD3 19 A1 10 15 D1 A14 34 39 D9 62 SO0 PD4 20 A0 11 14 D0 A13 35 38 D8 61 SI0 PD5 21 Vss 12 13 Vss Vss 36 37 Vss 60 CS0 PD6 22 59 PG7 PD7 23 58 PG6 PE0 24 57 PG5 PE1 25 56 PG4 PE2 26 55 AVDD PE3 27 54 AVREF PE4 28 53 AVSS PE5 29 52 PG3/AN7 PE6 30 51 PG2/AN6 PG1/AN5 PG0/AN4 AN3 AN2 AN1 AN0 VDD EXTAL XTAL Vss RST PF7/TO1/PWM PF6/TO0 PF5/NMI PF4/INT4 PF3/INT3 PF2/INT2 PF1/INT1 PE7 PF0/INT0 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note) 1. Do not make any connections to NC (Pin 88 ). 2. Vss (Pins 15, 41, 64 and 90) are connected to GND. 3. VDD (Pins 44 and 89) are both connected to VDD. 4. A19 to A23 are always high level output. –2– CXP922000 PJ0/KS0 PJ1/KS1 PJ2/KS2 PJ3/KS3 PJ4/KS4 PJ5/KS5 PJ6/KS6 NC VDD Vss PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 Pin Assignment in Evaluator Mode 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PB2 1 80 PI7/RMC PB3 2 79 PI6/CINT PB4 3 78 PI5/EC1 PB5 4 77 PI4/EC0 PB6 5 76 PI3 PB7 6 75 PI2 PC0 7 74 PI1/RxD PC1 8 73 PI0/TxD PC2 9 72 PH7/SCK2 PC3 10 AD10 1 24 VDD A23 25 48 VDD 71 PH6/SO2 PC4 11 AD9 2 23 AD11 A22 26 47 E/P 70 PH5/SI2 PC5 12 AD8 3 22 AD12 A21 27 46 ST0 69 PH4/CS2 PC6 13 AD7 4 21 I/T A20 28 45 ST1 68 PH3/SCK1 PC7 14 AD6 5 20 MON A19 29 44 ST2 67 PH2/SO1 Vss 15 AD5 6 19 ERST A18 30 43 ST3 66 PH1/SI1 PD0 16 AD4 7 18 C1 A17 31 42 WTACK 65 PH0/CS1 PD1 17 AD3 8 17 C2 A16 32 41 JRQH 64 Vss PD2 18 AD2 9 16 QS0 AD15 33 40 JRQL 63 SCK0 PD3 19 AD1 10 15 QS1 AD14 34 39 ENMI 62 SO0 PD4 20 AD0 11 14 QS2 AD13 35 38 MS 61 SI0 PD5 21 Vss 12 13 Vss Vss 36 37 Vss 60 CS0 PD6 22 59 PG7 PD7 23 58 PG6 PE0 24 57 PG5 PE1 25 56 PG4 PE2 26 55 AVDD PE3 27 54 AVREF PE4 28 53 AVSS PE5 29 52 PG3/AN7 PE6 30 51 PG2/AN6 PG1/AN5 PG0/AN4 AN3 AN2 AN1 AN0 VDD XTAL EXTAL Vss RST PF7/TO1/PWM PF6/TO0 PF5/NMI PF4/INT4 PF3/INT3 PF2/INT2 PF1/INT1 PF0/INT0 PE7 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note) 1. Do not make any connections to NC (Pin 88 ). 2. Vss (Pins 15, 41, 64 and 90) are connected to GND. 3. VDD (Pins 44 and 89) are both connected to VDD. –3– CXP922000 EPROM Read Timing (Ta = –20 to +75°C, VDD = 2.7 to 5.5V, Vss = 0V) Item Symbol Pins Min. Address → data Input delay time tACC A0 to A23 D0 to D15 Address → data hold time tIH A0 to A23 D0 to D15 Max. Unit 100∗1 50∗2 ns 0 ns ∗1 At 12MHz operation (VDD = 3.0 to 5.5V) ∗2 At 12MHz operation (VDD = 2.7 to 5.5V), at 20MHz operation (VDD = 3.0 to 5.5V) 0.8VDD A0 to A23 Address data 0.2VDD tACC tIH 0.8VDD D0 to D7 Input data 0.2VDD Product List Products Optional item Package ROM capacity Reset pin pull-up resistor Mask ROM Piggy/evaluation chip CXP922032 CXP922000-U01Q 100-pin plastic QFP 100-pin ceramic PQFP ( QFP supported ) 128K bytes EPROM 128K bytes Existent/Non-existent Existent –4– CXP922000 Switching of Piggyback Mode and Evaluator Mode Piggyback mode can be used by setting two LCC-type EPROM (for upper bytes, for lower byte) and connecting to the connector of top of the chip. Evaluator mode can be used by connecting in-circuit emulator CPU probe to the connector of top of the chip. Piggyback mode Pin 1 marking 0 For lower bytes 1 For upper bytes LCC-type PROM EPROM adaptor Evaluator mode CPU probe Chip –5– Chip CXP922000 Package Outline Unit: mm 100PIN PQFP(CERAMIC) 24.7 ± 0.5 22.3 ± 0.25 16.3 ± 0.2 0.8 ± 0.1 30 INDEX 0.5 ± 0.25 + 0.05 0.15 – 0.02 8.6 MAX 1 INDEX 0.65 ± 0.05 31 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE CERAMIC PQFP-100C-L04 LEAD TREATMENT GOLD PLATING AQFP100-C-0000 LEAD MATERIAL 42 ALLOY PACKAGE MASS 4.9g JEDEC CODE –6– 0.3 ± 0.08 100 13.9 50 1.5 ± 0.05 81 3.2 ± 0.2 51 3.57 ± 0.36 18.7 ± 0.5 80 18.0