CXP81900 CMOS 8-bit Single Chip Microcomputer Description The CXP81900 is a CMOS 8-bit single chip microcomputer of piggyback/evaluator combined type, which is developed for evaluating the function of the CXP81952/81960. Piggyback/ evaluator type 100 pin PQFP (Ceramic) Features • A wide instruction set (213 instructions) which cover LQFP supported QFP supported various types of data. – 16-bit operation/multiplication and division/ boolean bit operation instructions • Minimum instruction cycle 250ns at 16MHz operation (4.5 to 5.5V) 333ns at 12MHz operation (3.0 to 5.5V) 122µs at 32kHz operation • Applicable EPROM LCC type 27C256, LCC type 27C512 (Maximum 60Kbytes are available.) • Incorporated RAM capacity 2048 bytes • Peripheral functions – A/D converter 8-bit, 12-channel, successive approximation method (Conversion time of 20µs/16MHz) – Serial interface Incorporated buffer RAM (Auto transfer for 1 to 32 bytes), 1 channel Incorporated 8-bit and 8-stage FIFO (Auto transfer for 1 to 8 bytes), 1 channel – Timer 8-bit timer, 8-bit timer/counter 19-bit time base timer 32kHz timer/counter – High precision timing pattern generator PPG 19-pin, 32-stage programmable RTG 5 pins, 2 channels – PWM/DA gate output PWM output 12 bits, 2 channels (Repetitive frequency 62.5kHz/16MHz) DA gate pulse output 13 bits, 4channels – FRC capture unit Incorporated 26-bit and 8-stage FIFO – PWM output 14 bits, 1 channel – Remote control receiving circuit 8-bit pulse measurement counter with on-chip 6-stage FIFO – General purpose prescaler 7 bits (PG5 input frequency division, FRC capture possible.) – HSYNC counter 12-bit event counter (SYNC1 input count) • Interruption 20 factors, 15 vectors, multi-interruption possible • Standby mode SLEEP/STOP • Package 100-pin ceramic PQFP Note) Mask option depends on the type of the CXP81900. Refer to the Products List for details. Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E95828A68-PS CXP81900 PI5/SCK1 PI4/INT1/NMI PI3/TO/ADJ PI2/PWM PI1/RMC TX TEX VDD Vss NC PA7/PPO7 PA6/PPO6 PA5/PPO5 PA4/PPO4 PA3/PPO3 PA2/PPO2 PA1/PPO1 PA0/PPO0 PB7/PPO15 PB6/PPO14 Pin Assignment in Piggyback Mode (QFP package) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PB5/PPO13 1 80 PI6/SO1 PB4/PPO12 2 79 PI7/SI1 PB3/PPO11 3 78 PE0/INT0 PB2/PPO10 4 77 PE1/EC/INT2 74 PE4/DAA0 PC6/RTO6 8 73 PE5/DAA1 PC5/RTO5 9 72 PE6/DAB0 PC4/RTO4 10 71 PE7/DAB1 PC3/RTO3 11 70 PG0 PC2/PPO18 12 69 PG1 68 PG2 67 PG3 66 PG4 65 PG5/PCK 64 PG6/EXI0 63 PG7/EXI1 62 AN0 61 AN1 AN2 PC1/PPO17 13 PC0/PPO16 14 PJ7 15 PJ6 16 PJ5 17 PJ4 18 PJ3 19 PJ2 20 4 A6 3 NC 2 A13 7 A14 PE3/PWM1 PC7/RTO7 VDD PE2/PWM0 75 A15 76 6 A12 5 PB0/PPO8 A7 PB1/PPO9 1 32 31 30 29 5 6 A5 A4 27 CE D7 22 12 D0 A10 23 11 NC OE 24 10 A0 NC 25 9 A1 A11 26 8 A2 A9 28 7 A3 A8 13 D6 21 14 15 16 17 18 19 20 58 PF0/AN4 PD6 24 57 PF1/AN5 PD5 25 56 PF2/AN6 PD4 26 55 PF3/AN7 PD3 27 54 AVDD PD2 28 53 AVREF PD1 29 52 AVss PD0 30 51 PF4/AN8 NC D5 23 D4 AN3 PD7 D3 59 GND 22 D2 21 PJ0 D1 PJ1 60 PF5/AN9 PF6/AN10 PF7/AN11 SO0 SCK0 SI0 CS0 EXTAL Vss XTAL RST MP PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note) 1. NC (Pin 90) is always connected to VDD. 2. VSS (Pins 41 and 88) are both connected to GND. 3. MP (Pin 39) is always connected to GND. –2– CXP81900 PE0/INT0 PI7/SI1 PI6/SO1 PI5/SCK1 PI4/INT1/NMI PI3/TO/ADJ PI2/PWM PI1/RMC TEX TX VDD Vss NC PA7/PPO7 PA6/PPO6 PA5/PPO5 PA4/PPO4 PA3/PPO3 PA2/PPO2 PA1/PPO1 PA0/PPO0 PB7/PPO15 PB6/PPO14 PB5/PPO13 PB4/PPO12 Pin Assignment in Piggyback Mode (LQFP package) AA 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PB3/PPO11 75 PE1/EC/INT2 74 PE2/PWM0 73 PE3/PWM1 72 PE4/DAA0 5 71 PE5/DAA1 6 70 PE6/DAB0 69 PE7/DAB1 68 PG0 67 PG1 66 PG2 65 PG3 64 PG4 63 PG5/PCK 62 PG6/EXI0 61 PG7/EXI1 60 AN0 59 AN1 58 AN2 57 AN3 56 PF0/AN4 1 PB2/PPO10 2 PB1/PPO9 3 PB0/PPO8 4 PC7/RTO7 PC6/RTO6 A15 1 28 VDD A12 2 27 A14 A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 OE A2 8 21 A10 A1 9 20 CE A0 10 19 D7 D0 11 18 D6 D1 12 17 D5 D2 13 16 D4 GND 14 15 D3 PC5/RTO5 7 PC4/RTO4 8 PC3/RTO3 9 PC2/PPO18 10 PC1/PPO17 11 PC0/PPO16 12 PJ7 13 PJ6 14 PJ5 15 PJ4 16 PJ3 17 PJ2 18 PJ1 19 PJ0 20 PD7 21 55 PF1/AN5 PD6 22 54 PF2/AN6 PD5 23 53 PF3/AN7 PD4 24 52 AVDD PD3 25 51 AVREF Note) 1. NC (Pin 88) is always connected to VDD. 2. VSS (Pins 39 and 86) are both connected to GND. 3. MP (Pin 37) is always connected to GND. –3– AVss PF4/AN8 PF5/AN9 PF6/AN10 PF7/AN11 SCK0 SO0 SI0 CS0 EXTAL XTAL Vss RST MP PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 PD0 PD1 PD2 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CXP81900 PI5/SCK1 PI4/INT1/NMI PI3/TO/ADJ PI2/PWM PI1/RMC TEX TX Vss VDD NC PA7/PPO7 PA6/PPO6 PA5/PPO5 PA4/PPO4 PA3/PPO3 PA2/PPO2 PA1/PPO1 PA0/PPO0 PB7/PPO15 PB6/PPO14 Pin Assignment in Evaluator Mode (QFP package) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 78 PE0/INT0 PB2/PPO10 4 77 PE1/EC/INT2 PB1/PPO9 5 76 PE2/PWM0 PB0/PPO8 6 75 PE3/PWM1 PC7/RTO7 7 74 PE4/DAA0 A12 A13 3 A14 PI7/SI1 PB3/PPO11 VDD PI6/SO1 79 NC 80 2 A15 1 PB4/PPO12 A7/D7 PB5/PPO13 PC6/RTO6 8 73 PE5/DAA1 PC5/RTO5 9 72 PE6/DAB0 PC4/RTO4 10 71 PE7/DAB1 PC3/RTO3 11 70 PG0 PC2/PPO18 12 69 PG1 68 PG2 67 PG3 66 PG4 65 PG5/PCK 64 PG6/EXI0 63 PG7/EXI1 62 AN0 61 AN1 A6/D6 2 3 4 1 32 31 30 29 5 6 A5/D5 A8 A9 28 PC1/PPO17 13 PC0/PPO16 14 PJ7 15 PJ6 16 PJ5 17 PJ4 18 PJ3 19 PJ2 20 PJ1 21 60 AN2 PJ0 22 59 AN3 PD7 23 58 PF0/AN4 PF1/AN5 27 7 A4/D4 A3/D3 A11 26 8 NC A2/D2 9 25 HALT A1/D1 10 24 A10 A0/D0 23 11 NC 22 12 RD E/P 13 I/T MON 21 RST C1 C2 NC GND SYNC WR 14 15 16 17 18 19 20 PD6 24 57 PD5 25 56 PF2/AN6 PD4 26 55 PF3/AN7 PD3 27 54 AVDD PD2 28 53 AVREF PD1 29 52 AVss PD0 30 51 PF4/AN8 PF5/AN9 PF6/AN10 PF7/AN11 SO0 SCK0 SI0 CS0 EXTAL Vss XTAL RST MP PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note) 1. NC (Pin 90) is always connected to VDD. 2. VSS (Pins 41 and 88) are both connected to GND. 3. MP (Pin 39) is always connected to GND. –4– CXP81900 PE0/INT0 PI7/SI1 PI6/SO1 PI5/SCK1 PI4/INT1/NMI PI3/TO/ADJ PI2/PWM PI1/RMC TEX TX VDD Vss NC PA7/PPO7 PA6/PPO6 PA5/PPO5 PA4/PPO4 PA3/PPO3 PA2/PPO2 PA1/PPO1 PA0/PPO0 PB7/PPO15 PB6/PPO14 PB4/PPO12 PB5/PPO13 Pin Assignment in Evaluator Mode (LQFP package) A 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 PE1/EC/INT2 74 PE2/PWM0 73 PE3/PWM1 4 72 PE4/DAA0 PC7/RTO7 5 71 PE5/DAA1 PC6/RTO6 6 70 PE6/DAB0 PC5/RTO5 7 69 PE7/DAB1 PC4/RTO4 8 68 PG0 PC3/RTO3 9 PC2/PPO18 10 PC1/PPO17 11 PC0/PPO16 12 PJ7 13 PJ6 14 PJ5 15 PJ4 16 PJ3 17 PJ2 18 PJ1 19 PJ0 20 PD7 PB3/PPO11 1 PB2/PPO10 2 PB1/PPO9 3 PB0/PPO8 A15 1 28 VDD A12 2 27 A14 A7/D7 3 26 A13 67 PG1 A6/D6 4 25 A8 66 PG2 A5/D5 5 24 A9 65 PG3 A4/D4 6 23 A11 64 PG4 A3/D3 7 22 HALT 63 PG5/PCK A2/D2 8 21 A10 62 PG6/EXI0 A1/D1 9 20 E/P 61 PG7/EXI1 A0/D0 10 19 I/T 60 AN0 RD 11 18 MON 59 AN1 WR 12 17 RST 58 AN2 SYNC 13 16 C1 57 AN3 GND 14 15 C2 56 PF0/AN4 21 55 PF1/AN5 PD6 22 54 PF2/AN6 PD5 23 53 PF3/AN7 PD4 24 52 AVDD PD3 25 51 AVREF Note) 1. NC (Pin 88) is always connected to VDD. 2. VSS (Pins 39 and 86) are both connected to GND. 3. MP (Pin 37) is always connected to GND. –5– AVss PF4/AN8 PF5/AN9 PF6/AN10 PF7/AN11 SCK0 SO0 SI0 CS0 EXTAL XTAL Vss RST MP PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 PD0 PD1 PD2 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CXP81900 EPROM Read Timing (Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V) Item Symbol Pin Min. Address → data input delay time tACC A0 to A15 D0 to D7 Address → data hold time tIH A0 to A15 D0 to D7 Max. Unit 100∗1 75∗2 ns 0 ns ∗1 At 12MHz operation (VDD = 4.5 to 5.5V) ∗2 At 12MHz operation (VDD = 3.0 to 5.5V), At 16MHz operation (VDD = 4.5 to 5.5V) 0.8VDD A0 to A15 Address data 0.2VDD tACC tIH 0.8VDD D0 to D7 Input data 0.2VDD Products List Products Option item CXP81952 Package ROM capacity Piggyback/evaluator product Mask product CXP81960 CXP81900-U03Q CXP81900-U04Q CXP81900-U06R CXP81900-U03R CXP81900-U04R 100-pin plastic QFP/LQFP 52Kbytes 60Kbytes Pull-up resistor for reset pin Existent/Non-existent Supply voltage 3.0 to 5.5V 100-pin ceramic PQFP EPROM 60Kbytes 27C512 × 1 27C512 × 1 27C256 × 2 Existent 4.5 to 5.5V –6– 3.0 to 5.5V 3.0 to 5.5V CXP81900 Piggyback mode/evaluator mode can be switched as shown below. Piggyback mode Evaluator mode Piggyback/evaluator product Pin 1 marking LCC type EPROM Pin 1 marking Pin 1 index Note) CPU probe (27C512 only) EPROM adaptor Pin 1 marking Pin 1 index Note) Evaluation cap should be connected to CPU probe. U03R and U04R used CPU probe for LQFP LCC type EPROM for low voltage Pin 1 marking For lower address EPROM adaptor Pin 1 marking U06R used For upper address (27C256 only) Lower address Upper address –7– Address Memory space EPROM (27C256) Lower 1000H to 7FFFH 1000H to 7FFFH Upper 8000H to FFFFH 0000H to 7FFFH CXP81900 Package Outline Unit: mm PIN NO. 1 INDEX 18.7 100PIN PQFP (CERAMIC) 16.3 ± 0.2 INDEX 100 81 81 80 PIN No. 1 INDEX 1 80 0.65 ± 0.05 1 100 0.3 ± 0.08 14.22 18.12 ± 0.2 1.27 ± 0.13 12.02 30 0.7 1.0 0.3 6.0 24.7 22.3 ± 0.25 4.5 51 31 1.3 ± 0.3 51 50 9.48 11.66 30 50 31 0.45 15.58 ± 0.2 PACKAGE STRUCTURE PACKAGE MATERIAL PQFP-100C-L01 LEAD TREATMENT GOLD PLATING EIAJ CODE AQFP100-C-0000-A LEAD MATERIAL 42 ALLOY PACKAGE WEIGHT 5.7g 10.44 MAX + 0.05 0.15 – 0.02 0.50 ± 0.25 JEDEC CODE 3.57 ± 0.36 CERAMIC SONY CODE 100PIN PQFP (CERAMIC) 16.0 ± 0.4 12.4 14.0 ± 0.2 75 51 76 0.5 ± 0.05 + 0.08 0.18 – 0.03 1.5 3.2 ± 0.2 0.5 ± 0.05 12.0 ± 0.15 + 0.08 0.18 – 0.03 0.8 ± 0.2 26 100 1 INDEX 12.0 ± 0.15 50 25 12.8 ± 0.2 INDEX 6.9 + 0.15 0.2 – 0.13 + 0.05 0.127 – 0.02 3.32 PACKAGE STRUCTURE PACKAGE MATERIAL CERAMIC SONY CODE PQFP-100C-L02 LEAD TREATMENT GOLD PLATING EIAJ CODE AQFP100-C-1414-A LEAD MATERIAL 42 ALLOY PACKAGE WEIGHT 2.2g JEDEC CODE –8–