CXP974F096
CMOS 16-bit Single Chip Microcomputer
Description
The CXP974F096 is a CMOS 16-bit microcomputer
integrating on a single chip an A/D converter, serial
interface, I2C bus interface, timer, PWM output
circuit, programmable pattern generator, remote
control receive circuit, parallel interface, FLASH
ROM interface, and as well as basic configurations
like a 16-bit CPU, FLASH EEPROM, RAM, and I/O
port.
This LSI also provides the sleep/stop functions that
enable lower power consumption.
100 pin QFP (Plastic)
100 pin LQFP (Plastic)
Features
• An efficient instruction set as a controller
— Direct addressing, numerous abbreviated forms,
multiplication and division instructions
• Instruction sets for C language and RTOS
— Highly quadratic instruction system, generalpurpose register of 16-bit × 8-pin × 16-bank configuration
• Minimum instruction cycle
58.8ns at 34MHz operation (3.0 to 3.6V)
66.7ns at 30MHz operation (2.7 to 3.6V)
• Incorporated FLASH EEPROM capacity
384K bytes
• Incorporated RAM capacity
23.5K bytes
• Peripheral functions
— A/D converter
8-bit 12-analog input, successive approximation system,
3-stage FIFO (Conversion time: 1.55µs at 40MHz)
— Serial interface
Asynchronous serial interface (UART)
128-byte buffer RAM, 3 channels
— I2C bus interface
64-byte buffer RAM
(supports master/slave and automatic transfer mode)
— Timers
8-bit timer/counter, 2 channels (with timing output)
16-bit capture timer/counter (with timing output)
16-bit timer, 4 channels, watchdog timer
— PWM output circuit
14-bit PWM, 4 channels
(2-channel of binary output switch function by PPG)
— Programmable pattern generator 16-bit output, 64-byte buffer RAM, 1 channel
— Remote control receive circuit
8-bit pulse measurement counter, 10-stage FIFO
— Parallel interface
External register interface (8-bit parallel bus), 4-chip select
• Interruption
• Standby mode
• Package
• Piggy/evaluation chip
• Mask ROM
33 factors, 33 vectors, multi-interruption and priority selection possible
Sleep/stop
100-pin plastic QFP
100-pin plastic LQFP
CXP971000
CXP974096
Structure
Silicon gate CMOS IC
Perchase of Sony's I2C components conveys a licence under the Philips I2C Patent Rights to use these components
in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E00Z18-PS
SERIAL
INTERFACE
UNIT (CH2)
SCS2
SI2
SO2
SCK2
BUFFER
RAM
REMOCON
FIFO
2CH 14-BIT PWM (PPG)
PWM1
PWM0
RMC
2CH 14-BIT PWM
4CH 16-BIT TIMER
16-BIT CAPTURE
TIMER/COUNTER (CH2)
8-BIT TIMER (CH1)
8-BIT TIMER/COUNTER (CH0)
I2C BUS
INTERFACE
UNIT
BUFFER
RAM
BUFFER
RAM
BUFFER
RAM
PWM3
PWM2
EC2
CINT
T2
T1
EC0
SCL
SDA
UART
SERIAL
INTERFACE
UNIT (CH1)
SCS1
SI1
SO1
SCK1
TxD
RxD
SERIAL
INTERFACE
UNIT (CH0)
4
2
2
3
2
INT0
to INT7
KS0
to KS19
16
12
A/D
CONVERTER
FLASH
EEPROM
384K
BYTES
SPC970
CPU CORE
PROGRAMABLE
PATTEERN
GENERATOR
NMI
FIFO
INTERRUPT CONTROLLER
BUFFER RAM
PPO00
to PPO15
8
16
EXT. REGISTERS
INTERFACE
WATCHDOG TIMER
PRESCALER/
TIME-BASE TIMER
RAM
23.5K
BYTES
CLOCK GENERATOR/
SYSTEM CONTROLLER
VPP
XCS3
XCS2
XCS1
XCS0
SCS0
SI0
SO0
SCK0
A0 to A15
20
D0 to D7
8
ADTEN
ADTRG
AVSS
AVREF
AVDD
AN0
to AN11
EXTAL
XTAL
RST
VDD
VSS
XRD
XWR
PORT A
PORT B
PORT C
PORT D
PORT E
PORT F
PORT G
PK0 to PK4
PK5 to PK6
2
PJ0 to PJ7
PI0 to PI7
5
8
4
PH0, PH1,
PH6, PH7
PH2 to PH5
PG4 to PG7
4
4
PG0 to PG3
4
PE0 to PE7
8
PF6, PF7
PD0 to PD7
8
2
PC0 to PC7
8
PF0 to PF5
PB0 to PB7
8
6
PA0 to PA7
8
8
PORT H
PORT I
PORT J
–2–
PORT K
Block Diagram
CXP974F096
CXP974F096
PH1/SCL
PH2/RxD
PH3/TxD
PH4/RMC
PH5/TETC
PH6/XWR
PH7/XRD
VPP
VDD
VSS
PA0/A0
PA1/A1
PA2/A2
PA3/A3
PA4/A4
PA5/A5
PA6/A6
PA7/A7
PB0/PPO00/A8
PB1/PPO01/A9
Pin Assignment 1 (Top View) 100-pin QFP package
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
PB2/PPO02/A10
1
80
PH0/SDA
PB3/PPO03/A11
2
79
PK6/TETA
PB4/PPO04/A12
3
78
PK5/TETB
PB5/PPO05/A13
4
77
PK4/ADTRG
PB6/PPO06/A14
5
76
PK3/ADTEN
PB7/PPO07/A15
6
75
PK2
PC0/PPO08
7
74
PK1
PC1/PPO09
8
73
PK0
PC2/PPO10
9
72
AVDD
PC3/PPO11
10
71
AVREF
PC4/PPO12/XCS3
11
70
AVSS
PC5/PPO13/XCS2
12
69
PJ7/AN11/KS11
PC6/PPO14/XCS1
13
68
PJ6/AN10/KS10
PC7/PPO15/XCS0
14
67
PJ5/AN9/KS9
VSS
15
66
PJ4/AN8/KS8
PD0/D0/KS12
16
65
PJ3/AN7/KS7
PD1/D1/KS13
17
64
PJ2/AN6/KS6
PD2/D2/KS14
18
63
PJ1/AN5/KS5
PD3/D3/KS15
19
62
PJ0/AN4/KS4
PD4/D4/KS16
20
61
PI7/AN3/KS3
PD5/D5/KS17
21
60
PI6/AN2/KS2
PD6/D6/KS18
22
59
PI5/AN1/KS1
PD7/D7/KS19
23
58
PI4/AN0/KS0
PE0/INT0
24
57
Vss
PE1/INT1
25
56
PI3/SCK2
PE2/INT2
26
55
PI2/SO2
PE3/INT3
27
54
PI1/SI2
PE4/INT4
28
53
PI0/SCS2
PE5/INT5
29
52
PG7/SCK0
PE6/INT6
30
51
PG6/SO0
PG5/SI0
PG4/SCS0
PG3/PWM3
PG2/PWM2
PG1/PWM1
VDD
PG0/PWM0
EXTAL
XTAL
VSS
RST
PF7/T2
PF6/T1
PF5/SCK1
PF4/SO1
PF3/SI1
PF2/SCS1/NMI
PF1/EC2
PF0/EC0
PE7/INT7/CINT
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note) 1. VPP (Pin 88) must be connected to NC for Mask ROM.
2. Vss and AVss (Pins 15, 41, 57, 70 and 90) must be connected to GND.
3. VDD and AVDD (Pins 44, 72 and 89) must be connected to VDD.
–3–
CXP974F096
PK5/TETB
PK6/TETA
PH0/SDA
PH1/SCL
PH2/RxD
PH3/TxD
PH4/RMC
PH5/TETC
PH6/XWR
PH7/XRD
VPP
VDD
VSS
PA0/A0
PA1/A1
PA2/A2
PA3/A3
PA4/A4
PA5/A5
PA6/A6
PA7/A7
PB0/PPO00/A8
PB1/PPO01/A9
PB2/PPO02/A10
PB3/PPO03/A11
Pin Assignment 2 (Top View) 100-pin LQFP package
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
PB4/PPO04/A12
1
75
PK4/ADTRG
PB5/PPO05/A13
2
74
PK3/ADTEN
PB6/PPO06/A14
3
73
PK2
PB7/PPO07/A15
4
72
PK1
PC0/PPO08
5
71
PK0
PC1/PPO09
6
70
AVDD
PC2/PPO10
7
69
AVREF
PC3/PPO11
8
68
AVSS
PC4/PPO12/XCS3
9
67
PJ7/AN11/KS11
PC5/PPO13/XCS2
10
66
PJ6/AN10/KS10
PC6/PPO14/XCS1
11
65
PJ5/AN9/KS9
PC7/PPO15/XCS0
12
64
PJ4/AN8/KS8
VSS
13
63
PJ3/AN7/KS7
PD0/D0/KS12
14
62
PJ2/AN6/KS6
PD1/D1/KS13
15
61
PJ1/AN5/KS5
PD2/D2/KS14
16
60
PJ0/AN4/KS4
PD3/D3/KS15
17
59
PI7/AN3/KS3
PD4/D4/KS16
18
58
PI6/AN2/KS2
PD5/D5/KS17
19
57
PI5/AN1/KS1
PD6/D6/KS18
20
56
PI4/AN0/KS0
PD7/D7/KS19
21
55
Vss
PE0/INT0
22
54
PI3/SCK2
PE1/INT1
23
53
PI2/SO2
PE2/INT2
24
52
PI1/SI2
PE3/INT3
25
51
PI0/SCS2
PG7/SCK0
PG6/SO0
PG5/SI0
PG4/SCS0
PG3/PWM3
PG2/PWM2
PG1/PWM1
PG0/PWM0
VDD
EXTAL
XTAL
VSS
RST
PF7/T2
PF6/T1
PF5/SCK1
PF4/SO1
PF3/SI1
PF2/SCS1/NMI
PF1/EC2
PF0/EC0
PE7/INT7/CINT
PE6/INT6
PE5/INT5
PE4/INT4
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note) 1. VPP (Pin 86) must be connected to NC for Mask ROM.
2. Vss and AVss (Pins 13, 39, 55, 68 and 88) must be connected to GND.
3. VDD and AVDD (Pins 42, 70 and 87) must be connected to VDD.
–4–
CXP974F096
Pin Functions
Symbol
PA0/A0
to PA7/A7
I/O
Functions
(Port A)
Output / Output 8-bit output port.
(8 pins)
PB0/PPO00/
Output /
A8
to PB7/PPO07/ Output / Output
A15
PC0/PPO08
I/O / Output
to PC3/PPO11
PC4/PPO12/
I/O / Output /
XCS3
to PC7/PPO15/ Output
XCS0
External register interface address bus port
output data value and OR output.
(8 pins)
(Port B)
8-bit output port. PPO
value and OR output.
(8 pins)
(Port C)
8-bit I/O port. I/O can
be specified in 1-bit
units. PPO value and
OR output.
(8 pins)
(Port D)
8-bit I/O port. I/O can
be specified in 1-bit
units.
(8 pins)
External register interface address bus.
Address width can be extended in 1-bit
units.
(8 pins)
Programmable pattern generator outputs.
(16 pins)
External register interface chip select
signal. Chip select signal output function
can be selected in 1-bit units.
(4 pins)
Standby release input
function can be
specified in 1-bit units.
(8 pins)
PD0/D0/
KS12
to PD7/D7/
KS19
I/O / I/O / Input
PE0/INT0
to PE6/INT6
I/O / Input
PE7/INT7/
CINT
I/O / Input /
Input
PF0/EC0
PF1/EC2
Input / Input
External event inputs for 8-bit timer/counter.
(2 pins)
PF2/SCS1/
NMI
Input / Input /
Input
Serial chip select
(CH1) input.
PF3/SI1
Input / Input
PF4/SO1
Input / Output
PF5/SCK1
Input / I/O
PF6/T1
Output / Output
8-bit timer/counter output.
PF7/T2
Output / Output
16-bit capture timer/counter timing output.
(Port E)
8-bit I/O port. I/O can
be specified in 1-bit
units. (8 pins)
(Port F)
8-bit port. Lower 6 bits
are for input; upper 2
bits are for output.
(8 pins)
PG0/PWM0
Output / Output
to PG1/PWM1
PG6/SO0
(Port G)
8-bit port. Lower 4 bits
Output / Output
are for output; upper 4
bits are for I/O. Upper
I/O / Input
4 bits can be specified
I/O / Input
in 1-bit units.
(8 pins)
I/O / Output
PG7/SCK0
I/O / I/O
PG2/PWM2
PG3/PWM3
PG4/SCS0
PG5/SI0
External register
interface data bus.
(8 pins)
External interrupt inputs.
(8 pins)
External capture input for 16-bit capture
timer/counter.
Serial data (CH1) input.
Serial data (CH1) output.
Serial clock (CH1) I/O.
14-bit PWM output with output value switch
control by programmable pattern generator.
(2 pins)
14-bit PWM output.
(2 pins)
Serial chip select (CH0) input.
Serial data (CH0) input.
Serial data (CH0) output.
Serial clock (CH0) I/O.
–5–
Non-maskable external
interrupt input.
CXP974F096
Symbol
I/O
Functions
PH0/SDA
Output / I/O
I2C
PH1/SCL
Output / I/O
I2C bus interface clock I/O.
PH2/RxD
I/O / Input
PH3/TxD
I/O / Output
PH4/RMC
I/O / Input
PH5/TETC
I/O / Input
PH6/XWR
Output / Output
PH7/XRD
Output / Output
External register interface read signal.
PI0/SCS2
I/O / Input
Serial chip select (CH2) input.
PI1/SI2
I/O / Input
PI2/SO2
I/O / Output
PI3/SCK2
I/O / I/O
PI4/AN0/
KS0
to PI7/AN3/
KS3
I/O / Input /
Input
(Port H)
8-bit port. Lower 2 bits
are for large current
N-ch open drain
outputs; medium 4 bits
are for I/O; upper 2 bits
are for output. Medium
4 bits can be specified
in 1-bit units.
(8 pins)
bus interface data I/O.
UART reception data input. (common with data
reception during on-board rewrite boot mode)
UART transmission data output. (common with
data transmission during on-board rewrite boot
mode)
Remote control signal input.
On-board rewrite boot mode setting. (Total 3 pins)
External register interface write signal.
Serial data (CH2) input.
(Port I)
8-bit I/O port. I/O can
be specified in 1-bit
units.
(8 pins)
(Port J)
8-bit I/O port. I/O can
be specified in 1-bit
units.
(8 pins)
Serial data (CH2) output.
Serial clock (CH2) I/O.
Analog input for
A/D converter.
(12 pins)
Standby release input
function can be
specified in 1-bit units.
(12 pins)
PJ0/AN4/
KS4
to PJ7/AN11/
KS11
I/O / Input /
Input
PK0 to PK2
I/O
PK3/ADTEN
I/O / Input
PK4/ADTRG
I/O / Input
PK5/TETB
Output / Input
PK6/TETA
Output / Input
EXTAL
Input
Connects a crystal for main clock oscillation. (When the clock is supplied
externally, input it to EXTAL and input an opposite phase clock to XTAL.)
Input
System reset. Active at "L" level.
XTAL
RST
A/D converter operation enable input by external
trigger.
External trigger input for A/D converter.
On-board rewrite boot mode setting.
(Total 3 pins)
Positive power supply for A/D converter. (Must be the same voltage with
VDD.)
AVDD
AVREF
(Port K)
7-bit port. Lower 5 bits
are for I/O; upper 2 bits
are for output. Lower
5 bits can be specified
in 1-bit units.
(7 pins)
Input
Reference voltage input for A/D converter. (Must be the same voltage with
VDD.)
AVss
GND for A/D converter.
VPP
Positive power supply for FLASH EEPROM rewrite.
VDD
Positive power supply. (Connect both VDD pins to positive power supply.)
Vss
GND (Connect all four Vss pins to GND.)
–6–
CXP974F096
I/O Circuit Format for Pins
Pin
Circuit format
After a reset
A0 to A7
PA register
PA0/A0
to PA7/A7
(Undefined after a reset)
Hi-Z
Internal
data bus
RD
PA register write
S
Reset
R
Q
Address width
setting
("0" after a reset)
A8 to A15
PB0/PPO00/A8
to PB7/PPO07/
A15
PPO00 to PPO07
1
MPX
0
Hi-Z
PB register
(Undefined after a reset)
Internal
data bus
PB register write
RD
Reset
S
Q
R
PPO08 to PPO11
PC register
("0" after a reset)
PC0/PPO08
to PC3/PPO11
Input
IP protection
circuit
PCD register
("0" after a reset)
Internal
data bus
RD
–7–
Hi-Z
CXP974F096
Pin
Circuit format
After a reset
XCS output setting
("0" after a reset)
XCS3 to XCS0
PPO12 to PPO15
PC4/PPO12/
XCS3
to PC7/PPO15/
XCS0
1
MPX
0
PC register
Hi-Z
("0" after a reset)
PCD register
IP
("0" after a reset)
Internal
data bus
RD
WR (external register area)
External register
I/F
Internal data bus
External register operation enable
CLR
PD register
∗
("0" after a reset)
CLR
PD0/D0/KS12
to PD7/D7/
KS19
PDD register
IP
("0" after a reset)
Hi-Z
Internal data bus
RD
Standby release
Internal data bus
External register
I/F
External register operation enable
RD (external register area)
∗
Large current drive
5mA (VDD = 2.7 to 3.6V)
PE register
(Undefined after a reset)
PE0/INT0
to PE7/INT7/
CINT
PED register
IP
("0" after a reset)
Internal data bus
RD
INT0 to INT7/CINT
CMOS Schmitt input
–8–
Hi-Z
CXP974F096
Pin
Circuit format
After a reset
IP
EC0, EC2
PF0/EC0
PF1/EC2
Hi-Z
CMOS Schmitt input
Internal data bus
RD
Internal data bus
IP
CMOS Schmitt input
RD
PF2/SCS1/
NMI
SCS1
Hi-Z
PFSL register
("0" after a reset)
NMI
NMI input enable
("0" after a reset)
Internal data bus
IP
CMOS Schmitt input
RD
PF3/SI1
SI1
Hi-Z
PFSL register
("0" after a reset)
SO1
SO1 output enable
PF4/SO1
Hi-Z
PFSL register
IP
("0" after a reset)
Internal data bus
RD
SCK1
SCK1 output enable
PF5/SCK1
Hi-Z
PFSL register
IP
("0" after a reset)
Internal data bus
CMOS Schmitt input
RD
SCK1
–9–
CXP974F096
Pin
Circuit format
After a reset
1
MPX
0
T1
PF register
("1" after a reset)
PF6/T1
"H" level
PFSL register
("0" after a reset)
Internal data bus
RD
∗
1
MPX
0
T2
PF register
"H" level
("H" level at ON
resistance of
pull-up transistor
by a reset.)
("1" after a reset)
PF7/T2
PFSL register
("0" after a reset)
Internal data bus
RD
PF register write
S
Reset
R
Q
∗ Pull-up
transistor
approximately 150kΩ (VDD = 2.7 to 3.6V)
1
MPX
0
PWM0 to PWM3
PG register
(Undefined after a reset)
PG0/PWM0
to PG3/PWM3
PGSL register
Hi-Z
("0" after a reset)
Internal data bus
RD
PG register write
S
Reset
R
– 10 –
Q
CXP974F096
Pin
Circuit format
After a reset
PG register
(Undefined after a reset)
PGD register
("0" after a reset)
PGSL register
PG4/SCS0
IP
("0" after a reset)
Hi-Z
SCS0
Internal data bus
CMOS Schmitt input
RD
PG register
(Undefined after a reset)
PGD register
("0" after a reset)
PGSL register
PG5/SI0
IP
("0" after a reset)
Hi-Z
SI0
Internal data bus
CMOS Schmitt input
RD
SO0
PG register
1
MPX
0
(Undefined after a reset)
PGSL register
("0" after a reset)
PG6/SO0
SO0 output enable
PGD register
IP
1
MPX
0
("0" after a reset)
Internal
data bus
RD
– 11 –
Hi-Z
CXP974F096
Pin
Circuit format
After a reset
1
MPX
0
SCK0
PG register
(Undefined after a reset)
PGSL register
("0" after a reset)
IP
1
MPX
0
SCK0 output enable
PG7/SCK0
PGD register
Hi-Z
("0" after a reset)
Internal
data bus
RD
SCK0
CMOS Schmitt input
1
MPX
0
SDA, SCL
PH register
∗
("1" after a reset)
PHSL register
PH0/SDA
PH1/SCL
("0" after a reset)
Hi-Z
IP
Internal data bus
RD
SDA, SCL
CMOS Schmitt input
∗
Large current drive
5mA (VDD = 2.7 to 3.6V)
PHL register
(Undefined after a reset)
PHD register
PH2/RxD
IP
Hi-Z
("0" after a reset)
Internal data bus
RD
CMOS Schmitt input
RxD
– 12 –
CXP974F096
Pin
Circuit format
After a reset
1
MPX
0
TxD
PH register
(Undefined after a reset)
TxD output enable
Hi-Z
PH3/TxD
PHD register
IP
("0" after a reset)
Internal
data bus
RD
PH register
(Undefined after a reset)
PHD register
PH4/RMC
IP
Hi-Z
("0" after a reset)
Internal data bus
RD
CMOS Schmitt input
RMC
PH register
(Undefined after a reset)
PHD register
PH5/TETC
IP
Hi-Z
("0" after a reset)
Internal data bus
RD
CMOS Schmitt input
PHSL register
("0" after a reset)
1
MPX
0
XWR, XRD
PH6/XWR
PH7/XRD
PH register
Hi-Z
(Undefined after a reset)
Internal
data bus
RD
PH register write
S
Reset
R
– 13 –
Q
CXP974F096
Pin
Circuit format
After a reset
PI register
(Undefined after a reset)
PID register
("0" after a reset)
PISL register
PI0/SCS2
Hi-Z
IP
("0" after a reset)
SCS2
Internal data bus
CMOS Schmitt input
RD
PI register
(Undefined after a reset)
PID register
("0" after a reset)
PISL register
PI1/SI2
IP
("0" after a reset)
Hi-Z
SI2
Internal data bus
CMOS Schmitt input
RD
SO2
PI register
1
MPX
0
(Undefined after a reset)
PISL register
("0" after a reset)
PI2/SO2
SO2 output enable
PID register
IP
1
MPX
0
("0" after a reset)
Internal
data bus
RD
– 14 –
Hi-Z
CXP974F096
Pin
Circuit format
After a reset
1
MPX
0
SCK2
PI register
(Undefined after a reset)
PISL register
("0" after a reset)
IP
1
MPX
0
SCK2 output enable
PI3/SCK2
PID register
Hi-Z
("0" after a reset)
Internal data bus
RD
CMOS Schmitt input
SCK2
PI register
(Undefined after a reset)
PID register
("0" after a reset)
PISL register
PI4/AN0/KS0
to PI7/AN3/
KS3
("0" after a reset)
IP
Hi-Z
IP
Hi-Z
Internal data bus
RD
Standby release
A/D converter
Input multiplexer
PJ register
(Undefined after a reset)
PJD register
("0" after a reset)
PJ0/AN4/KS4
to PJ7/AN11/
KS11
PJSL register
("0" after a reset)
Internal data bus
RD
Standby release
A/D converter
Input multiplexer
– 15 –
CXP974F096
Pin
Circuit format
After a reset
PK register
(Undefined after a reset)
PK0 to PK2
PKD register
IP
Hi-Z
("0" after a reset)
Internal data bus
RD
PK register
(Undefined after a reset)
PK3/ADTEN
PK4/ADTRG
PKD register
IP
Hi-Z
("0" after a reset)
Internal data bus
RD
ADTEN, ADTRG
CMOS Schmitt input
PK register
PK5/TETB
"H" level
("1" after a reset)
Internal data bus
RD
∗
PK register
"H" level
("H" level at ON
resistance of
pull-up transistor
by a reset.)
("1" after a reset)
PK6/TETA
Internal data bus
RD
PK register write
S
Reset
R
Q
∗ Pull-up
transistor
approximately 150kΩ (VDD = 2.7 to 3.6V)
– 16 –
CXP974F096
Pin
Circuit format
EXTAL
XTAL
EXTAL
After a reset
IP
Timing
generator
Oscillation
stop control
Oscillation
XTAL
• Diagram shows circuit configuration during oscillation.
• Feedback resistor is reoved during standby stop mode,
and XTAL is driven at "H" level.
Mask option
∗
OP
RST
RST
Internal reset circuit
IP
CMOS Schmitt input
∗ Pull-up
transistor
approximately 30kΩ (VDD = 2.7 to 3.6V)
– 17 –
"L" level
(during a reset)
CXP974F096
Absolute Maximum Ratings
Item
(Vss = 0V reference)
Symbol
Rating
Unit
V
AVDD
–0.3 to +4.6
AVSS to +4.6∗1
AVREF
AVSS to +4.6∗1
VDD
Supply voltage
AVSS
Remarks
V
V
Input voltage
VIN
–0.3 to +0.3
–0.3 to +4.6∗2
V
Output voltage
VOUT
–0.3 to +4.6∗2
V
High level output current
IOH
–5.0
mA
Output (value per pin)
High level total output current
ΣIOH
–50
mA
Total for all output pins
IOL
15.0
mA
All pins excluding large
current output pins
(value per pin)
IOLC
20.0
mA
Large current output pins∗3
(value per pin)
Low level total output current
ΣIOL
130
mA
Total for all output pins
Operating temperature
Topr
–30 to +85
°C
Storage temperature
Tstg
–55 to +150
°C
Allowable power dissipation
PD
V
Low level output current
600
380
QFP-100P-L01
mW
LQFP-100P-L01
∗1 AVDD and AVREF must be the same voltage with VDD.
∗2 VIN and VOUT excluding PH0 and PH1 must not exceed VDD + 0.3V.
∗3 The large current drive transistor is N-ch transistor of PD and PH0, PH1.
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
be conducted under the recommended operating conditions. Exceeding these conditions may adversely
affect the reliability of the LSI.
– 18 –
CXP974F096
Recommended Operating Conditions
Item
Symbol
Min.
Max.
2.7
3.6
2.0
3.6
AVDD
2.7
3.6
V
Guaranteed data hold range during stop mode
∗1
AVREF
2.7
3.6
V
∗1
VIH
0.7VDD
VDD
V
∗2
VIHS
0.8VDD
VDD
V
VDD
Supply voltage
High level input
voltage
VIHEX
Low level input
voltage
Operating
temperature
∗1
∗2
∗3
∗4
(Vss = 0V reference)
VDD – 0.4 VDD + 0.2
Unit
Remarks
V
V
VIL
0
0.2VDD
V
VILS
0
0.2VDD
V
VILEX
–0.3
0.4
V
Topr
–30
+85
°C
Tpwe
0
+50
°C
CMOS Schmitt input∗3
EXTAL∗4
CMOS Schmitt input∗3
EXTAL∗4
Recommended operating range of FLASH
EEPROM rewrite operation
AVDD and AVREF must be the same voltage with VDD.
PC, PD, PF4, PG6, PH3, PI2, PI4 to PI7, PJ, PK0 to PK2, PWE for normal input port.
RST, PE, PF0 to PF3, PF5, PG4, PG5, PG7, PH0 to PH2, PH4, PH5, PI0, PI1, PI3, PK3 and PK4.
Specified only during self-oscillation.
– 19 –
CXP974F096
Electrical Characteristics
DC Characteristics 1
Item
High level
output
voltage
Low level
output
voltage
Symbol
Pins
VOH
PD to PE, PF6,
PF7, PG0 to PG5,
PH2, PH4, PH5,
PI to PJ,
PK0 to PK6
PA to PC, PF4,
PF5, PG6, PG7,
PH3, PH6, PH7,
PI2, PI3
Conditions
Min.
VDD = 3.0V, IOH = –0.15mA
2.70
VDD = 2.7V, IOH = –0.15mA
2.40
VDD = 3.0V, IOH = –0.5mA
2.30
VDD = 2.7V, IOH = –0.5mA
2.00
VDD = 3.0V, IOH = –1.5mA
2.30
VDD = 2.7V, IOH = –1.5mA
2.00
VOL
IILE
IILR
Typ.
Max.
Unit
V
V
V
PE, PF6, PF7,
IOL = 1.2mA
PG0 to PG5,
PH2, PH4, PH5,
PI0, PI1, PI4 to PI7, IOL = 1.6mA
PJ, PK0 to PK6
IIHE
Input
current
(Topr = –30 to +85°C, Vss = 0V reference)
0.30
V
0.50
V
PA to PC, PF4,
PF5, PG6, PG7,
PH3, PH6, PH7,
PI2, PI3
IOL = 2.0mA
0.30
V
IOL = 3.0mA
0.50
V
PD, PH0, PH1
IOL = 5.0mA
1.00
V
EXTAL
RST∗1
VDD = 3.6V, VIH = 3.6V
0.3
61
µA
VDD = 3.6V, VIL = 0.3V
–0.3
–61
µA
VDD = 3.6V, VIL = 0.3V
–0.9
–250
µA
I/O leakage
IIZ
current
PA to PJ, PK0 to PK6,
VDD = 3.6V, VI = 0, 3.6V
RST∗1
±31
µA
Open drain
output
leakage
current
(N-ch Tr.
off-state)
PH0, PH1
31
µA
ILOH
VDD = 3.6V, VIH = 3.6V
∗1 RST specifies the input current when pull-up resistor has been selected; the leakage current when no
resistor has been selected.
– 20 –
CXP974F096
DC Characteristics 2
Item
(Topr = –30 to +85°C, Vss = 0V reference)
Symbol
∗2
IDD1
Supply
current∗1
∗2
IDDS2
IDDS3
Pins
Min.
Conditions
Typ.
Max.
Unit
VDD, VSS
VDD = 3.3 ± 0.3V,
fEX = fsrc = 40MHz, External clock operation
A/D off state, PLL off state
65
75
mA
VDD, VSS
VDD = 3.3 ± 0.3V,
fEX = fsrc = 40MHz, External clock operation
A/D off state, PLL off state,
sleep mode
26
30
mA
VDD, VSS
VDD = 3.6V, stop mode
85°C or less
500
75°C or less
350
50°C or less
100
µA
∗1 When all output pins are open.
∗2 When the upper two bits (PCK1, PCK0) of the clock control register (CLC: 0002FEh) are set to "00" and the
LSI is operated in high-speed mode (1/2 frequency dividing clock).
I/O Capacitance
Item
Input
capacitance
Output
capacitance
I/O
capacitance
Symbol
Pins
Conditions
Min.
Typ.
Max.
Unit
CIN
PF0 to PF3,
EXTAL, RST
Clock 1MHz,
0V for all pins excluding
measured pins
10
20
pF
COUT
PA to PB, PF6, PF7,
Clock 1MHz,
PG0 to PG3,
0V for all pins excluding
PH6, PH7, PK5, PK6,
measured pins
XTAL
10
20
pF
CI/O
PC to PE, PF4, PF5,
Clock 1MHz,
PG4 to PG7,
0V for all pins excluding
PH0 to PH5, PI to PJ,
measured pins
PK0 to PK4
10
20
pF
– 21 –
CXP974F096
AC Characteristics
(1) Clock timing
Item
(Topr = –30 to +85°C, VDD = 2.7 to 3.6 V, Vss = 0V reference)
Symbol
Pins
Conditions
VDD = 3.3 ± 0.3V
9.5
34.5
VDD = 3.0 ± 0.3V
9.5
31.0
Fig.1, Fig.2
–30 to +75°C
VDD = 3.3 ± 0.3V
9.5
35.5
VDD = 3.0 ± 0.3V
9.5
32.5
Fig.1, Fig.2
–30 to +50°C
VDD = 3.3 ± 0.3V
9.5
38.5
VDD = 3.0 ± 0.3V
9.5
35.0
Fig.1, Fig.2
Main clock base
oscillation frequency
fEX
EXTAL,
XTAL
tXH
tXL
Main clock base
oscillation input pulse
width
tXH
tXL
EXTAL,
XTAL
tXH
tXL
tXR
tXF
Main clock base
oscillation input
rise time, fall time
tXR
tXF
EXTAL,
XTAL
tXR
tXF
Main clock duty
duty
XTAL
Min. Typ. Max. Unit
MHz
MHz
MHz
fEX = 40.0MHz
Fig.1, Fig.2
External clock drive
4.0
ns
fEX = 33.86MHz
Fig.1, Fig.2
External clock drive
4.0
ns
fEX = 20.0MHz
Fig.1, Fig.2
External clock drive
11
ns
fEX = 40.0MHz
Fig.1, Fig.2
External clock drive
8.5
ns
fEX = 33.86MHz
Fig.1, Fig.2
External clock drive
10.5
ns
fEX = 20.0MHz
Fig.1, Fig.2
External clock drive
14
ns
60
%
Fig.1, Fig.2
1/2 VDD point
40
50
Note) tsys indicates the four values below according to the upper two bits (PCK1, PCK0) of the clock control
register (CLC: 0002FEh).
tsys [ns] = 2/fEX (PCK1, PCK0 = 00), 4/fEX (PCK1, PCK0 = 01), 8/fEX (PCK1, PCK0 = 10,
16/fEX (PCK1, PCK0 = 11)
– 22 –
CXP974F096
1/fEX
VDD – 0.4V
EXTAL
XTAL
0.4V
tXH
tXF
tXL
tXR
tEX
XTAL
1/2VDD
tX
duty = tx/tEX; tEX = 1/fEX
Fig. 1. Clock timing
Oscillator connection example
of main oscillation circuit
EXTAL
XTAL
(i)
Connection example (1)
of external clock
EXTAL
XTAL
(ii)
Connection example (2)
of external clock
EXTAL
XTAL
(iii)
Fig. 2. Oscillator connection and clock applied conditions
– 23 –
CXP974F096
(2) Event count input
(Topr = –30 to +85°C, VDD = 2.7 to 3.6V, Vss = 0V reference)
Item
Symbol
tEH,
tEL
Event count input clock
pulse width
Pins
Conditions
EC0,
EC2
Min.
Max.
tsys + 100
Fig. 3
Unit
ns
0.8VDD
EC0
EC2
0.2VDD
tEH
tEL
Fig. 3. Event count input timing
(3) Interruption and reset input
Item
External interruption
high, low level width
Reset input low level
width
(Topr = –30 to +85°C, VDD = 2.7 to 3.6V, Vss = 0V reference)
Symbol
tIH,
tIL
tRST
Pins
Conditions
NMI,
INT0 to INT7,
KS0 to KS19
Main mode
Sleep mode
Fig. 4
INT4 to INT7
Noise filter
selected
Fig. 4
Min.
φ
2tsys + 100
PS4
32/fEX + 100
PS6
128/fEX + 100
50/fEX
tIH
tIL
0.8VDD
NMI
INT0 to INT7
KS0 to KS19
0.2VDD
Fig. 4. Interruption input timing
tRST
RST
0.2VDD
Fig. 5. Reset input timing
– 24 –
Unit
tsys + 100
Fig. 5
RST
Max.
ns
ns
CXP974F096
(4) A/D converter characteristics
(Topr = –30 to +85°C, VDD = AVDD = AVREF = 2.7 to 3.6V, Vss = AVss = 0V reference)
Item
Symbol
Pins
Conditions
Min.
Typ.
Resolution
Linearity error
VDD = AVDD = AVREF = 3.0V
Absolute error
Conversion time
tCONV
Sampling time
tSAMP
∗1
∗1
VDD = AVDD = AVREF
Reference input voltage VREF
AVREF
Analog input voltage
AN0 to AN11
Main
mode
IREF
AVREF current
AVREF
8
Bits
±1
LSB
±3
LSB
34tsys
ns
62tsys
ns
10tsys
ns
20tsys
ns
2.7
3.6
V
0
AVREF
V
VDD = 3.3 ± 0.3V
fSRC = 40MHz
1.5
2.1
mA
VDD = 3.3 ± 0.3V
fSRC = 20MHz
1.2
1.7
mA
12
µA
ADC off state∗2
Stop mode
IREFS
Max. Unit
∗1 When Bit 6 (ADCK) of A/D control status register (ADCS: 000132h) is specified to "1".
∗2 When Bit 5 (ADPC) of A/D control status register (ADCS: 000132h) is specified to "1".
Note) AVDD and AVREF must be the same voltage with VDD.
(100h)
FFh
FEh
Digital conversion value
Digital conversion value
FFh
FEh
Linearity error
01h
00h
VZT∗1
Analog input
Absolute error
01h
00h
VFT∗2
Absolute error
Analog input
∗1 VZT: Value at which the digital conversion value changes from 00h to 01h and vice versa.
∗2 VFT: Value at which the digital conversion value changes from FEh to FFh and vice versa.
Fig. 6. Definition of A/D converter terms
– 25 –
AVREF
CXP974F096
(5) Serial transfer (CH0, CH1, CH2)
Item
(Topr = –30 to +85°C, VDD = 2.7 to 3.6V, Vss = 0V reference)
Symbol
Pins
CS ↓ → SCK
delay time
tDCSK
SCK0,
SCK1,
SCK2
CS ↑ → SCK
float delay time
tDSKF
CS ↓ → SO
delay time
tDCSO
CS ↑ → SO
float delay time
tDCSOF SCS1, External start
transfer mode
CS high level
width
tWHCS
SCK cycle time
SCK
high, low pulse
width
SI input data
setup time
(for SCK ↑)
SI input data
hold time
(for SCK ↑)
SCK ↓ → SO
delay time
Minimum interval
time
tKCY
tKH,
tKL
tSIK
tKSI
tKSO
tINT
Max.
Unit
VDD = 3.3 ± 0.3V
1.5tsys + 200
ns
VDD = 3.0 ± 0.3V
1.5tsys + 210
ns
VDD = 3.3 ± 0.3V
1.5tsys + 200
ns
VDD = 3.0 ± 0.3V
1.5tsys + 210
ns
SO0,
SO1,
SO2
VDD = 3.3 ± 0.3V
1.5tsys + 200
ns
VDD = 3.0 ± 0.3V
1.5tsys + 210
ns
SCS0,
VDD = 3.3 ± 0.3V
1.5tsys + 200
ns
SCS2
VDD = 3.0 ± 0.3V
1.5tsys + 210
ns
SCS0,
SCS1,
SCS2
VDD = 3.3 ± 0.3V
tsys + 100
ns
VDD = 3.0 ± 0.3V
tsys + 110
ns
VDD = 3.3 ± 0.3V
2tsys + 200
ns
VDD = 3.0 ± 0.3V
2tsys + 210
ns
VDD = 3.3 ± 0.3V
16/fEX
ns
VDD = 3.0 ± 0.3V
16/fEX
ns
VDD = 3.3 ± 0.3V
ns
VDD = 3.0 ± 0.3V
tsys + 100
tsys + 110
VDD = 3.3 ± 0.3V
8/fEX – 100
ns
VDD = 3.0 ± 0.3V
8/fEX – 110
ns
VDD = 3.3 ± 0.3V
100
ns
VDD = 3.0 ± 0.3V
110
ns
VDD = 3.3 ± 0.3V
200
ns
VDD = 3.0 ± 0.3V
210
ns
VDD = 3.3 ± 0.3V
2tsys + 100
ns
VDD = 3.0 ± 0.3V
2tsys + 110
ns
VDD = 3.3 ± 0.3V
100
ns
VDD = 3.0 ± 0.3V
110
ns
SCK0,
SCK1,
SCK2
SCK0,
SCK1,
SCK2
SCK0,
SCK1,
SCK2
SI0,
SI1,
SI2
SI0,
SI1,
SI2
SO0,
SO1,
SO2
SCK0,
SCK1,
SCK2
Conditions
External start
transfer mode
(SCK = output
mode)
Input mode
Output mode
Input mode
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
Min.
ns
VDD = 3.3 ± 0.3V
2tsys + 150
ns
VDD = 3.0 ± 0.3V
2tsys + 160
ns
VDD = 3.3 ± 0.3V
100
ns
VDD = 3.0 ± 0.3V
110
ns
VDD = 3.3 ± 0.3V
3tsys + 100
ns
VDD = 3.0 ± 0.3V
3tsys + 110
ns
VDD = 3.3 ± 0.3V
8/fEX – 100
ns
VDD = 3.0 ± 0.3V
8/fEX – 110
ns
Note) The load condition for the SCK output mode and SO output delay time is 100pF.
– 26 –
CXP974F096
tWHCS
0.8VDD
SCS0
SCS1
SCS2
0.2VDD
tKCY
tDCSK
tKL
tDCSKF
tKH
0.8VDD
SCK0
SCK1
SCK2
0.2VDD
tSIK
tKSI
0.8VDD
SI0
SI1
SI2
Input data
0.2VDD
tDCSO
tDCSOF
tKSO
0.8VDD
SO0
SO1
SO2
Output data
0.2VDD
tINT
0.8VDD
SCK0
SCK1
SCK2
Fig. 7. Serial transfer CH0, CH1, CH2 timing
– 27 –
CXP974F096
(6) I2C bus
(Topr = –30 to +85°C, VDD = 2.7 to 3.6V, Vss = 0V reference)
Item
Symbol
Pins
Standard mode
Min.
Max.
High-speed mode
Min.
Max.
Unit
SCK clock frequency
tSCL
SCL
Bus free time between stop
and start conditions
tBUF
SDA
4.7
1.3
µs
Hold time under (resend)
start condition
tHD;STA
SDA,
SCL
4.0
0.6
µs
Hold time in SCL clock low
state
tLow
SCL
4.7
1.3
µs
Hold time in SCL clock high
state
tHigh
SCL
4.0
0.6
µs
Setup time under (resend)
start condition
tSU;STA
SDA,
SCL
4.7
0.6
µs
Data hold time
tHD;DAT
SDA,
SCL
0
0
Data setup time
tSU;DAT
SDA,
SCL
250
100
SCL, SDA signal output
rise time
SCL, SDA signal output
fall time
tRd,
tRc
tFd,
tFc
Setup time under stop
condition
tSU;STO
100
400
0.9
kHz
µs
ns
SDA,
SCL
1000
20 + α∗1
300
ns
SDA,
SCL
300
20 + α∗1
300
ns
SDA,
SCL
4.0
0.6
µs
∗1 Due to the total capacitance of the bus.
tSU;DAT
tBUF
SDA
tHD;STA
tRd
tFd
tSCL
tRc
tFc
tLow
SCL
tHD;STA
tHD;DAT
tHigh
Fig. 8. I2C bus timing
– 28 –
tSU;STA
tSU;STO
CXP974F096
(7) Remote control reception
Item
Remote control receive
high, low level width
(Topr = –30 to +85°C, VDD = 2.7 to 3.6V, Vss = 0V reference)
Symbol
tRMC
Pins
RMC
Conditions
Main mode
Typ.
PS5 selected
128/fEX + 100
PS7 selected
512/fEX + 100
PS9 selected
2048/fEX + 100
0.8VDD
RMC
0.2VDD
tRMC
tRMC
Fig. 9. Remote control signal input timing
– 29 –
Max.
Unit
ns
CXP974F096
(8) External register interface
Item
(Vss = 0V reference)
3.3 ± 0.3V
3.3 ± 0.3V
3.0 ± 0.3V
Topr
=
–20
to
+75°C
Topr
=
–30
to
+85°C
Topr
= –30 to +85°C
Symbol
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Chip select
pulse width 1
tCS1
1.5tsys
–20
1.5tsys
1.5tsys
–20
1.5tsys
1.5tsys
–30
1.5tsys
ns
Chip select
pulse width 2
tCS2
2.5tsys
–20
16.5tsys
2.5tsys
–20
16.5tsys
2.5tsys
–30
16.5tsys
ns
Chip select
pulse width 3
tCS3
2.5tsys
–20
32.5tsys
2.5tsys
–20
32.5tsys
2.5tsys
–30
32.5tsys
ns
Chip select
pulse width 4
tCS4
3.5tsys
–20
33.5tsys
3.5tsys
–20
33.5tsys
3.5tsys
–30
33.5tsys
ns
Chip select
pulse width 5
tCS5
2.5tsys
–20
17.5tsys
2.5tsys
–20
17.5tsys
2.5tsys
–30
17.5tsys
ns
Chip select
pulse width 6
tCS6
3.5tsys
–20
18.5tsys
3.5tsys
–20
18.5tsys
3.5tsys
–30
18.5tsys
ns
Chip select
pulse width 7
tCS7
4.5tsys
–20
34.5tsys
4.5tsys
–20
34.5tsys
4.5tsys
–30
34.5tsys
ns
Read/write strobe
pulse width 1
tRW1
tsys – 25
tsys
tsys – 25
tsys
tsys – 35
tsys
ns
Read/write strobe
pulse width 2
tRW2
2tsys – 25
16tsys
2tsys – 25
16tsys
2tsys – 35
16tsys
ns
Read/write strobe
pulse width 3
tRW3
2tsys – 25
32tsys
2tsys – 25
32tsys
2tsys – 35
32tsys
ns
Address setting time 1
tAS1
tsys/2
tsys/2
tsys/2
tsys/2
tsys/2
tsys/2
ns
Address setting time 2
tAS2
1.5tsys
–25
1.5tsys
1.5tsys
–25
1.5tsys
1.5tsys
–35
1.5tsys
ns
Address hold time
tAH
tsys/2
—
ns
Read data setting
request time
tDS1
Read data hold
request time
–25
–25
—
tsys/2
15
—
tDH1
0
Write data
setting time 1
tDS2
Write data
setting time 2
Write data hold time
–35
—
tsys/2
15
—
20
—
ns
—
0
—
0
—
ns
1.5tsys
–25
1.5tsys
1.5tsys
–25
1.5tsys
1.5tsys
–35
1.5tsys
ns
tDS3
2.5tsys
–25
16.5tsys
2.5tsys
–25
16.5tsys
2.5tsys
–35
16.5tsys
ns
tDH2
tsys/2
tsys/2
tsys/2
tsys/2
tsys/2
tsys/2
–25
+30
–25
+30
–35
+30
–25
– 30 –
–25
–35
ns
CXP974F096
Read Timing
t1
t2
A15 to A0
tCS1
tAH
XCS3 to XCS0
tAS1
tRW1
XRD
tDS1
tDH1
D7 to D0
Fig. 10. Byte read (without programmable wait)
t1
t2 or tw
t3 or tW + 1
A15 to A0
tCS2
tAH
XCS3 to XCS0
tAS1
tRW2
XRD
tDS1
D7 to D0
Fig. 11. Byte read (with programmable wait)
– 31 –
tDH1
CXP974F096
t1
t2
t3
EVEN ADD.
A15 to A0
ODD ADD.
tCS3
tAH
XCS3 to XCS0
tAS1
tRW3
XRD
tDS1
tDS1
tDH1
D7 to D0
Fig. 12. Word read (no strobe mode, without programmable wait)
t1
t2
t3
EVEN ADD.
A15 to A0
t4
ODD ADD.
tCS4
tAH
XCS3 to XCS0
tAS1
tRW1
tAH
tAS1
tRW1
XRD
tDS1
tDH1
tDS1
D7 to D0
Fig. 13. Word read (strobe mode, without programmable wait)
– 32 –
tDH1
CXP974F096
Write Timing
t1
t2
t3
A15 to A0
tCS5
tAH
XCS3 to XCS0
tAS2
tRW1
XWR
tDS2
tDH2
D7 to D0
Fig. 14. Byte write (without programmable wait)
t1
t2
t3 or tw
t4 or tW + 1
A15 to A0
tCS6
tAH
XCS3 to XCS0
tAS2
tRW2
XWR
tDS3
D7 to D0
Fig. 15. Byte write (with programmable wait)
– 33 –
tDH2
CXP974F096
t1
A15 to A0
t2
t3
t4
EVEN ADD.
t5
ODD ADD.
tCS7
tAH
XCS3 to XCS0
tRW1
tAH
tAS1
tRW1
XWR
tDS2
tDH2
tDS2
D7 to D0
Fig. 16. Word write (without programmable wait)
– 34 –
tDH2
CXP974F096
Appendix
SPC970 Series recommended oscillation circuit and oscillator
(i) Main oscillation circuit
EXTAL
(ii) Main oscillation circuit
XTAL
EXTAL
XTAL
Rd
C1
(iii) Main oscillation circuit
EXTAL
XTAL
Rd
Rd
C2
C1
C1 C2
C2
C3
L
Circuit
example
Fig. 17. Recommended oscillation circuit
Manufacturer
MURATA MFG
CO., LTD.
fEX (MHz)
C1 (pF)
C2 (pF)
Rd (Ω)
CSA6.00MG040
6.0
100
100
0
CSA8.00MTZ
8.0
30
30
0
CSA10.0MTZ
10.0
30
30
0
CSA12.0MTZ
12.0
30
30
0
CSA16.00MXZ040
16.0
15
15
0
CSA20.00MXZ040
20.0
10
10
0
CSA24.00MXZ040
CST6.00MGW040∗
24.0
7
7
0
6.0
100
100
0
Model
Remarks
(i)
CST8.00MTW∗
CST10.0MTW∗
8.0
30
30
0
10.0
30
30
0
CST12.0MTW∗
12.0
30
30
0
CST16.00MXW0C3∗
16.0
15
15
0
6.0
18
18
560
8.0
15
15
330
10.0
10
10
330
CL = 9.5pF
12.0
10
10
220
CL = 10pF
RIVER ELETEC
HC-49/U03
CO., LTD.
∗ Indicates types with on-chip grounding capacitor (C1, C2).
– 35 –
(ii)
CL = 13.5pF
(i)
CL = 12pF
CL: Load capacitor
CXP974F096
Manufacturer
Model
HC-49/U-S
KINSEKI LTD.
HC-49/U
TDK
Corporation
fEX (MHz)
C1 (pF)
C2 (pF)
Rd (Ω)
6.0
15
15
5.6k
8.0
15
15
3.0k
10.0
10
10
1.8k
12.0
12
12
1.0k
16.0
12
12
470
20.0
12
12
390
24.0
12
12
200
28.0
1
1
100
32.0
3
0.01µF
0
36.0
3
0.01µF
0
40.0
1
0.01µF
0
CCR6.0MC5∗
6.0
36 (±20%) 36 (±20%)
0
CCR12.0MSC5∗
12.0
20 (±20%) 20 (±20%)
0
CCR16.0MSC6∗
16.0
10 (±20%) 10 (±20%)
0
CCR28.0MSC6∗
28.0
10 (±20%) 10 (±20%)
0
CCR40.0MS6
40.0
5
5
∗ Indicates types with on-chip grounding capacitor (C1, C2).
0
Product name
FLASH EEPROM incorporated version
CXP974F096Q-1, CXP974F096R-1
FLASH EEPROM capacitance
384K byte
RAM capacitance
23.5K byte
Package
100-pin plastic QFP,
100-pin plastic LQFP
Main clock base
oscillation frequency
40MHz
Reset pin pull-up
resistor
Existent
– 36 –
Remarks
CL = 16pF
(i)
CL = 12pF
C3 = 10pF,
L = 2.7µH
(iii)
C3 = 5pF,
L = 2.7µH
C3 = 3pF,
L = 3.3µH
(ii)
(i)
CCR∗∗∗: Surface mounted type ceramic
oscillator
CL:
Load capacitor
Product List
Type
Circuit
example
CXP974F096
Notes on PK6 Usage
FLASH EEPROM incorporated PK6 is also used as flash mode setting function. Note the followings:
1. "H" is output to PK6 during a reset. That is driven at comparatively high impedance (approximately 150kΩ),
and take care that VOH should not fall under 0.7VDD by the partial pressure with external circuit load
impedance.
2. When using software reset functions, PK6 may not rise enough during a reset. Switching PK6 to "H" output
prior to software reset execution or connecting pull-up resistor is recommended.
RST
Normal operation
PK6
Flash mode
Keep PK6 above 0.7VDD
during this period.
Mask ROM and piggy/evaluation chip do not have flash mode setting function. Considering that FLASH
EEPROM incorporated type is used, above countermeasure should be performed.
Limits on Usage of FLASH EEPROM incorporated Type
The main clock doubler circuit is not guaranteed to operate.
– 37 –
CXP974F096
Characteristics Curve
IDD vs. VDD
IDD vs. VDD
(fEX = 40MHz, Topr = 25°C, Typical)
72
72
66
66
60
60
1/2 frequency
54 dividing mode
54
IDD – Supply current [mA]
IDD – Supply current [mA]
(fEX = 40MHz, Topr = 25°C, Typical)
48
42
36 1/4 frequency
dividing mode
30 1/8 frequency
dividing mode
24 1/16 frequency
dividing mode
42
36
24
18
12
12
6
6
0
2.1
2.4
2.7
3
3.3
3.6
VDD – Supply voltage [V]
2.1
3.9
2.4
2.7
3
3.3
3.6
VDD – Supply voltage [V]
IDD vs. fEX
IDD vs. fEX
(VDD = 3V, Topr = 25°C, Typical)
(VDD = 3V, Topr = 25°C, Typical)
72
72
66
66
1/2 frequency
dividing mode
60
3.9
60
54
48
42
1/4 frequency
dividing mode
36
1/8 frequency
dividing mode
30
1/16 frequency
dividing mode
24
IDD – Supply current [mA]
54
48
42
36
24
18
12
12
6
6
0
10
20
30
40
fEX – Main clock base oscillation frequency [MHz]
Sleep mode
(1/2 frequency dividing mode)
Sleep mode
(1/4 frequency dividing mode)
Sleep mode
(1/8 frequency dividing mode)
Sleep mode
(1/16 frequency dividing mode)
30
18
0
Sleep mode
(1/2 frequency dividing mode)
Sleep mode
(1/4 frequency dividing mode)
Sleep mode
(1/8 frequency dividing mode)
Sleep mode
(1/16 frequency dividing mode)
30
18
0
IDD – Supply current [mA]
48
0
0
10
20
30
40
fEX – Main clock base oscillation frequency [MHz]
– 38 –
CXP974F096
Package Outline
Unit: mm
100PIN QFP (PLASTIC)
23.9 ± 0.4
+ 0.4
20.0 – 0.1
+ 0.1
0.15 – 0.05
80
51
+ 0.4
14.0 – 0.1
17.9 ± 0.4
15.8 ± 0.4
50
81
A
31
100
1
30
+ 0.15
0.3 – 0.1
0.65
0.13
+ 0.2
0.1 – 0.05
+ 0.35
2.75 – 0.15
M
0˚ to 10˚
DETAIL A
0.8 ± 0.2
(16.3)
0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-100P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
QFP100-P-1420
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
1.7g
JEDEC CODE
LEAD SPECIFICATIONS
ITEM
SPEC.
LEAD MATERIAL
ALLOY 42
LEAD TREATMENT
Sn-Pb 10%
LEAD TREATMENT THICKNESS
5-18µm
– 39 –
CXP974F096
Package Outline
Unit: mm
100PIN LQFP (PLASTIC)
16.0 ± 0.2
∗ 14.0 ± 0.1
75
51
76
50
(15.0)
B
26
100
1
0.5 ± 0.2
A
(0.22)
25
b
0.13 M
0.1 ± 0.1
+ 0.2
1.5 – 0.1
0.1
+ 0.05
0.127 – 0.02
0.5
+ 0.08
b = 0.18 – 0.03
0.5 ± 0.2
0˚ to 10˚
(0.127)
( 0.18 )
DETAIL B
NOTE: Dimension "∗" does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
LQFP-100P-L01
SONY CODE
P-LQFP100-14x14-0.5
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
LEAD MATERIAL
42 / COPPER ALLOY
PACKAGE MASS
0.7g
LEAD SPECIFICATIONS
ITEM
SPEC.
LEAD MATERIAL
ALLOY 42
LEAD TREATMENT
Sn-Pb 10%
LEAD TREATMENT THICKNESS
5-18µm
– 40 –
Sony Corporation