CXP86608/86612/86616 CMOS 8-bit Single Chip Microcomputer Description The CXP86608/86612/86616 are the CMOS 8-bit single chip microcomputer integrating on a single chip an A/D converter, serial interface, timer/counter, time-base timer, I2C bus interface, PWM output, remote control reception circuit, watchdog timer, 32kHz timer/counter besides the basic configurations of 8-bit CPU, ROM, RAM, I/O ports. The CXP86608/86612/86616 also provide a sleep function that enables to lower the power consumption. 64 pin SDIP (Plastic) 64 pin QFP (Plastic) Structure Silicon gate CMOS IC Features • A wide instruction set (213 instructions) which covers various types of data — 16-bit operation/multiplication and division/Boolean bit operation instructions • Minimum instruction cycle 250ns at 16MHz operation 122µs at 32kHz operation • Incorporated ROM 8K bytes (CXP86608) 12K bytes (CXP86612) 16K bytes (CXP86616) • Incorporated RAM 352 bytes • Peripheral functions — A/D converter 8 bits, 6 channels, successive approximation method (Conversion time of 3.25µs at 16MHz) — Serial interface 8-bit clock sync type, 1 channel — Timer 8-bit timer 8-bit timer/counter 19-bit time-base timer 32kHz timer/counter — I2C bus interface — PWM output 8 bits, 4 channels — Remote control reception circuit 8-bit pulse measurement counter, 6-stage FIFO — Watchdog timer • Interruption 11 factors, 11 vectors, multi-interruption possible • Standby mode Sleep • Package 64-pin plastic SDIP/QFP • Piggyback/evaluator CXP86400 64-pin ceramic PQFP CXP86490 64-pin ceramic PSDIP Perchase of Sony's I2C components conveys a licence under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E97750-PS SERIAL INTERFACE UNIT 8 BIT TIMER/ COUNTER 0 8 BIT TIMER 1 SI SO SCK EC TO FIFO 2 I2C BUS INTERFACE UNIT SDA0 REMOCON INTERRUPT CONTROLLER INT0 INT1 INT2 SDA1 RMC SCL0 A/D CONVERTER 6CH SCL1 6 2 ADJ AN0 to AN5 RAM 352 BYTES ROM 8K/12K/16K BYTES 4 8 BIT PWM 32kHz TIMER/COUNTER WATCHDOG TIMER PRESCALER/ TIME BASE TIMER CLOCK GENERATOR /SYSTEM CONTROL TEX TX EXTAL XTAL RST VDD VSS SPC700 CPU CORE PWM0 to PWM3 PORT A PORT B PORT C PORT D PORT E PORT F –2– PORT G Block Diagram PC0 to PC5 PC6 to PC7 6 2 PE4 to PE6 PF0 to PF3 PF4 to PF7 3 4 4 PG3 to PG7 PE2 to PE3 2 5 PE0 to PE1 2 PD0 to PD7 PB0 to PB7 8 8 PA0 to PA7 8 CXP86608/86612/86616 CXP86608/86612/86616 Pin Assignment (Top View) 64-pin SDIP PC3 1 64 PC4 PC2 2 63 PC5 PC1 3 62 PC6 PC0 4 61 PC7 PD7/EC 5 60 PF0/PWM0 PD6/RMC 6 59 PF1/PWM1 PD5 7 58 PF2/PWM2 PF3/PWM3 PD4 8 57 PD3/SI 9 56 PF4/SCL0 PD2/SO 10 55 PF5/SCL1 PD1/SCK 11 54 PF6/SDA0 PD0/INT2 12 53 PF7/SDA1 PA7 13 52 PE0/TO/ADJ PA6 14 51 PE1 RST 15 50 PE2/TEX/INT0 VSS 16 49 PE3/TX XTAL 17 48 VSS EXTAL 18 47 VDD PA5/AN5 19 46 NC PA4/AN4 20 45 NC PA3/AN3 21 44 NC PA2/AN2 22 43 PE4 PA1/AN1 23 42 PE5 PA0/AN0 24 41 PE6 PB7 25 40 NC PB6 26 39 NC PB5 27 38 NC PB4 28 37 PB0 PB3 29 36 PB1 PG7/INT1 30 35 PB2 PG6 31 34 PG3 PG5 32 33 PG4 Note) 1. NC (Pins 38, 39, 40, 44 and 46) are left open. 2. Vss (Pins 16 and 48) are both connected to GND. 3. Pin 45 is the NC pin. However, connect it to VDD because it is the EXLC pin (input) for the piggyback/evaluator and OTP devices. –3– CXP86608/86612/86616 PF2/PWM2 PF1/PWM1 PF0/PWM0 PC7 PC6 PC5 PC4 PC3 PC1 PC2 PC0 PD7/EC PD6/RMC Pin Assignment (Top View) 64-pin QFP 64 63 62 61 60 59 58 57 56 55 54 53 52 PD5 1 51 PF3/PWM3 PD4 2 50 PF4/SCL0 PD3/SI 3 49 PF5/SCL1 PD2/SO 4 48 PF6/SDA0 PD1/SCK 5 47 PF7/SDA1 PD0/INT2 6 46 PE0/TO/ADJ PA7 7 45 PE1 PA6 8 44 PE2/TEX/INT0 RST 9 43 PE3/TX VSS 10 42 VSS XTAL 11 41 VDD EXTAL 12 40 NC PA5/AN5 13 39 NC PA4/AN4 14 38 NC PA3/AN3 15 37 PE4 PA2/AN2 16 36 PE5 PA1/AN1 17 35 PE6 PA0/AN0 18 34 NC PB7 19 33 NC NC PB0 PB1 PB2 PG3 PG4 PG5 PG6 PB3 PG7/INT1 PB4 PB5 PB6 20 21 22 23 24 25 26 27 28 29 30 31 32 Note) 1. NC (Pins 32, 33, 34, 38 and 40) are left open. 2. Vss (Pins 10 and 42) are both connected to GND. 3. Pin 39 is the NC pin. However, connect it to VDD because it is the EXLC pin (input) for the piggyback/evaluator and OTP devices. –4– CXP86608/86612/86616 Pin Description Symbol I/O PA0/AN0 to PA5/AN5 I/O/ Analog input PA6 to PA7 I/O PB0 to PB7 I/O Description (Port A) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) Analog inputs to A/D converter. (6 pins) (Port B) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) (Port C) Lower 6 bits are I/O ports; I/O can be set in a unit of single bits. Upper 2bits are output port and large current (12mA) N-channel open drain output. Upper 2 bits are medium voltage drive (12V), lower 6 bits are 5V drive. (8 pins) PC0 to PC5 I/O PC6 to PC7 Output PD0/INT2 I/O/Input PD1/SCK I/O/I/O PD2/SO I/O/Output PD3/SI I/O/Input PD4 to PD5 I/O PD6/RMC I/O/Input PD7/EC I/O/Input External event input for timer/counter. PE0/TO/ADJ I/O/Output/ Output Rectangular wave output for 8-bit timer/counter. PE1 I/O PE2/TEX/INT0 Input/Input/ Input PE3/TX Input/Output PE4 to PE6 Output External interruption request input. Active at the falling edge. (Port D) 8-bit I/O port. I/O can be set in a unit of single bits. Can drive 12mA sink current. (8 pins) (Port E) Bits 0 and 1 are I/O port; I/O can be set in a unit of single. Bits 2 and 3 are input port. Bits 4, 5 and 6 are output port. (7 pins) –5– Serial clock I/O. Serial data output. Serial data input. Remote control reception circuit input. 32kHz oscillation frequency dividing output. Connects a crystal for External interruption 32kHz timer/counter request input. Active at clock oscillation. When the falling edge used as an event counter, input to TEX pin and leave TX pin open. CXP86608/86612/86616 Symbol I/O Description (Port F) 8-bit output port and large current (12mA) N-channel open drain output. Lower 4 bits are medium voltage drive (12V); upper 4 bits are 5V drive. (8 pins) 8-bit PWM output. (4 pins) PF0/PWM0 to PF3/PWM3 Output/Output PF4/SCL0 to PF5/SCL1 Output/I/O PF6/SDA0 to PF7/SDA1 Output/I/O PG3 to PG6 I/O PG7/INT1 I/O/Input EXTAL Input XTAL Output Connects a crystal for system clock oscillation. When a clock is supplied externally, input to EXTAL pin and input a reversed phase clock to XTAL pin. RST Input System reset; active at Low level. I2C bus interface transfer clock I/O. (2 pins) I2C bus interface transfer data I/O. (2 pins) (Port G) 5-bit I/O port. I/O can be set in a unit of single bits. (5 pins) External interruption request input. Active at the falling edge. NC No connected. Connect this pin to VDD under normal operation. VDD Positive power supply. Vss GND. Connect two Vss pins to GND. –6– CXP86608/86612/86616 Input/Output Circuit Formats for Pins Pin Circuit format After reset Port A Port A data Port A direction PA0/AN0 to PA5/AN5 "0" after reset Hi-Z IP Data bus Input protection circuit RD (Port A) Port A function selection "0" after reset A/D converter Input multiplexer 6 pins Port A Port A data PA6 PA7 Port A direction "0" after reset Hi-Z Schmitt input Data bus IP RD (Port A) 2 pins Port B Ports B, C, G data Port C PB0 to PB7 PC0 to PC5 PG3 to PG6 PG7/INT1 Port G Ports B, C, G direction "0" after reset Schmitt input only for PG7 Data bus Hi-Z IP RD (Ports B, C, G) 19 pins INT1 Port C PC6 PC7 ∗ Port C data Hi-Z Data bus 2 pins RD (Port C) –7– ∗ 12V drive Large current 12mA CXP86608/86612/86616 Pin Circuit format After reset Port D Port D data Port D direction PD0/INT2 PD3/SI PD6/RMC PD7/EC ∗ "0" after reset Hi-Z Schmitt input Data bus IP RD (Port D) ∗ Large current 12mA INT2, SI, RMC, EC 4 pins Port D SCK, SO SIO output enable Port D data PD1/SCK PD2/SO ∗ Port D direction Hi-Z "0" after reset IP Schmitt input only for PD1 Data bus RD (Port D) 2 pins ∗ Large current 12mA SCK only Port D Port D data Port D direction PD4 PD5 ∗ "0" after reset Hi-Z Schmitt input Data bus IP RD (Port D) ∗ Large current 12mA 2 pins –8– CXP86608/86612/86616 Pin Circuit format After reset Port E Internal reset signal Port E data 00 "1" after reset TO ∗1 ADJ16K ∗ ADJ2K 1 PE0/TO/ADJ 01 10 11 MPX ∗2 Port E function selection (upper) Port E function selection (lower) ∗1 ADJ signals are frequency dividing outputs for 32kHz oscillation frequency IP adjustment. ADJ2K provides usage as buzzer output. ∗2 Pull-up transistor approx. 150kΩ "00" after reset Port E direction "1" after reset Data bus 1 pin High level (with the resistor of pull-up transistor ON when reset) RD (Port E) Port E Port E data "1" after reset PE1 Port E direction High level "1" after reset IP Data bus RD (Port E) 1 pin Port E 32kHz oscillation circuit control "1" after reset Schmitt input INT0 Data bus RD (Port E) PE2/TEX/INT0 PE3/TX Data bus PE2/ TEX/ INT0 2 pins RD (Port E) Schmitt input IP IP PE3/ TX –9– Clock input Oscillation stop Port input CXP86608/86612/86616 Pin Circuit format After reset Port E PE4 PE5 PE6 Port E data Hi-Z Output becomes active from high impedance by data writing to port register. Data bus 3 pins RD (Port E) Port F PWM0 to PWM3 Port F function selection PF0/PWM0 to PF3/PWM3 ∗ "0" after reset Hi-Z Port F data "1" after reset ∗ 12V drive Large current 12mA Data bus RD (Port F) 4 pins Port F SCL, SDA I2C output enable PF4/SCL0 PF5/SCL1 PF6/SDA0 PF7/SDA1 ∗ Port F data "1" after reset Hi-Z Schmitt input SCL, SDA (I2C circuit) IP BUS SW 4 pins ∗ Large current 12mA – 10 – To internal I2C pins (SCL1 for SCL0) CXP86608/86612/86616 Pin EXTAL XTAL Circuit format EXTAL After reset IP • Diagram shows the circuit composition during oscillation. • Feedback resistor is removed during stop. (This device does not enter the stop mode.) XTAL 2 pins Oscillation Pull-up resistor RST AA AA Mask option OP 1 pin Schmitt input – 11 – Low level (when reset) CXP86608/86612/86616 Absolute Maximum Ratings Item (Vss = 0V reference) Symbol Ratings Unit V Remarks Supply voltage VDD Input voltage VIN –0.3 to +7.0 –0.3 to +7.0∗1 Output voltage VOUT –0.3 to +7.0∗1 V Medium drive output voltage VOUTP –0.3 to +15.0 V High level output current IOH –5 mA High level total output current ∑IOH –50 mA Total of all output pins IOL 15 mA IOLC 20 mA Ports excluding large current output (value per pin) Large current output ports (value per pin∗2) Low level total output current ∑IOL 130 mA Total of all output pins Operating temperature Topr –20 to +75 °C Storage temperature Tstg –55 to +150 °C Allowable power dissipation PD 1000 mW SDIP-64P-01 600 mW QFP-64P-L01 Low level output current V ∗1 VIN and VOUT should not exceed VDD + 0.3V. ∗2 The large current output port is Port C (PC6, PC7), Port D (PD) and Port F (PF). Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI. Recommended Operating Conditions Item Supply voltage High level input voltage Symbol (Vss = 0V reference) Min. Max. Unit 4.5 5.5 V Guaranteed operation range for 1/2 and 1/4 frequency dividing clocks 3.5 5.5 V Guaranteed operation range for 1/16 frequency dividing clock or sleep mode 2.7 5.5 V — — V Guaranteed operation range for TEX Guaranteed data hold range for stop∗1 VIH 0.7VDD VDD V ∗2 VIHS 0.8VDD VDD V ∗3 VDD – 0.4 VDD+0.3 V VDD Remarks VIL 0 0.3VDD V EXTAL pin∗4, TEX pin∗5 ∗2 VILS 0 0.2VDD V ∗3 VILEX –0.3 0.4 V EXTAL pin∗4, TEX pin∗5 Operating temperature Topr –20 +75 °C VIHEX Low level input voltage ∗1 ∗2 ∗3 ∗4 ∗5 This device does not enter the stop mode. PA0 to PA5, PB0 to PB7, PC0 to PC5, PD2, PE0, PE1, PE3, PG3 to PG6, SCL0, SCL1, SDA0, SDA1 pins PA6, PA7, INT2, SCK, SI, PD4, PD5, RMC, EC, INT0, INT1, RST pins Specifies only during external clock input. Specifies only during external event count input. – 12 – CXP86608/86612/86616 Electrical Characteristics (Ta = –20 to +75°C, Vss = 0V reference) DC characteristics Item High level output voltage Low level output voltage Symbol VOH VOL Pins Conditions Min. PA, PB, PC0 to PC5, PD, PE0 to PE1, PE4 to PE6, PG VDD = 4.5V, IOH = –0.5mA 4.0 V VDD = 4.5V, IOH = –1.2mA 3.5 V Input current IIHT IILT I/O leakage current V 0.6 V PC6, PC7, PD, PF VDD = 4.5V, IOL = 12.0mA 1.5 V PF4 to PF7 (SCL0, SCL1, SDA0, SDA1) VDD = 4.5V, IOL = 3.0mA 0.4 V VDD = 4.5V, IOL = 4.0mA 0.6 V EXTAL TEX VDD = 5.5V, VIH = 5.5V 0.5 40 µA VDD = 5.5V, VIL = 0.4V –0.5 –40 µA VDD = 5.5V, VIH = 5.5V 0.1 10 µA –0.1 –10 µA –1.5 –400 µA ±10 µA 50 µA IILR RST∗1 IIZ PA to PE, PG, RST∗1 VDD = 5.5V, VI = 0, 5.5V I2C bus switch connection impedance RBS (in output Tr off state) Unit 0.4 VDD = 5.5V, VIL = 0.4V Open drain I/O ILOH leakage current (in N-ch Tr off state) Max. PA to PD, PE0 to PE1, VDD = 4.5V, IOL = 1.8mA PE4 to PE6, PF0 to PF3, VDD = 4.5V, IOL = 3.6mA PG IIHE IILE Typ. PC6, PC7, PF0 to PF3 VDD = 5.5V, VOH = 12.0V PF4 to PF7 VDD = 5.5V, VOH = 5.5V 10 µA SCL0: SCL1 SDA0: SDA1 VDD = 4.5V VSCL0 = VSCL1 = 2.25V VSDA0 = VSDA1 = 2.25V 120 Ω 18 28 mA 30 80 µA 1.2 2.1 mA 12 35 µA — — µA 1/2 frequency dividing clock operation IDD1 VDD = 5.5V, 16MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3.3V, 32MHz crystal oscillation (C1 = C2 = 47pF) IDD2 Supply current∗2 Sleep mode IDDS1 IDDS2 IDDS3 VDD VDD = 5.5V, 16MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3.3V, 32MHz crystal oscillation (C1 = C2 = 47pF) Stop mode∗3 VDD = 5.5V, termination of 16MHz and 32MHz oscillation – 13 – — CXP86608/86612/86616 Item Input capacitance Symbol CIN Pins Conditions PA to PD, PE0 to PE3, Clock 1MHz PF4 to PF7, PG3 to PG7, 0V for no measured pins EXTAL, TEX, RST Min. Typ. Max. Unit 10 20 pF ∗1 For RST pin, specifies the input current when pull-up resistor is selected, and specifies the leakage current when non-resistor is selected. ∗2 When all output pins are left open. ∗3 This device does not enter the stop mode. – 14 – CXP86608/86612/86616 AC Characteristics (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) (1) Clock timing Item Symbol System clock frequency fC tXL, tXH System clock input rise and fall tCR, times tCF Event count input clock pulse tEH, width tEL Event count input clock rise and tER, fall times tEF System clock input pulse width System clock frequency fC tTL, tTH Event count input clock rise and tTR, fall times tTF Event count input clock input pulse width Pins Conditions Min. XTAL EXTAL Fig. 1, Fig. 2 8 EXTAL Fig. 1, Fig. 2 External clock drive 28 EXTAL Fig. 1, Fig. 2 External clock drive EC Fig. 3 EC Fig. 3 TEX TX VDD = 2.7 to 5.5V Fig. 2 (32kHz clock applied conditions) TEX Fig. 3 TEX Fig. 3 Typ. Max. Unit 16 MHz ns 200 4tsys∗1 ns ns 20 ms kHz 32.768 µs 10 20 ms ∗1 Indicates three values according to the contents of the clock control register (CLC: 00FEh) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") 1/fc VDD – 0.4V EXTAL 0.4V tCF tXH tXL tCR Fig. 1. Clock timing AAAAAAAAAAAAA AAAAAAAAAAAAA Crystal oscillation Ceramic oscillation EXTAL C1 External clock EXTAL XTAL C2 32kHz clock applied condition Crystal oscillation TEX XTAL 74HC04 TX C1 C2 Fig.2. Clock applied conditions 0.8VDD TEX EC 0.2VDD tEH tTH tEF tTF tEL tTL Fig. 3. Event count clock timing – 15 – tER tTR CXP86608/86612/86616 (2) Serial transfer Item (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol Pins tKCY SCK SCK High and Low level width tKH tKL SCK SI input setup time (for SCK ↑) tSIK SI SI hold time (for SCK ↑) tKSI SI SCK ↓ → SO delay time tKSO SO SCK cycle time Conditions Min. Input mode Max. 1000 ns 8000/fc ns 400 ns 4000/fc – 50 ns SCK input mode 100 ns SCK output mode 200 ns SCK input mode 200 ns SCK output mode 100 ns Output mode SCK input mode SCK output mode SCK input mode 200 ns SCK output mode 100 ns Note) The load of SCK output mode and SO output delay time is 50pF + 1TTL. tKCY tKL tKH 0.8VDD SCK 0.2VDD tSIK tKSI 0.8VDD Input data SI Unit 0.2VDD tKSO 0.8VDD SO Output data 0.2VDD Fig. 4. Serial transfer timing – 16 – CXP86608/86612/86616 (3) A/D converter characteristics Item Symbol (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Max. Unit Resolution 8 Bits Linearity error ±3 LSB Zero transition voltage VZT∗1 Full-scale transition voltage VFT∗2 Conversion time tCONV tSAMP Sampling time Analog input voltage VIAN Pins Conditions Ta = 25°C VDD = 5.0V Vss = 0V Min. Typ. –10 10 70 mV 4910 4970 5030 mV 26/fADC∗3 6/fADC∗3 AN0 to AN5 FFh FEh 0 µs VDD V Digital conversion value ∗1 VZT: Value at which the digital conversion value changes from 00h to 01h and vice versa. ∗2 VFT: Value at which the digital conversion value changes from FEh to FFh and vice versa. ∗3 fADC indicates the below values due to the contents of bit 6 (CKS) of the A/D control register (ADC: 00F6h): Linearity error fADC = fc (CKS = "0"), fc/2 (CKS = "1") 01h 00h µs VZT VFT Analog input Fig. 5. Definitions of A/D converter terms – 17 – CXP86608/86612/86616 (4) Interruption, reset input Item (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol Pins Conditions Min. Max. Unit External interruption High, Low level width tIH tIL INT0 INT1 INT2 1 µs Reset input Low level width tRSL RST 32/fc µs tIH tIL INT0 INT1 INT2 (falling edge) 0.8VDD 0.2VDD Fig. 6. Interruption input timing tRSL RST 0.2VDD Fig. 7. RST input timing – 18 – CXP86608/86612/86616 (5) I2C bus timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item Symbol Pins Conditions Min. Max. Unit 0 100 kHz SCL clock frequency fSLC SCL Bus-free time before starting transfer tBUF tHD; STA tLOW tHIGH tSU; STA tHD; DAT tSU; DAT tR tF tSU; STO SDA, SCL 4.7 µs SDA, SCL 4.0 µs SCL 4.7 µs SCL 4.0 µs SDA, SCL µs SDA, SCL 4.7 0∗1 SDA, SCL 250 ns Hold time for starting transfer Clock Low level width Clock High level width Setup time for repeated transfers Data hold time Data setup time SDA, SCL rise time SDA, SCL fall time Setup time for transfer completion µs SDA, SCL 1 µs SDA, SCL 300 ns SDA, SCL 4.7 µs ∗1 The data hold time should be 300ns or more because the SCL rise time (300ns Max.) is not included in it. SDA tBUF tR tF tHD; STA SCL tHD; STA tSU; STA P S tLOW tHD; DAT tHIGH St tSU; DAT tSU; STO P Fig. 8. I2C bus transfer timing I2C device RS I2C device RS RS R S RP RP SDA0 (or SDA1) SCL0 (or SCL1) Fig. 9. I2C device recommended circuit • A pull-up resistor (Rp) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1). • The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance (Rs = 300Ω or less) can be used to reduce the spike noise caused by CRT flashover. – 19 – CXP86608/86612/86616 Appendix AAAA AAAA AAAA AAAA AAAAA AAAA AAAAA AAAA AAAAA AAA A (i) Main clock EXTAL (ii) Main clock EXTAL XTAL Rd C1 (iii) Sub clock TEX XTAL TX Rd C2 Rd C2 C1 C1 C2 Fig. 10. Recommended oscillation circuit Manufacture Model MURATA MFG CO., LTD. fc (MHz) CSA10.0MTZ 10.0 CSA12.0MTZ 12.0 CSA16.00MXZ040 CST10.0MTW∗ 16.0 10.0 C1 (pF) C2 (pF) 30 30 5 5 30 30 CST12.0MTW∗ 12.0 CST16.00MXW0C1∗ 16.0 5 5 8.0 18 18 12.0 12 12 16.0 10 10 8.0 10 10 12.0 5 5 16.0 Open Open 32.768kHz 30 33 RIVER ELETEC HC-49/U03 CORPORATION HC-49/U (-S) KINSEKI LTD. P3 Rd (Ω) Circuit example (i) 0 ∗1 (ii) 330 ∗1 (i) 0 ∗1 120k (iii) ∗Models with an asterisk have the built-in ground capacitance (C1, C2). ∗1 The series resistor for XTAL (Rd = 500Ω or less) can reduce the effect of the noise caused by the electrostatic discharge. Mask Option Table Item Reset pin pull-up resistor Content Non-existent – 20 – Existent CXP86608/86612/86616 IDD vs. VDD IDD vs. fc (fc = 16MHz, Ta = 25°C, Typical) (VDD = 5V, Ta = 25°C, Typical) 100 1/2 dividing mode 1/4 dividing mode 15 1/16 dividing mode Sleep mode 1 0.1 32kHz operation mode IDD – Supply current [mA] IDD – Supply current [mA] 10 1/2 dividing mode 10 1/4 dividing mode 5 32kHz sleep mode 1/16 dividing mode 0.01 Sleep mode 1 2 3 4 5 6 7 0 0 VDD – Supply voltage [V] 5 10 fc – System clock [MHz] Fig. 11. Characteristic curves – 21 – 15 CXP86608/86612/86616 Unit: mm + 0.1 0.05 0.25 – 64PIN SDIP (PLASTIC) + 0.4 57.6 – 0.1 64 19.05 + 0.3 17.1 – 0.1 33 1 0° to 15° 32 3.0 MIN 0.5 MIN + 0.4 4.75 – 0.1 1.778 0.5 ± 0.1 0.9 ± 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE SDIP-64P-01 LEAD TREATMENT SOLDER PLATING EIAJ CODE SDIP064-P-0750 LEAD MATERIAL 42 ALLOY PACKAGE MASS 8.6g JEDEC CODE 64PIN QFP(PLASTIC) 23.9 ± 0.4 + 0.4 20.0 – 0.1 + 0.1 0.15 – 0.05 0.15 32 64 20 1 16.3 52 17.9 ± 0.4 33 + 0.2 0.1 – 0.05 19 + 0.35 2.75 – 0.15 + 0.15 0.4 – 0.1 1.0 0.2 M 0° to10° 0.8 ± 0.2 51 + 0.4 14.0 – 0.1 Package Outline PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER/PALLADIUM PLATING SONY CODE QFP-64P-L01 LEAD TREATMENT EIAJ CODE QFP064-P-1420 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 1.5g JEDEC CODE – 22 –