CXR704060
CMOS 32-bit Single Chip Microcomputer
Description
The CXR704060 is a CMOS 32-bit microcomputer
integrating on a single chip a micro processor unit
having a 32-bit RISC CPU as its core, and a signal
processing block having an accelerator circuit suited
for arithmetic signal processing. Adoption of this
arithmetic signal processing accelerator circuit
enables flexible support of various signal processing
systems.
The microcomputer block incorporates Memory Stick
interface, a MagicGate, FLASH memory interface,
USB interface, D/A converter for audio applications,
A/D converter, serial interface, I2C bus interface,
timer and PWM pulse generator as well as basic
configurations like a 32-bit RISC CPU, ROM, RAM,
and I/O ports. It also provides the idle/sleep/stop
functions that enable lower power consumption.
Features
• CPU
• Minimum instruction cycle
• Incorporated ROM
• Incorporated RAM
• Peripheral hardware
— Bus interface unit
— DMA controller
— A/D converter
— Serial interface
208 pin TFLGA (Plastic)
SR11 series 32-bit RISC CPU core (ARM7TDMI)
44.29ns (fSRC: 22.5792MHz)
192K bytes
256K bytes
16-bit data bus, 24-bit address bus, 5 chip select outputs
4 channels
10-bit 8-analog input, successive approximation method
Clock synchronization, 1 channel (Incorporated 128-byte buffer RAM)
Clock synchronization, 1 channel (Incorporated 32-byte buffer RAM)
Asynchronization, 2 channels
8 channels (timer output)
— 8-bit timer
— Time-base timer
— Prescaler
— Watchdog timer
16 bits × 1 channel
— PWM pulse generator
8 bits × 1 channel
— 16-bit D/A converter for audio applications
L channel, R channel
— Memory Stick interface
1 channel
— MagicGate
— Serial interface for EEPROM Serial interface for CXK2000, 1 channel
— USB interface
Conforms to USB1.1, internal transceiver
— Flash memory interface
1-bit error correction function
— External interruption
10 channels (polarity selection and both edge detection possible)
• Accelerator for arithmetic signal processing
• Standby mode
Idle/sleep/stop
• Package
208-pin plastic TFLGA
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E02655-PS
16
8-BIT TIMER (CH7)
PWM PULSE GENERATOR
BUS INTERFACE UNIT
EXTERNAL BUS
8
2
8
8
8
8
8
PORT K
8-BIT TIMER (CH6)
8
PORT R PORT Q PORT P PORT O PORT N PORT M PORT L
5
PORT J
8
PORT I
ROM
192K BYTES
RAM
256K BYTES
PRESCALLER/
TIME BASE TIMER
WATCHDOG TIMER
PORT G PORT F
4
1
4
8
8
4
8
PORT E PORT D PORT C PORT B
ARM7TDMI
CPU CORE
3
PORT A
VIRTUAL MOBILE ENGINE
CLOCK GENERATOR/
SYSTEM CONTROLLER
7
CXR704060
A0 to A23
5
D0 to D15
8
CS0, CS1,
CS5 to CS7
2
RE
2
WAIT
8-BIT TIMER (CH5)
DMAC (CH0)
8-BIT TIMER (CH4)
DMAC (CH2)
8-BIT TIMER (CH3)
DMAC (CH1)
8-BIT TIMER/COUNTER (CH2)
WE
8
DMAC (CH3)
8-BIT TIMER (CH1)
LWR/LB
8-BIT TIMER/COUNTER (CH0)
UWR/UB
RAM
VDIODF
I2C BUS INTERFACE
FAD0 to FAD7
VREFR
VREFL
A/D CONVERTER
FCE0 to FCE1
AVDDA
AVSDA
2
FLASH MEMORY
INTERFACE
PWM
UART (CH1)
FRB0 to FRB1
BEEP
2
FALE
FCLE
–2–
T3
UART (CH0)
FWP
FRE
FWE
RAM
MEMORY STICK
INTERFACE
SERIAL INTERFACE
(CH1)
MSINS
MSDIO
MSSCLK
MSBS
VDIOMS
SCS1
SI1
SO1
SCK1
INTERRUPT CONTROLLER
RAM
MAGIC GATE CORE
SERIAL INTERFACE
(CH0)
EEPROM SERIAL
INTERFACE
SCS0
SI0
SO0
SCK0
KRB
KCS
KCLK
KDO
KDI
T1
EC2
USB INTERFACE
TxD0
RxD0
TRON
TX
TEX
UDM
UDP
VBUS
AVSPLL
AVDPLL
VDIOUS
AVDUO
TxD1
RxD1
SDA
SCL
EC0
8
D/A CONVERTER
AN0 to AN7
AOUTR
AOUTL
MUTFGR
MUTFGL
FS256
ADDT
DADT
XBCK
LRCK
TDI
TMS
TCK
TDO
TRST
AVDMO
AVSOSC
RST
EXTAL
XTAL
DACK1
DREQ1
DACK0
DREQ0
INT3 to INT9
MSINS
VBUS
(USB SUSPEND)
AVDAD
AVSAD
Block Diagram
24
CXR704060
Pin Assignment (Top View) 208-pin TFLGA package
18
V
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
101
93
89
87
85
83
81
77
75
71
70
67
64
63
61
55
91
97
99
92
88
79
80
73
69
65
58
56
57
59
51
U
53
52
47
T
1
V
U
100
105
103
T
112
107
106
R
113
110
104
102
98
95
94
86
82
76
72
66
60
54
49
45
R
P
118
116
108
100
111
96
90
84
78
74
68
62
50
44
46
41
P
N
120
121
114
115
48
40
43
39
N
M
123
122
117
119
42
35
38
37
M
L
128
126
124
125
36
30
34
33
L
K
129
131
127
130
32
27
31
29
K
J
134
133
132
136
26
21
28
24
J
H
135
139
137
138
18
16
25
23
H
G
140
141
143
145
14
10
22
20
G
F
142
144
149
155
8
6
17
19
F
E
146
147
154
165
173
177
180
187
191
193
195
199
1
4
13
15
E
D
148
151
157
164
171
175
179
185
189
194
197
205
203
207
12
11
D
C
150
153
156
3
7
9
C
B
152
158
159
163
166
169
174
178
183
182
184
192
196
200
202
208
2
5
B
160
161
162
167
168
170
172
176
181
186
188
190
198
201
204
206
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
A
18
–3–
A
1
CXR704060
• Pin Assignment Table
Pin
No.
Pin
position
Pin function
Pin
No.
Pin
position
Pin function
Pin
No.
Pin
position
Pin function
1
E5
VDIO0
37
M1
VDIO1
73
U8
PE4/SCK1
2
B2
PM4/A12
38
M2
PO0/D0
74
P8
PE5/SO1
3
C3
PM5/A13
39
N1
PO1/D1
75
V9
PE6/SI1
4
E4
PM6/A14
40
N4
PO2/D2
76
R8
PE7/SCS1
5
B1
PM7/A15
41
P1
PO3/D3
77
V10
TEST5
6
F4
PN0/A16
42
M5
PO4/D4
78
P9
DVDD1
7
C2
PN1/A17
43
N2
PO5/D5
79
U10
DVSS3
8
F5
PN2/A18
44
P4
PO6/D6
80
U9
VDIO3
9
C1
PN3/A19
45
R1
PO7/D7
81
V11
PF0/EC0/INT3
10
G4
PN4/A20
46
P2
PB0/D8
82
R9
PF1/T1
11
D1
PN5/A21
47
T1
PB1/D9
83
V12
PF2/EC2/INT4
12
D2
PN6/A22
48
N5
PB2/D10
84
P10
PF3/T3
13
E2
PN7/A23
49
R2
PB3/D11
85
V13
PF4/BEEP
14
G5
DVSS7
50
P5
PB4/D12
86
R10
PG0/DACK0
15
E1
FAD0
51
U1
PB5/D13
87
V14
PG1/DREQ0/INT5
16
H4
FAD1
52
T2
PB6/D14
88
U11
PG2/DACK1/INT6
17
F2
FAD2
53
T3
PB7/D15
89
V15
PG3/DREQ1/INT7
18
H5
FAD3
54
R4
PA0/PWM
90
P11
TEST2
19
F1
FAD4
55
V2
PA1/SDA
91
U15
TEST3
20
G1
FAD5
56
U4
PA2/SCL
92
U12
TEST0
21
J4
FAD6
57
U3
PC0/SCK0
93
V16
TEST1
22
G2
FAD7
58
U5
PC1/SO0
94
R11
TEST6
23
H1
FCLE
59
U2
PC2/SI0
95
R12
EVA
24
J1
FALE
60
R5
PC3/SCS0
96
P12
AVSAD
25
H2
VDIODF
61
V3
DVSS2
97
U14
AVDAD
26
J5
FWE
62
P6
VDIO2
98
R13
AN0
27
K4
FRE
63
V4
KDI
99
U13
AN1
28
J2
FWP
64
V5
KRB
100
P14
AN2
29
K1
FCE0
65
U6
KCLK
101
V17
AN3
30
L4
FRB0
66
R6
KCS
102
R14
AN4
31
K2
FCE1
67
V6
KDO
103
U16
AN5
32
K5
FRB1
68
P7
TEST4
104
R15
AN6/INT8
33
L1
PP0
69
U7
PE0/TxD0
105
U17
AN7/INT9
34
L2
PP1
70
V7
PE1/RxD0
106
T16
RST
35
M4
DVDD0
71
V8
PE2/TXD1
107
T17
RAMBK
36
L5
DVSS1
72
R7
PE3/RXD1
108
P15
VDBK
–4–
CXR704060
Pin
No.
Pin
position
TDI
143
G15
R17
TMS
144
111
P13
TCK
112
T18
113
Pin
No.
Pin
position
Pin
No.
Pin
position
109
U18
AVDUO
177
E12
PI6/MUTFGR
110
F17
AVSPLL
178
B11
DVDD3
145
G14
AVDPLL
179
D11
DVSS5
TRST
146
E18
PQ0
180
E11
VDIO5
R18
TDO
147
E17
PQ1
181
A9
PJ0/WAIT
114
N15
VDIOJT
148
D18
PQ2
182
B9
PJ1/RE
115
N14
DVDD2
149
F15
PQ3
183
B10
PJ2/LWR/LB
116
P17
DVSS4
150
C18
PQ4
184
B8
PJ3/UWR/UB
117
M15
VDIO4
151
D17
PQ5
185
D10
PJ4/WE
118
P18
PD0/CONNECT
152
B18
PQ6
186
A8
PK0/CS0
119
M14
PD1/XVDATA
153
C17
PQ7
187
E10
PK1/CS1
120
N18
PD2/DPLS
154
E15
DVSS8
188
A7
PK2
121
N17
PD3/DMNS
155
F14
VDIO7
189
D9
PK3
122
M17
PD4/TXDPLS
156
C16
PR0
190
A6
PK4
123
M18
PD5/TXDMNS
157
D15
PR1
191
E9
PK5/CS5
124
L15
PD6/TXENL
158
B17
PR2
192
B7
PK6/CS6
125
L14
PD7/SUSPEND
159
B16
PR3
193
E8
PK7/CS7
126
L17
VBUS
160
A17
PR4
194
D8
DVSS6
127
K15
VDIOUS
161
A16
PR5
195
E7
VDIO6
128
L18
UDM
162
A15
PR6
196
B6
PL0/A0
129
K18
UDP
163
B15
PR7
197
D7
PL1/A1
130
K14
TRON
164
D14
DVSS9
198
A5
PL2/A2
131
K17
AVSDA
165
E14
VDIOMS
199
E6
PL3/A3
132
J15
VREFR
166
B14
MSDIO
200
B5
PL4/A4
133
J17
AOUTR
167
A14
MSBS
201
A4
PL5/A5
134
J18
AOUTL
168
A13
MSSCLK
202
B4
PL6/A6
135
H18
VREFL
169
B13
MSINS
203
D5
PL7/A7
136
J14
AVDDA
170
A12
PI7
204
A3
PM0/A8
137
H15
XTAL
171
D13
PI0/DADT
205
D6
PM1/A9
138
H14
EXTAL
172
A11
PI1/ADDT
206
A2
PM2/A10
139
H17
AVDMO
173
E13
PI2/LRCK
207
D4
PM3/A11
140
G18
AVSOSC
174
B12
PI3/XBCK
208
B3
DVSS0
141
G17
TX
175
D12
PI4/FS2S6
142
F18
TEX
176
A10
PI5/MUTFGL
Pin function
Pin function
–5–
Pin function
CXR704060
Pin Functions
Symbol
I/O power supply
Function
I/O
PJ0/WAIT
I/O / Input
Wait input for external bus.
PJ1/RE
I/O / Output
Read signal output for external
bus.
PJ2/LWR/
LB
I/O / Output /
Output
PJ3/UWR/
UB
I/O / Output /
Output
PJ4/WE
I/O / Output
PK0/CS0,
PK1/CS1
I/O / Output
PK2 to PK4
I/O
PK5/CS5 to
PK7/CS7
I/O / Output
PL0/A0 to
PL7/A7
PM0/A8 to
PM7/A15
PN0/A16 to
PN7/A23
(Port J)
5-bit I/O port.
I/O can be specified in
1-bit units.
Pull-up resistor can be
incorporated through
program in 1-bit units.
(5 pins)
Write strobe
signal output
for D0 to D7.
Strobe signal
output indicates
access to D0 to
D7.
Strobe signal
Write strobe
signal output output indicates
for D8 to D15. access to D8 to
D15.
Write signal output for external
bus.
(Port K)
8-bit I/O port.
I/O can be specified in
1-bit units.
Pull-up resistor can be
incorporated through
program in 1-bit units.
(8 pins)
I/O / Output
(Port L)
8-bit I/O port.
I/O can be specified in
1-bit units.
Pull-up resistor can be
incorporated through
program in 1-bit units.
(8 pins)
I/O / Output
(Port M)
8-bit I/O port.
I/O can be specified in
1-bit units.
Pull-up resistor can be
incorporated through
program in 1-bit units.
(8 pins)
I/O / Output
(Port N)
8-bit I/O port.
I/O can be specified in
1-bit units.
Pull-up resistor can be
incorporated through
program in 1-bit units.
(8 pins)
–6–
Chip select output for external
bus. (2 pins)
Chip select output for external
bus. (3 pins)
Address bus output for external
bus. (24 pins)
VDIO0
VDIO5
VDIO6
CXR704060
Symbol
I/O
Function
FAD0 to FAD7 I/O
Flash memory interface data I/O.
FCLE
Output
CLE output of flash memory interface.
FALE
Output
ALE output of flash memory interface.
FWE
Output
WE output of flash memory interface.
FRE
Output
RE output of flash memory interface.
FWP
Output
WP output of flash memory interface.
FCE0, FCE1
Output
CE output of flash memory interface.
FRB0, FRB1
Input
RB input of flash memory interface.
I/O
(Port P)
2-bit I/O port.
I/O can be specified in 1-bit units.
Pull-up resistor can be incorporated through program in
1-bit units.
(2 pins)
I/O / I/O
(Port O)
8-bit I/O port.
I/O can be specified in
1-bit units.
Pull-up resistor can be
incorporated through
program in 1-bit units.
(8 pins)
PP0, PP1
PO0/D0 to
PO7/D7
PB0/D8 to
PB7/D15
I/O / I/O
(Port B)
8-bit I/O port.
I/O can be specified in
1-bit units.
Pull-up resistor can be
incorporated through
program in 1-bit units.
(8 pins)
(Port A)
3-bit I/O port.
I/O can be specified in
1-bit units.
For Bit 0, pull-up resistor
can be incorporated
through program.
(3 pins)
VDIODF
Data bus I/O for external bus.
(16 pins)
VDIO1
VDIO2
VDIO3
PA0/PWM
I/O / Output
PA1/SDA
I/O / I/O
PA2/SCL
I/O / I/O
PC0/SCK0
I/O / I/O
PC1/SO0
I/O / Output
PC2/SI0
I/O / Input
PC3/SCS0
I/O / Input
(Port C)
4-bit I/O port.
I/O can be specified in
1-bit units.
Pull-up resistor can be
incorporated through
program in 1-bit units.
(4 pins)
KDI
Input
Serial interface data input for EEPROM.
KRB
Input
Serial interface Ready/Busy input for EEPROM.
–7–
I/O power supply
8-bit PWM output.
I2C bus interface data I/O.
I2C bus interface clock I/O.
Serial clock (CH0) I/O.
Serial data (CH0) output.
Serial data (CH0) input.
Serial chip select (CH0) input.
CXR704060
Symbol
I/O
I/O power supply
Function
KCLK
Output
Serial interface clock output for EEPROM.
KCS
Output
Serial interface chip select output for EEPROM.
KDO
Output
Serial interface data output for EEPROM.
PE0/TxD0
I/O / Output
PE1/RxD0
I/O / Input
PE2/TxD1
I/O / Output
PE3/RxD1
I/O / Input
PE4/SCK1
I/O / I/O
PE5/SO1
I/O / Output
Serial data (CH1) output.
PE6/SI1
I/O / Input
Serial data (CH1) input.
PE7/SCS1
I/O / Input
Serial chip select (CH1) input.
PF0/EC0/
INT3
I/O / Input /
Input
PF1/T1
I/O / Output
PF2/EC2/
INT4
I/O / Input /
Input
PF3/T3
I/O / Output
PF4/BEEP
Output /
Output
PG0/DACK0
I/O / Output
PG1/DREQ0/
INT5
I/O / Input /
Input
UART (CH0) transmit data
output.
(Port E)
8-bit I/O port.
I/O can be specified in
1-bit units.
Pull-up resistor can be
incorporated through
program in 1-bit units.
(8 pins)
(Port F)
Lower 4 bits are for I/O;
upper 1 bit is output-only
5-bit port.
For lower 4 bits, I/O can
be specified in 1-bit units.
For lower 4 bits, pull-up
resistor can be
incorporated through
program in 1-bit.
(5 pins)
UART (CH0) receive data
input.
UART (CH1) transmit data
output.
UART (CH1) receive data
input.
Serial clock (CH1) I/O.
External event
input to 8-bit
timer (CH0).
External
interruption
request input.
8-bit timer (CH1) output.
External event
input to 8-bit
timer (CH2).
External
interruption
request input.
VDIO1
VDIO2
VDIO3
8-bit timer (CH3) output.
Beep output.
Transfer request acknowledge
signal output from DMA
controller (CH0).
(Port G)
4-bit I/O port.
I/O can be specified in
1-bit units.
Pull-up resistor can be
incorporated through
program in 1-bit units.
(4 pins)
Transfer request External
input to DMA
interruption
controller (CH0). request input.
Transfer request
acknowledge
External
signal output
interruption
from DMA
request input.
controller (CH1).
PG2/DACK1/
INT6
I/O / Output /
Input
PG3/DREQ1/
INT7
I/O / Input /
Input
AN0 to AN5
Input
Analog input to A/D converter. (6 pins)
AN6/INT8,
AN7/INT9
Input / Input
Analog input to A/D
converter. (2 pins)
Transfer request External
input to DMA
interruption
controller (CH1). request input.
–8–
External interruption request
input. (2 pins)
AVDAD
CXR704060
Symbol
I/O
Function
PD0/
CONNECT
I/O / Input
USB connection input.
(for external USB transceiver)
PD1/XVDATA
I/O / Input
USB receive data input.
(for external USB transceiver)
PD2/DPLS
I/O / Input
PD3/DMNS
I/O / Input
PD4/TXDPLS
I/O / Output
PD5/TXDMNS I/O / Output
(Port D)
8-bit I/O port.
I/O can be specified in
1-bit units.
Pull-up resistor can be
incorporated through
program in 1-bit units.
(8 pins)
USB D+ data input.
(for external USB transceiver)
USB D– data input.
(for external USB transceiver)
USB D+ data output.
(for external USB transceiver)
I/O / Output
USB data control output.
(for external USB transceiver)
PD7/
SUSPEND
I/O / Output
USB suspend output.
(for external USB transceiver)
VBUS
Input
USB power signal input.
(USB connection detection signal input, for internal USB
transceiver)
UDM
I/O
USB D– data I/O. (for internal USB transceiver)
UDP
I/O
USB D+ data I/O. (for internal USB transceiver)
TRON
Output
UDP pull-up resistor connection control output.
VREFL
Output
Internal DAC reference voltage output. (Lch)
AOUTL
Output
Internal DAC Lch output.
AOUTR
Output
Internal DAC Rch output.
VREFR
Output
Internal DAC reference voltage output. (Rch)
I/O
(Port Q)
8-bit I/O port.
I/O can be specified in 1-bit units.
Pull-up resistor can be incorporated through program in
1-bit units. (8 pins)
I/O
(Port R)
8-bit I/O port.
I/O can be specified in 1-bit units.
Pull-up resistor can be incorporated through program in
1-bit units. (8 pins)
PR0 to PR7
–9–
VDIO4
USB D– data output.
(for external USB transceiver)
PD6/TXENL
PQ0 to PQ7
I/O power supply
VDIOUS
AVDDA
VDIO7
CXR704060
Symbol
I/O
Function
I/O power supply
PI0/DADT
I/O / Output
Audio data output to external
DAC. (for test output)
PI1/ADDT
I/O / Input
Audio data input from external
ADC. (for test input)
PI2/LRCK
I/O / I/O
PI3/XBCK
I/O / I/O
PI4/FS256
I/O / Output
PI5/MUTFGL
I/O / Output
PI6/MUTFGR
I/O / Output
PI7
I/O
MSDIO
I/O
Memory Stick interface data I/O.
MSBS
Output
Memory Stick interface bus state output.
MSSCLK
Output
Memory Stick interface clock output.
MSINS
Input
Memory Stick interface card detection input. (INT0)
TEST4
Input
Test input.
TEST2, TEST3 Input
Test input.
TEST0, TEST1 Input
Test input.
TEST6
Output
Test output.
EVA
Input
EVA mode switching input.
TDI
Input
Data input for JTAG boundary scanning test.
TMS
Input
Test mode control input for JTAG boundary scanning
test.
TCK
Input
Clock input for JTAG boundary scanning test.
TRST
Input
Reset input for JTAG boundary scanning test.
TDO
Output
Data output for JTAG boundary scanning test.
EXTAL
Input
AVDMO
XTAL
Output
Oscillation connector for main oscillation.
(When a clock is supplied externally, input it to EXTAL;
opposite phase clock should be input to XTAL.)
TEST5
Output
Test output.
VDIO1
VDIO2
VDIO3
TEX
Input
AVDUO
TX
Output
Oscillation connector for sub oscillation.
(When a clock is supplied externally, input it to TEX;
opposite phase clock should be input to TX.)
RST
Input
System reset input.
RAMBK
Input
Control signal input for RAM backup.
(Port I)
8-bit I/O port.
I/O can be specified in
1-bit units.
Pull-up resistor can be
incorporated through
program in 1-bit units.
(8 pins)
L/R sampling clock I/O to
external DAC/ADC. (44.1kHz)
Bit clock I/O to external
DAC/ADC. (2.822MHz)
VDIO0
VDIO5
VDIO6
256fs clock output.
(11.2896MHz)
Zero data detection signal
output. (Lch)
Zero data detection signal
output. (Rch)
VDIOMS
VDIO1
VDIO2
VDIO3
– 10 –
VDIOJT
AVDAD
CXR704060
Symbol
I/O
Function
VDBK
Positive power supply for RAM backup.
AVDAD
Positive power supply for A/D converter.
AVSAD
GND for A/D converter.
AVDDA
Positive power supply for internal DAC.∗1
AVSDA
GND for internal DAC.
AVDPLL
Positive power supply for PLL.∗2
AVSPLL
GND for PLL.
AVDUO
Positive power supply for main clock oscillator.∗1
Positive power supply for sub clock oscillator.∗2
AVSOSC
Main clock and sub clock oscillator GND.
VDIODF
Positive power supply for flash memory interface.
VDIOMS
Positive power supply for Memory Stick interface.
VDIOJT
Positive power supply for JTAG.
VDIOUS
Positive power supply for USB transceiver.
VDIO0 to
VDIO7
I/O interface positive power supply.
DVDD0 to
DVDD3
Positive power supply.
(Connect all four VDD pins to positive power supply.)
DVSS0 to
DVSS9
GND. (Connect all ten DVss pins to GND.)
AVDMO
∗1 AVDDA and AVDMO must be the same potential.
∗2 AVDPLL and AVDUO must be the same potential.
– 11 –
I/O power supply
CXR704060
• I/O Power Supply and Pin Correspondence Table
I/O power supply
Digital/Analog
Symbol
VDIO0
VDIO5
VDIO6
Digital power supply
PI0/DADT, PI1/ADDT, PI2/LRCK, PI3/XBCK, PI4/FS256,
PI5/MUTFGL, PI6/MUTFGR, PJ0/WAIT, PJ1/RE, PJ2/LWR/LB,
PJ3/UWR/UB, PJ4/WE, PK0/CS0, PK1/CS1, PK2, PK3, PK4,
PK5/CS5, PK6/CS6, PK7/CS7, PL0/A0 to PL7/A7,
PM0/A8 to PM7/A15, PN0/A16 to PN7/A23
VDIODF
Digital power supply
FAD0 to FAD7, FCLE, FALE, FWE, FRE, FWP, FCE0, FRB0,
FCE1, FRB1
VDIO1
VDIO2
VDIO3
Digital power supply
AVDAD
Analog power supply
PP0, PP1, PO0/D0 to PO7/D7, PB0/D8 to PB7/D15, PA0/PWM,
PA1/SDA, PA2/SCL, PC0/SCK0, PC1/SO0, PC2/SI0, PC3/SCS0,
KDI, KRB, KCLK, KCS, KDO, TEST4, PE0/TxD0, PE1/RxD0,
PE2/TxD1, PE3/RxD1, PE4/SCK1, PE5/SO1, PE6/SI1, PE7/SCS1,
TEST5, PF0/EC0/INT3, PF1/T1, PF2/EC2/INT4, PF3/T3,
PF4/BEEP, PG0/DACK0, PG1/DREQ0/INT5, PG2/DACK1/INT6,
PG3/DREQ1/INT7, TEST0 to TEST3, TEST6, EVA
AN0 to AN5, AN6/INT8, AN7/INT9 (RST, RAMBK) ∗1
VDIOJT
Digital power supply
TDI, TMS, TCK, TRST, TDO
VDIO4
Digital power supply
PD0/CONNECT, PD1/XVDATA, PD2/DPLS, PD3/DMNS,
PD4/TXDPLS, PD5/TXDMNS, PD6/TXENL, PD7/SUSPEND,
VBUS
VDIOUS
Digital power supply
UDM, UDP, TRON
AVDDA
Analog power supply
VREFR, AOUTR, AOUTL, VREFL
AVDMO
Analog power supply
XTAL, EXTAL
AVDUO
Analog power supply
TX, TEX
VDIO7
Digital power supply
PQ0 to PQ7, PR0 to PR7
VDIOMS
Digital power supply
MSDIO, MSBS, MSSCLK, MSINS, PI7
∗1 The H level input to RST and RAMBK must be the same potential as DVDD0 to DVDD3 and VDBK.
– 12 –
CXR704060
I/O Circuit Format for Pins
Pin
Circuit format
After a reset
VDIO
PWM
MPX
PA register
PASL register
"0" after a reset
PAD register
PA0/PWM
VDIO
"0" after a reset
Hi-Z
PAPUL register
"0" after a reset
Data bus
MPX
Input data
latch
RD
IP
CMOS
Schmitt input
SDA, SCL
MPX
PA register
PASL register
"0" after a reset
PA1/SDA
PA2/SCL
Hi-Z
PAD register
"0" after a reset
Data bus
MPX
Input data
latch
RD
IP
CMOS
Schmitt input
SDA, SCL
VDIO
D8 to D15
MPX
PB register
PBSL register
"0" after a reset
DE
PB0/D8
to
PB7/D15
MPX
PBD register
VDIO
"0" after a reset
PBPUL register
"0" after a reset
Data bus
MPX
Input data
latch
RD
IP
CMOS
Schmitt input
D8 to D15
– 13 –
Hi-Z
CXR704060
Pin
Circuit format
After a reset
VDIO
SCK0
MPX
PC register
PCSL register
"0" after a reset
SCK0E
MPX
PC0/SCK0
PCD register
VDIO
"0" after a reset
Hi-Z
PCPUL register
"0" after a reset
Data bus
MPX
Input data
latch
RD
IP
CMOS
Schmitt input
SCK0
VDIO
SO0
MPX
PC register
PCSL register
"0" after a reset
SO0E
MPX
PC1/SO0
PCD register
VDIO
"0" after a reset
Hi-Z
PCPUL register
"0" after a reset
Data bus
MPX
Input data
latch
RD
IP
CMOS
Schmitt input
VDIO
PC register
PCD register
"0" after a reset
PC2/SI0
PC3/SCS0
VDIO
Hi-Z
PCPUL register
"0" after a reset
Data bus
MPX
Input data
latch
RD
SI0, SCS0
– 14 –
IP
CMOS
Schmitt input
CXR704060
Pin
Circuit format
After a reset
VDIO
PD register
PDD register
"0" after a reset
VDIO
PDPUL register
PD0/CONNECT
PD1/XVDATA
PD2/DPLS
PD3/DMNS
"0" after a reset
Hi-Z
PDSL register
"0" after a reset
Data bus
MPX
Input data
latch
RD
IP
CMOS
Schmitt input
To USB interface
CONNECT, XVDATA, DPLS, DMNS
MPX
CONNECT, XVDATA, DPLS, DMNS
Signals from internal USB transceiver
TXDPLS, TXDMNS,
TXENL, SUSPEND
VDIO
MPX
PD register
PDSL register
"0" after a reset
PD4/TXDPLS
PD5/TXDMNS
PD6/TXENL
PD7/SUSPEND
PDD register
VDIO
"0" after a reset
PDPUL register
"0" after a reset
Data bus
MPX
RD
Input data
latch
IP
CMOS
Schmitt input
– 15 –
Hi-Z
CXR704060
Pin
Circuit format
After a reset
VDIO
TXD0, TXD1
MPX
PE register
PESL register
"0" after a reset
PED register
PE0/TXD0
PE2/TXD1
VDIO
"0" after a reset
Hi-Z
PEPUL register
"0" after a reset
Data bus
MPX
Input data
latch
RD
IP
CMOS
Schmitt input
VDIO
PE register
PED register
PE1/RXD0
PE3/RXD1
PE6/SI1
PE7/SCS1
"0" after a reset
VDIO
Hi-Z
PEPUL register
"0" after a reset
Data bus
MPX
Input data
latch
RD
IP
CMOS
Schmitt input
RXD0, RXD1, SI1, SCS1
VDIO
SCK1
MPX
PE register
PESL register
"0" after a reset
SCK1E
MPX
PED register
PE4/SCK1
VDIO
"0" after a reset
PEPUL register
"0" after a reset
Data bus
MPX
Input data
latch
RD
IP
CMOS
Schmitt input
SCK1
– 16 –
Hi-Z
CXR704060
Pin
Circuit format
After a reset
VDIO
SO1
MPX
PE register
PESL register
"0" after a reset
SO1E
MPX
PE5/SO1
PED register
VDIO
"0" after a reset
Hi-Z
PEPUL register
"0" after a reset
Data bus
MPX
Input data
latch
RD
IP
CMOS
Schmitt input
VDIO
PF register
PFD register
"0" after a reset
VDIO
PF0/EC0/INT3
PF2/EC2/INT4
Hi-Z
PFPUL register
"0" after a reset
Data bus
MPX
Input data
latch
RD
IP
CMOS
Schmitt input
EC0,EC2
INT3, INT4
VDIO
T1, T3
MPX
PF register
PFSL register
"0" after a reset
PFD register
PF1/T1
PF3/T3
VDIO
"0" after a reset
PFPUL register
"0" after a reset
Data bus
MPX
RD
Input data
latch
IP
CMOS
Schmitt input
– 17 –
Hi-Z
CXR704060
Pin
Circuit format
After a reset
VDIO
BEEP
MPX
PF register
"0" after a reset
PF4/BEEP
Hi-Z
PFSL register
BEEPE
Data bus
RD
VDIO
DACK0
MPX
PG register
PGSL register
"0" after a reset
PGD register
PG0/DACK0
VDIO
"0" after a reset
Hi-Z
PGPUL register
"0" after a reset
Data bus
MPX
Input data
latch
RD
IP
CMOS
Schmitt input
VDIO
PG register
PGD register
"0" after a reset
PG1/DREQ0/
INT5
PG3/DREQ1/
INT7
VDIO
Hi-Z
PGPUL register
"0" after a reset
Data bus
MPX
Input data
latch
RD
DREQ0, DREQ1
INT5, INT7
– 18 –
IP
CMOS
Schmitt input
CXR704060
Pin
Circuit format
After a reset
VDIO
DACK1
MPX
PG register
PGSL register
"0" after a reset
PGD register
PG2/DACK1/
INT6
VDIO
"0" after a reset
Hi-Z
PGPUL register
"0" after a reset
Data bus
MPX
Input data
latch
RD
IP
CMOS
Schmitt input
INT6
DADT, FS256,
MUTFGL, MUTFGR
VDIO
MPX
PI register
PISL register
"0" after a reset
PI0/DADT
PI4/FS256
PI5/MUTFGL
PI6/MUTFGR
PID register
VDIO
"0" after a reset
Hi-Z
PIPUL register
"0" after a reset
Data bus
MPX
Input data
latch
RD
IP
CMOS
Schmitt input
VDIO
PI register
PID register
"0" after a reset
VDIO
PI1/ADDT
Hi-Z
PIPUL register
"0" after a reset
Data bus
MPX
Input data
latch
RD
ADDT
– 19 –
IP
CMOS
Schmitt input
CXR704060
Pin
Circuit format
After a reset
VDIO
LRCK, XBCK
MPX
PI register
PISL register
"0" after a reset
LRCKE, XBCKE
MPX
PI2/LRCK
PI3/XBCK
PID register
VDIO
"0" after a reset
Hi-Z
PIPUL register
"0" after a reset
Data bus
MPX
Input data
latch
RD
IP
CMOS
Schmitt input
LRCK, XBCK
VDIOMS
PI register
PID register
"0" after a reset
VDIOMS
PI7
Hi-Z
PIPUL register
"0" after a reset
Data bus
MPX
Input data
latch
RD
IP
CMOS
Schmitt input
VDIO
PJ register
PJD register
"0" after a reset
VDIO
PJ0/WAIT
Hi-Z
PJPUL register
"0" after a reset
Data bus
MPX
Input data
latch
RD
WAIT
– 20 –
IP
CMOS
Schmitt input
CXR704060
Pin
Circuit format
After a reset
VDIO
RE, LWR/LB, UWR/UB, WE
MPX
PJ register
PJSL register
"0" after a reset
PJ1/RE
PJ2/LWR/LB
PJ3/UWR/UB
PJ4/WE
PJD register
VDIO
"0" after a reset
Hi-Z
PJPUL register
"0" after a reset
Data bus
MPX
Input data
latch
RD
IP
CMOS
Schmitt input
VDIO
CS0, CS1, CS5 to CS7
MPX
PK register
PKSL register
PK0/CS0
to
PK1/CS1
"0" after a reset
PKD register
VDIO
"0" after a reset
PK5/CS5
to
PK7/CS7
Hi-Z
PKPUL register
"0" after a reset
Data bus
MPX
Input data
latch
RD
IP
CMOS
Schmitt input
VDIO
PK register
PKD register
"0" after a reset
VDIO
PK2 to PK4
Hi-Z
PKPUL register
"0" after a reset
Data bus
MPX
RD
Input data
latch
IP
CMOS
Schmitt input
– 21 –
CXR704060
Pin
Circuit format
After a reset
VDIO
A0 to A7
MPX
PL register
PLSL register
"0" after a reset
AE
PL0/A0
to
PL7/A7
MPX
PLD register
VDIO
"0" after a reset
Hi-Z
PLPUL register
"0" after a reset
Data bus
MPX
Input data
latch
RD
IP
CMOS
Schmitt input
VDIO
A8 to A15
MPX
PM register
PMSL register
"0" after a reset
AE
PM0/A8
to
PM7/A15
MPX
PMD register
VDIO
"0" after a reset
PMPUL register
"0" after a reset
Data bus
MPX
RD
Input data
latch
IP
CMOS
Schmitt input
– 22 –
Hi-Z
CXR704060
Pin
Circuit format
After a reset
VDIO
A16 to A23
MPX
PN register
PNSL register
"0" after a reset
AE
PN0/A16
to
PN7/A23
MPX
PND register
VDIO
"0" after a reset
Hi-Z
PNPUL register
"0" after a reset
Data bus
MPX
Input data
latch
RD
IP
CMOS
Schmitt input
VDIO
D0 to D7
MPX
PO register
POSL register
"0" after a reset
DE
PO0/D0
to
PO7/D7
MPX
POD register
VDIO
"0" after a reset
Hi-Z
POPUL register
"0" after a reset
Data bus
MPX
Input data
latch
RD
IP
CMOS
Schmitt input
D0 to D7
VDIO
PP register
PPD register
"0" after a reset
PP0
PP1
VDIO
Hi-Z
PPPUL register
"0" after a reset
Data bus
MPX
RD
Input data
latch
IP
CMOS
Schmitt input
– 23 –
CXR704060
Pin
Circuit format
After a reset
VDIO
PQ register
PQD register
"0" after a reset
VDIO
PQ0 to PQ7
Hi-Z
PQPUL register
"0" after a reset
Data bus
MPX
Input data
latch
RD
IP
CMOS
Schmitt input
VDIO
PR register
PRD register
"0" after a reset
VDIO
PR0 to PR7
Hi-Z
PRPUL register
"0" after a reset
Data bus
MPX
Input data
latch
RD
IP
CMOS
Schmitt input
RST
AN0 to AN5
To A/D converter
AN0 to AN5
Hi-Z
IP
RST
AN6/INT8
AN7/INT9
To A/D converter
AN6, AN7
IP
Hi-Z
INT8, INT9
AVDAD × (0.7 ± 0.1)
– 24 –
CXR704060
Pin
Circuit format
After a reset
VDIODF
FAD0 to FAD7
output data
FAD0 to FAD7
output enable
FAD0 to FAD7
VDIODF
"L" output
FAD0 to FAD7
pull-up control
FAD0 to FAD7
input data
IP
CMOS
Schmitt input
FCLE
FALE
FWE
FRE, FWR,
FCE0, FCE1
VDIODF
FCL, FALE, FWE, FRE,
FWR, FCE0, FCE1
"L" output
FRB0, FRB1
FRB0
FRB1
"L" output
IP
CMOS
Schmitt input
KDI
KRB
IP
KDI, KRB
Hi-Z
VDIO
KDO
"L" output
KDO
VDIO
KCS
KCLK
"H" output
KCS, KCLK
EVA
IP
EVA
Hi-Z
VBUS
IP
VBUS
Hi-Z
– 25 –
CXR704060
Pin
Circuit format
After a reset
VDIOUS
TRON output data
TRON
Hi-Z
TRON output enable
VDIOMS
MSDIO output data
MSDIO output enable
MSDIO
Hi-Z
IP
MSDIO input data
CMOS
Schmitt input
VDIOMS
MSBS
MSSCLK
"L" output
MSBS, MSSCLK
MSINS
IP
MSINS
Hi-Z
AVDMO
EXTAL
XTAL
EXTAL
• Diagram shows the circuit
configuration during
oscillation.
IP
Oscillation
• XTAL is "H" level when
oscillation is stopped.
XTAL
AVDUO
TEX
TX
TEX
• Diagram shows the circuit
configuration during
oscillation.
IP
• TX is "H" level when
oscillation is stopped.
TX
– 26 –
Oscillation
CXR704060
Pin
Circuit format
RAMBK
IP
After a reset
RAMBK
Hi-Z
VDIOJT
TDI
TMS
TCK
Pull-up
IP
TDI, TMS, TCK
IP
TRST
TRST
Pull-down
VDIOJT
VDIOJT
TDO output data
Hi-Z
TDO
TDO output enable
IP
RST
(to reset circuit)
RST
Hi-Z
To AN0 to AN7
TEST0
(to test circuit)
IP
TEST0
Hi-Z
CMOS
Schmitt input
TEST1
to
TEST3
TEST4
IP
TEST1 to TEST3
(to test circuit)
IP
TEST4
(to test circuit)
VDIO
CMOS
Schmitt input
Hi-Z
Pull-down
VDIO
TEST5
TEST6
"L" output
TEST5, TEST6
(from test circuit)
– 27 –
CXR704060
Absolute Maximum Ratings
Item
Supply voltage
Input voltage
(DVSS = 0V reference)
Symbol
Rating
Unit
DVDD
–0.3 to +2.5
V
DVDD0, DVDD1, DVDD2, DVDD3
VDBK
–0.3 to +2.5
V
Power supply for backup RAM
AVDAD
–0.3 to +4.5
V
AVDDA
–0.3 to +4.5
V
AVDMO
–0.3 to +4.5
V
AVDUO
–0.3 to +4.5
V
AVDPLL
–0.3 to +4.5
V
VDIO
–0.3 to +4.5
V
VDIODF
–0.3 to +4.5
V
VDIOJT
–0.3 to +4.5
V
VDIOUS
–0.3 to +4.5
V
VDIOMS
–0.3 to +4.5
–0.3 to +4.5∗1
V
VIN
VINR
–0.3 to +2.5∗2
–0.3 to +4.5∗1
Remarks
VDIO0, VDIO1, VDIO2, VDIO3,
VDIO4, VDIO5, VDIO6, VDIO7
V
Excludes RST and RAMBK pins
V
RST and RAMBK pins
Output voltage
VOUT
High level output current
IOH
–5
mA
Output (value per pin)
High level total output current
ΣIOH
–40
mA
Total for all output pins
Low level output current
IOL
10
mA
Output (value per pin)
Low level total output current
ΣIOL
80
mA
Total for all output pins
Operating temperature
Topr
–20 to +70
°C
Storage temperature
Tstg
–55 to +150
°C
Allowable power dissipation
PD
380
mW
V
∗1 VIN and VOUT must not exceed I/O supply voltage (VDIO, VDIODF, VDIOJT, VDIOUS and VDIOMS) + 0.3V.
∗2 VINR must not exceed DVDD + 0.3V.
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI.
Normal operation should be conducted under the recommended operating conditions. Exceeding these
conditions may adversely affect the reliability of the LSI.
– 28 –
CXR704060
Recommended Operating Conditions
(DVSS = 0V reference)
Max.
Unit
Remarks
1.1
1.3
V
DVDD0, DVDD1, DVDD2, DVDD3
1.1
1.3
V
∗1
AD converter supply voltage AVDAD
2.2
3.3
V
DAC supply voltage
AVDDA
2.2
3.3
V
Main oscillation voltage
AVDMO
2.2
3.3
V
Sub oscillation voltage
AVDUO
2.7
3.3
V
PLL voltage
AVDPLL
2.7
3.3
V
I/O voltage
VDIO
DVDD
3.6
V
JTAG voltage
VDIOJT
1.65
3.3
V
FLASH I/F voltage with ECC VDIODF
2.7
3.6
V
Memory Stick I/F voltage VDIOMS
2.7
3.6
V
USB transceiver voltage
3.0
3.45
V
Item
Symbol
Min.
Internal supply voltage
DVDD
Supply voltage for
internal RAM backup
VDBK
High level input voltage
VDIOUS
Operating temperature
∗1
∗2
∗3
∗4
∗5
∗6
∗7
∗8
3.3
VDIO0, VDIO1, VDIO2, VDIO3,
VDIO4, VDIO5, VDIO6, VDIO7
VIHR
0.7DVDD
DVDD
V
RST pin
VIHBK
0.7VDBK
VDBK
V
RAMBK pin
VIHS
0.7VDIO
VDIO
V
VIHMSS
0.7VDIOMS
VDIOMS
V
VIHDFS
0.7VDIODF
VDIODF
V
0.7VDIO
VDIO
V
VIHJTC
0.7VDIOJT
VDIOJT
V
VIHMSC
0.7VDIOMS
VDIOMS
V
CMOS input∗6
CMOS input∗7
VIHKW
0.8AVDAD
AVDAD
V
AN6 and AN7 pins∗8
VILR
0
0.2DVDD
V
RST pin
VILBK
0
0.2VDBK
V
RAMBK pin
VILS
0
0.2VDIO
V
VILMSS
0
0.2VDIOMS
V
VILDFS
0
0.2VDIODF
V
VILC
0
0.2VDIO
V
VILJTC
0
0.2VDIOJT
V
VILMSC
0
0.2VDIOMS
V
CMOS input∗6
CMOS input∗7
VILKW
0
0.6AVDAD
V
AN6 and AN7 pins∗8
Topr
–20
+70
°C
VIHC
Low level input voltage
Typ.
CMOS Schmitt trigger input∗2
CMOS Schmitt trigger input∗3
CMOS Schmitt trigger input∗4
CMOS input∗5
CMOS Schmitt trigger input∗2
CMOS Schmitt trigger input∗3
CMOS Schmitt trigger input∗4
CMOS input∗5
VDBK should be the same voltage as DVDD (DVDD ± 0.1V or less).
Each pin of normal input ports (PA to PE, PF0 to PF3, PG, PI0 to PI6, PJ to PR, TEST0).
MSDIO and PI7 pins.
FAD0 to FAD7, FRB0 and FRB1 pins.
KDI, KRB, TEST1 to TEST4, EVA and VBUS pins.
TDI, TMS, TCK and TRST pins.
MSINS pins.
Do not set AN6 and AN7 to the center potential in the steady state.
(Low level input voltage: 0 to 0.4V, High level input voltage: (AVDAD – 0.4V) to AVDAD)
– 29 –
CXR704060
Electrical Characteristics
DC Characteristics
(DVDD = VDBK = 1.1 to 1.3V, AVDAD = AVDDA = AVDMO = 2.2 to 3.3V, AVDUO = AVDPLL = 2.7 to 3.3V)
(VDIO = VDIODF = VDIOMS = 2.7 to 3.6V, VDIOJT = 2.7 to 3.3V, VDIOUS = 3.0 to 3.45V)
(Topr = –20 to +70°C, DVSS = 0V reference)
Item
High level
output
voltage
Low level
output
voltage
Symbol
VOH
VOL
Pins
Conditions
PA0/PWM, PB, PD to PG,
PI0 to PI6, PJ to PR ∗1
VDIO = 2.7V,
IOH = –2.0mA
PI7
VDIOMS = 2.7V,
IOH = –2.0mA
D0 to D15, PC0/SCK0,
PC1/SO0, PC2, PC3,
TXDPLS, TXDMNS, TXENL,
SUSPEND, TXD0, TXD1,
SCK1, SO1, BEEP, DACK0,
VDIO = 2.7V,
DACK1, DADT, LRCK,
IOH = –4.0mA
XBCK, FS256, MUTFGL,
MUTFGR, RE, LWR/LB,
UWR/UB, WE, CS0, CS1,
CS5 to CS7, A0 to A23,
KDO, KCLK, KCS ∗2
Min.
Typ.
Max.
Unit
VDIO – 0.4
V
VDIOMS – 0.4
V
VDIO – 0.4
V
TDO
VDIOJT = 2.7V,
IOH = –4.0mA
VDIOJT – 0.4
V
TRON
VDIOUS = 3.0V,
IOH = –4.0mA
VDIOUS – 0.4
V
MSDIO, MSBS, MSSCLK
VDIOMS = 2.7V,
IOH = –4.0mA
VDIOMS – 0.4
V
FAD0 to FAD7, FCLE,
FALE, FWE, FRE, FWP,
FCE0, FCE1
VDIODF = 2.7V,
IOH = –4.0mA
VDIODF – 0.4
V
PA0/ PWM, PB, PD to PG,
PI0 to PI6, PJ to PR ∗1
VDIO = 2.7V,
IOL = 2.0mA
0.4
V
PI7
VDIOMS = 2.7V,
IOL = 2.0mA
0.4
V
FRB0, FRB1
VDIODF = 2.7V,
IOL = 2.0mA
0.4
V
0.4
V
0.4
V
PA1/ SDA, PA2/SCL,
D0 to D15, PC0/SCK0,
PC1/SO0, PC2, PC3,
TXDPLS, TXDMNS, TXENL,
SUSPEND, TXD0, TXD1,
SCK1, SO1, BEEP, DACK0, VDIO = 2.7V,
DACK1, DADT, LRCK,
IOL = 4.0mA
XBCK, FS256, MUTFGL,
MUTFGR, RE, LWR/LB,
UWR/UB, WE, CS0, CS1,
CS5 to CS7, A0 to A23,
KDO, KCLK, KCS ∗2
TDO
VDIOJT = 2.7V,
IOL = 4.0mA
– 30 –
CXR704060
Item
Low level
output
voltage
Symbol
VOL
Pins
IIL∗3
I/O
leakage
current
IZL
Typ.
Max.
Unit
VDIOUS = 3.0V,
IOL = 4.0mA
0.4
V
MSDIO, MSBS, MSSCLK
VDIOMS = 2.7V,
IOL = 4.0mA
0.4
V
FAD0 to FAD7, FCLE,
FALE, FWE, FRE, FWP,
FCE0, FCE1
VDIODF = 2.7V,
IOL = 4.0mA
0.4
V
PI7
FAD0 to FAD7
IZH ∗3
Min.
TRON
PA to PG, PI0 to PI6,
PJ to PR
Input
current
Conditions
VDIO = 2.7V,
VIL = VSS
–30
VDIO = 3.6V,
VIL = VSS
VDIOMS = 2.7V,
VIL = VSS
–150
–30
VDIOMS = 3.6V,
VIL = VSS
VDIODF = 2.7V,
VIL = VSS
VDIODF = 3.6V,
VIL = VSS
µA
µA
µA
–150
–30
µA
µA
–150
µA
PA to PG, PI0 to PI6,
PJ to PR, KDI, KRB, KDO,
KCLK, KCS,
TEST0 to TEST6, EVA,
VBUS
VDIO = 3.6V,
VI = 3.6V
10
µA
TDO
VDIOJT = 3.3V,
VI = 3.3V
10
µA
TRON
VDIOUS = 3.45V,
VI = 3.45V
10
µA
PI7, MSDIO, MSBS,
MSSCLK, MSINS
VDIOMS = 3.6V,
VI = 3.6V
10
µA
FAD0 to FAD7, FCLE,
FALE, FWE, FRE, FWP,
FCE0, FCE1, FRB0, FRB1
VDIODF = 3.6V,
VI = 3.6V
10
µA
AN0 to AN7
AVDAD = 3.3V,
VI = 3.3V
10
µA
RAMBK, RST
VDBK = 1.3V,
VI = 1.3V
10
µA
PA to PG, PI0 to PI6,
PJ to PR, KDI, KRB, KDO,
KCLK, KCS,
TEST0 to TEST6, EVA,
VBUS
VDIO = 3.6V,
VI = 0V
–10
µA
TDO
VDIOJT = 3.3V,
VI = 0V
–10
µA
TRON
VDIOUS = 3.45V,
VI = 0V
–10
µA
PI7, MSDIO, MSBS,
MSSCLK, MSINS
VDIOMS = 3.6V,
VI = 0V
–10
µA
– 31 –
CXR704060
Item
I/O
leakage
current
Max.
Unit
VDIODF = 3.6V,
VI = 0V
–10
µA
AN0 to AN7
AVDAD = 3.3V,
VI = 0V
–10
µA
RAMBK, RST
VDBK = 1.3V,
VI = 0V
–10
µA
PA to PG, PI to PR,
AN0 to AN7, FAD0 to FAD7,
FRB0, FRB1, MSDIO,
MSINS, KRB, KDI, EVA,
TEST0 to TEST4, RAMBK,
RST
Clock 1MHz
0V except the
measured pins
11
pF
Symbol
IZL
Input
CIN
capacitance
Pins
Conditions
FAD0 to FAD7, FCLE,
FALE, FWE, FRE, FWP,
FCE0, FCE1, FRB0, FRB1
Min.
Typ.
∗1 When used as PA0/PWM, PB, PD to PG and PI to PO, specified at IOH = –2.0mA and IOL = 2.0mA.
∗2 When used as PA1/SDA, PA2/SCL, PC and dual function pins, specified at IOH = –4.0mA and IOL = 4.0mA.
∗3 The PA to PG, PI to PR and FAD0 to FAD7 pins specify the input current when the pull-up resistor is
selected, and specify the leakage current when non-resistor is selected.
(Topr = –20 to +70°C, DVDD = 1.1 to 1.3V, DVss = 0V reference)
Item
Pins
Symbol
IDD1
Supply
current∗1
IDD2
DVDD/VDBK
IDDI
IDDS1
IDDS2
∗1
∗2
∗3
∗4
Conditions
Main execution mode∗2
fSRC = 22.58MHz crystal oscillation
1/2 frequency division (11.29MHz)
(C1 = C2 = 10pF)∗4
Main execution mode∗3
fSRC = 22.58MHz crystal oscillation
(C1 = C2 = 10pF)∗4
Main idle mode
fSRC = 22.58MHz crystal oscillation
(C1 = C2 = 10pF)∗4
Stop mode
Ta = 25°C (DVDD = 1.2V)
Ta = –20 to +50°C
Min.
Typ.
Max.
Unit
—
4.5
7.5
mA
—
—
29
mA
—
3.5
6.5
mA
100
300
—
1500
—
When all output pins are left open, this indicates the current flowing to DVDD and VDBK.
During ATRAC3 decoding operation.
When the arithmetic accelerator circuit is always operating.
C1 and C2 indicate the external capacitors attached to the EXTAL and XTAL pins, respectively.
– 32 –
µA
CXR704060
AC Characteristics
(1) EXTAL pins
1) Automatic oscillation
(Topr = –20 to +70°C, DVDD = VDBK = 1.1 to 1.3V, AVDMO = 2.2 to 3.3V, AVSOSC = DVss = 0V reference)
Item
Symbol
Oscillation frequency
Conditions
fSRC
Min.
Typ.
Max.
Unit
22.4
22.5792
22.8
MHz
2) When inputting pulses to EXTAL pin
(Topr = –20 to +70°C, DVDD = VDBK = 1.1 to 1.3V, AVDMO = 2.2 to 3.3V, AVSOSC = DVss = 0V reference)
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
High level pulse width
tWHX
16
ns
Low level pulse width
tWLX
16
ns
Pulse period
tCX
43.9
Input high level
VIHX
0.7AVDMO
Input low level
VILX
0.2AVDMO
V
Rise time, fall time
tR , t F
7
ns
44.6
ns
V
Note) When the clock is supplied externally, input to the EXTAL pin and input an opposite phase clock to
the XTAL pin.
tCX
tWHX
tWLX
VIHX
VIHX – (VIHX – VILX) × 0.1
AVDMO/2
EXTAL
tR
VILX + (VIHX – VILX) × 0.1
VILX
tF
Fig. 1. Main Clock Timing
– 33 –
CXR704060
(2) TEX pin
1) Automatic oscillation
(Topr = –20 to +70°C, DVDD = VDBK = 1.1 to 1.3V, AVDUO = 2.7 to 3.3V, AVSOSC = DVss = 0V reference)
Item
Symbol
Oscillation frequency
Conditions
Min.
fTEX
Typ.
8
Max.
Unit
16
MHz
2) When inputting pulses to TEX pin
(Topr = –20 to +70°C, DVDD = VDBK = 1.1 to 1.3V, AVDUO = 2.7 to 3.3V, AVSOSC = DVss = 0V reference)
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
High level pulse width
tWHTX
25
ns
Low level pulse width
tWLTX
25
ns
Pulse period
tCTX
62.5
Input high level
VIHTX
0.7AVDUO
Input low level
VILTX
0.2AVDUO
V
Rise time, fall time
t R , tF
7
ns
125
ns
V
Note) When the clock is supplied externally, input to the TEX pin and input an opposite phase clock to the
TX pin.
tCTX
tWHTX
tWLTX
VIHTX
VIHTX – (VIHTX – VILTX) × 0.1
AVDUO/2
TEX
tR
VILTX + (VIHTX – VILTX) × 0.1
VILTX
tF
Fig. 2. Sub Clock Timing
– 34 –
CXR704060
3) Serial transfer (CH0, CH1)
(Topr = –20 to +70°C, DVDD = 1.1 to 1.3V, VDIO = 2.7 to 3.3V, DVSS = 0V reference)
Item
Symbol
Conditions
Min.
Max.
Unit
SCK0
Input mode
6/fPS2
—
ns
SCK1
Output mode
1/fSCK
—
ns
tKH
SCK0
Input mode
3/fPS2
—
ns
tKL
SCK1
Output mode
0.5/fSCK – 5
—
ns
SI0
SCLK input mode
–2/fPS2 + 5
—
ns
SI1
SCLK output mode
35
—
ns
SI0
SCLK input mode
2/fPS2 + 5
—
ns
SI1
SCLK output mode
0
—
ns
SO0
SCLK input mode
—
3/fPS2 + 40
ns
SO1
SCLK output mode
—
5
ns
SCK cycle time
tKCY
SCK high, low pulse
width
SI input setup time
(for SCK↑)
tSIK
SI input hold time
(for SCK↑)
tKSI
SCK↓ → SO delay time
tKSO
Note
Note
Note
Note
Pins
1) The load capacitance of the measurement pin is 75pF.
2) fSCK: Serial clock
3) fPS2: PS2 clock (fPS2 = fSRC/4)
4) fSCK = fPS2/{2 × (Register setting value + 1)}: Register setting value (01h to FFh)
tKCY
tKL
tKH
SCK0
SCK1
tSIK
SI0
SI1
tKSI
Input data
tKSO
SO0
SO1
Output data
Fig. 3. Serial CH0 and CH1 Transfer Timing
– 35 –
CXR704060
4) Serial transfer (Memory Stick)
(Topr = –20 to +70°C, DVDD = 1.1 to 1.3V, VDIOMS = 2.7 to 3.6V, DVSS = 0V reference)
Symbol
Item
Pins
Conditions
Min.
Max.
Unit
1000/fMSCK
—
ns
500/fMSCK – 5
—
ns
MSSCLK cycle time
tKCY
MSSCLK high, low pulse width
tKH, tKL MSSCLK
MSBS output delay time
tBSD
MSBS
For MSSCLK↓
—
10
ns
MSDIO output delay time
tDIOD
MSDIO
For MSSCLK↓
—
10
ns
MSDIO input setup time
tDIOS
MSDIO
For MSSCLK↑
14
—
ns
MSDIO input hold time
tDIOH
MSDIO
For MSSCLK↑
5
—
ns
MSSCLK
Note 1) The load capacitance is 26pF.
Note 2) The oscillation of the TEX pin is at 50% duty.
Note 3) fMSCK is as follows for fSRC from the main oscillation circuit or fTEX from the sub oscillation circuit.
Shift clock frequency division ratio
fMSCK [MHz]
Main oscillation 1/2 frequency division
fSRC/2
Main oscillation 1/4 frequency division
fSRC/4
Sub oscillation
fTEX
tKCY
0.7VDIOMS
MSSCLK
0.2VDIOMS
tKL
tKH
Bus state output
MSBS
tBSD
MSDIO (output)
Output data
tDIOD
MSDIO (input)
Input data
tDIOS
Fig. 4. Memory Stick Transfer Timing
– 36 –
tDIOH
CXR704060
5) Flash memory interface characteristics
(Topr = –20 to +70°C, DVDD = 1.1 to 1.3V, VDIODF = 2.7 to 3.3V, DVSS = 0V reference)
Item
Symbol
Pins
Conditions
Min.
Max.
Unit
T × (RSTB setting value) – 10
—
ns
FRE low pulse width
tRECY
FRE
FRE↑ setup time
tRSFA
FAD[7:0]
35
—
ns
FRE↑ hold time
tRHFA
FAD[7:0]
0
—
ns
FEW low pulse width
tWECY
FWE
T × (WSTB setting value) – 10
—
ns
FWE↑ setup time
tWSFA
FAD[7:0]
T × (WSTP setting value +
WSTB setting value) – 10
—
ns
FWE↑ hold time
tWHFA
FAD[7:0]
T × (WHLD setting value) – 10
—
ns
Note 1) "T" indicates the 1 cycle (1/fSRC) of the system clock.
Note 2) RSTB, WSTB, WSTP and WHLD indicate the register set to the flash memory interface WE/RE
timing register (FIWERETR).
See the table below for allowable setting values.
Note 3) The load capacitance of the measurement pin is 75pF.
RSTB, WSTB, WSTP and WHLD setting value
Item
Bits within FIWERETR register
Allowable setting values
WSTP
[27:24]
0h to Fh
WSTB
[23:20]
0h to Fh
WHLD
[19:16]
0h to Fh
RSTB
[7:4]
0h to Fh
– 37 –
CXR704060
• During Read
tRECY
FRE
VDIODF/2
tRSFA
tRHFA
FAD[7:0]
• During Write
tWECY
FWE
VDIODF/2
tWSFA
FAD[7:0]
Fig. 5. Flash Memory Interface Transfer Timing with ECC
– 38 –
tWHFA
CXR704060
6) Bus interface unit (BIU) characteristics
• 2-cycle access AC characteristics parameter in write operation
(Topr = –20 to +70°C, DVDD = 1.1 to 1.3V, VDIO = 2.7 to 3.3V, DVSS = 0V reference)
Item
Symbol
Min.
Max.
Unit
Address setup time for UWR (UB) and LWR (LB) ↓
tADULD1
3/2fSRC – 5
—
ns
CS↓ and WE↓ setup time for UWR (UB) and LWR (LB) ↓
tCWULD1
3/2fSRC – 5
—
ns
Address hold time for UWR (UB) and LWR (LB) ↑
tULADD1
1/2fSRC – 5
—
ns
CS↑ and WE↑ hold time for UWR (UB) and LWR (LB) ↑
tULCWD1
1/2fSRC – 5
—
ns
UWR (UB) and LWR (LB) low pulse width
tWUL1
1/fSRC
—
ns
Data setup time for UWR (UB) and LWR (LB) ↓
tDULD1
1/2fSRC – 5
—
ns
Data hold time for CS↑ and WE↑
tDD1
0
—
ns
Note) The load capacitance of the measurement pin is 75pF.
Tw
T1
T2
Address
tADULD1
tULADD1
tCWULD1
tULCWD1
CS, WE
tWUL1
UWR, UB,
LWR, LB
RD
tDD1
tDULD1
D15 to D0
Valid
Fig. 6. 2-cycle Access Basic Timing in Write Operation
– 39 –
CXR704060
• 3-cycle access AC characteristics parameter in write operation
(Topr = –20 to +70°C, DVDD = 1.1 to 1.3V, VDIO = 2.7 to 3.3V, DVSS = 0V reference)
Item
Symbol
Min.
Max.
Unit
Address setup time for UWR (UB) and LWR (LB) ↓
tADULD2
2/fSRC – 5
—
ns
CS↓ and WE↓ setup time for UWR (UB) and LWR (LB) ↓
tCWULD2
2/fSRC – 5
—
ns
Address hold time for UWR (UB) and LWR (LB) ↑
tULADD2
1/fSRC – 5
—
ns
CS↑ and WE↑ hold delay time for UWR (UB) and LWR (LB) ↑
tULCWD2
1/fSRC – 5
—
ns
UWR (UB) and LWR (LB) low pulse width
tWUL2
1/fSRC
—
ns
Data setup time for UWR (UB) and LWR (LB) ↓
tDULD2
1/fSRC – 5
—
ns
Data hold time for CS↑ and WE↑
tDD2
0
—
ns
Note) The load capacitance of the measurement pin is 75pF.
Tw
T1
T2
T3
Address
tULADD2
tADULD2
CS, WE
tCWULD2
tULCWD2
tWUL2
UWR, UB,
LWR, LB
RD
tDD2
tDULD2
D15 to D0
Valid
Fig. 7. 3-cycle Access Basic Timing in Write Operation
– 40 –
CXR704060
• 2-cycle access AC characteristics parameter in read operation
(Topr = –20 to +70°C, DVDD = 1.1 to 1.3V, VDIO = 2.7 to 3.3V, DVSS = 0V reference)
Item
Symbol
Min.
Max.
Unit
Address, CS and WE setup time for UWR (UB) and LWR (LB) ↓
tADULD3
1/2fSRC – 5
—
ns
UWR (UB) and LWR (LB) low pulse width
tWUL3
1/fSRC
—
ns
Address, CS and WE hold time for UWR (UB), LWR (LB) ↓ and RD↓
tULADD3
1/2fSRC – 5
—
ns
Data setup time for UWR (UB), LWR (LB) ↑ and RD↑
tRDS1
1/2fSRC + 23
—
ns
Data hold time for UWR (UB), LWR (LB) ↑ and RD↑
tRDH1
0
—
ns
Note) The load capacitance of the measurement pin is 75pF.
T1
T2
Address
CS, WE
tADULD3
tWUL3
tULADD3
UWR, UB,
LWR, LB, RD
tRDS1
D15 to D0
tRDH1
Valid data in
Fig. 8. 2-cycle Access Basic Timing in Read Operation
– 41 –
CXR704060
• 3-cycle access AC characteristics parameter in read operation
(Topr = –20 to +70°C, DVDD = 1.1 to 1.3V, VDIO = 2.7 to 3.3V, DVSS = 0V reference)
Item
Symbol
Min.
Max.
Unit
—
ns
—
ns
Address, CS and WE setup time for UWR (UB), LWR (LB) ↓ and RD↓
tADULD4 1/fSRC – 5
UWR (UB) and LWR (LB) low pulse width
tWUL4
Address, CS and WE hold time for UWR (UB), LWR (LB) ↓ and RD↓
tULADD4 1/fSRC – 5
—
ns
Data setup time for UWR (UB), LWR (LB) ↑ and RD↑
tRDS2
24
—
ns
Data hold time for UWR (UB), LWR (LB) ↑ and RD↑
tRDH2
0
—
ns
Note) The load capacitance of the measurement pin is 75pF.
T1
T2
T3
Address
CS, WE
tWUL4
tADULD4
tULADD4
UWR, UB,
LWR, LB, RD
tRDS2
D15 to D0
tRDH2
Valid data in
Fig. 9. 3-cycle Access Basic Timing in Read Operation
– 42 –
1/fSRC
CXR704060
7) A/D converter characteristics
(Topr = –20 to +70°C, DVDD = 1.1 to 1.3V, AVDAD = 2.2 to 3.0V, DVss = 0V, AVSAD = 0V reference)
Item
Symbol
Pins
Min.
Typ.
Max.
Unit
Resolution
—
—
—
10
Bits
Absolute error
—
—
—
±7
LSB
Differential linearity error
—
—
—
±1
LSB
Integral linearity error
—
—
—
±3
LSB
Conversion time
tCONV
—
19/fPS4
—
20/fPS4
µs
Sampling time
tSAMP
—
—
3/fPS4
—
µs
Analog input voltage
VIAN
0
—
AVDAD
V
AN0 to AN7
Note) fPS4 is fSRC/16 [MHz] relative to the main oscillation circuit output fSRC.
Conversion time indicates the time required from the start of conversion when one channel is selected
until the ADC interrupt request is generated, and also includes the sampling time.
Digital conversion value
Differential linearity error
(Code center interval offset)
3FFh
Digital conversion value
3FEh
Absolute error
A/D conversion
line
A/D conversion
results
Integral linearity error
(Code center offset from AD conversion line)
001h
000h
AVDAD
Analog input voltage
Analog input voltage
Fig. 10. Definition of A/D Converter Terms
– 43 –
CXR704060
Internal DAC Specifications
1) Digital filter characteristics
Pass band
0 [Hz] to 20 [kHz]
Stop band
24.1 to 328.7 [kHz]
Pass band ripple
±0.03 [dB] or less
Stop band attenuation
54 [dB] or more
2) Analog characteristics
Item
(AVDDA = 2.4V, Ta = 25°C)
Min.
Typ.
Max.
Unit
S/N
—
92
—
dB
THD + N
—
0.015
—
%
Dynamic range
—
93
—
dB
Gain difference between channels
Output voltage∗1
—
0.1
0.15
dB or less
—
666.2
—
Vrms
Output load resistor
10
—
—
kΩ or more
Analog filter cutoff frequency
—
90
—
kHz
∗1 The output voltage is approximately 0.8AVDDA [Vp-p].
– 44 –
CXR704060
Package Outline
Unit: mm
208PIN TFLGA
0.20 S A
13.0
PIN 1 INDEX
1.1MAX
0.1 MAX
0.20 S B
0.15
0.20 S
13.0
x4
(0.55)
1.0
(0.55)
1.075
0.65
DETAIL X
A
208– φ0.35 ± 0.05
V
1.075
U
φ0.08 M S AB
T
R
0.325
P
N
M
B
L
K
0.65
J
H
G
1.075
1.0
F
E
D
C
B
A
(0.55)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
1.0
C0.3
(0.55)
0.325
0.975
3-
0.10 S
X
0.975
PACKAGE STRUCTURE
PACKAGE MATERIAL
1.075
ORGANIC SUBSTRATE
SONY CODE
TFLGA-208P-01
TERMINAL TREATMENT NICKEL & GOLD PLATING
EIAJ CODE
P-TFLGA-208-13.0x13.0-0.65
TERMINAL MATERIAL
PACKAGE MASS
JEDEC CODE
– 45 –
COPPER
0.39g
Sony Corporation