ICX080AK
Diagonal 6mm (Type 1/3) CCD Image Sensor for NTSC Color Video Cameras
Description
The ICX080AK is an interline CCD solid-state
image sensor suitable for NTSC color video
cameras. This chip conforms to DV standard SD
mode, and has the optimal number of pixels for
MPEG2 Main level. While achieving a horizontal
resolution of 450 TV lines, the area has been
expanded 33% in both vertical and horizontal
directions, making the chip suitable for electronic
vibration stabilizer and electronic panning/tilting. In
addition, complete 16:9 wide aspect ratio images
are provided with a high picture quality without
requiring vertical interpolation.
High sensitivity and low dark current are achieved
through the adoption of Ye, Cy, Mg and G
complementary color mosaic filters and HAD (HoleAccumulation Diode) sensors.
This chip features a field period readout system
and an electronic shutter with variable chargestorage time.
The package is a 16-pin DIP (Plastic), and both
top and bottom surface reference can be assured at
the same time.
16 pin DIP (Plastic)
AAAAAA
AAAAAA
AAAAAA
AAAAAA
Pin 1
8
V
4
Pin 9
H
12
50
Features
Optical black position
• Supports electronic vibration stabilizer and electronic panning/tilting
(Top View)
(33%/one side)
• Supports electronic zoom
• Supports DV standard SD mode and MPEG2 Main level (13.5MHz)
• Supports 16:9 wide aspect ratio (for both 18MHz and 5fsc)
• Supply voltage: 12V
• Horizontal register and reset gate: 2.7 to 3.6V drive
• No voltage adjustment (Reset gate and substrate bias are not adjusted.)
• High resolution, high sensitivity, low dark current and low smear
• Excellent antiblooming characteristics
• Continuous variable-speed shutter (1/60 to 1/10000s)
• Supports short exit pupil distance (Recommended range: –20 to –100mm)
• Ye, Cy, Mg and G complementary color mosaic filters on chip
• 16-pin high precision plastic package (both top and bottom surface reference possible)
Device Structure
• Interline CCD image sensor
• Image size:
• Total number of pixels:
• Total number of effective pixels:
• Number of effective pixels: 4:3 NTSC:
16:9 18MHz:
16:9 5fsc:
• Chip size:
• Unit cell size:
• Optical black:
• Number of dummy bits:
• Substrate material:
Diagonal 6mm (Type 1/3)
1016 (H) x 674 (V) approx. 680K pixels
962 (H) x 654 (V)
approx. 630K pixels
711 (H) x 485 (V)
approx. 340K pixels
948 (H) x 485 (V)
approx. 460K pixels
942 (H) x 485 (V)
approx. 460K pixels
5.90mm (H) x 4.92mm (V)
5.05µm (H) x 5.55µm (V)
Horizontal (H) direction: Front 4 pixels, rear 50 pixels
Vertical (V) direction:
Front 12 pixels, rear 8 pixels
Horizontal 28
Vertical 1 (even fields only)
Silicon
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E95518D99
ICX080AK
GND
GND
GND
Vφ1
Vφ2
Vφ3
Vφ4
8
7
6
5
4
3
2
1
Vertical Register
VOUT
Block Diagram and Pin Configuration
(Top View)
Cy
Ye
Cy
Mg
G
Mg
Ye
G
Cy
Ye
Cy
Ye
G
Mg
G
Mg
Cy
Ye
Cy
Ye
Mg
G
Mg
G
Note)
Horizontal Register
GND
φSUB
CSUB
Pin Description
Pin No. Symbol
Description
13
14
15
16
Hφ2
12
Hφ1
11
φRG
10
VL
9
VDD
Note)
Pin No. Symbol
: Photo sensor
Description
1
Vφ4
Vertical register transfer clock
9
VDD
Supply voltage
2
Vφ3
Vertical register transfer clock
10
GND
GND
3
Vφ2
Vertical register transfer clock
11
φSUB
4
Vφ1
Vertical register transfer clock
12
CSUB
Substrate clock
Substrate bias ∗1
5
GND
GND
13
VL
Protective transistor bias
6
GND
GND
14
φRG
Reset gate clock
7
GND
GND
15
Hφ1
Horizontal register transfer clock
8
VOUT
Signal output
16
Hφ2
Horizontal register transfer clock
∗1 DC bias is generated within the CCD, so that this pin should be grounded externally through a capacitance
of 0.1µF.
Absolute Maximum Ratings
Item
Against φSUB
Against VL
–40 to +10
V
Vφ1, Vφ3 – φSUB
–50 to +15
V
Vφ2, Vφ4, VL – φSUB
–50 to +0.3
V
Hφ1, Hφ2, GND – φSUB
–40 to +0.3
V
–25 to
V
VDD, VOUT, φRG, CSUB – GND
–0.3 to +18
V
Vφ1, Vφ2, Vφ3, Vφ4 – GND
–10 to +18
V
Hφ1, Hφ2 – GND
–10 to +5
V
Vφ1, Vφ3 – VL
–0.3 to +28
V
Vφ2, Vφ4, Hφ1, Hφ2, GND – VL
–0.3 to +15
V
to +15
V
–5 to +5
V
–13 to +13
V
–30 to +80
°C
–10 to +60
°C
Voltage difference between vertical clock input pins
Between input clock
pins
Unit Remarks
VDD, VOUT, φRG – φSUB
CSUB – φSUB
Against GND
Ratings
Hφ1 – Hφ2
Hφ1, Hφ2 – Vφ4
Storage temperature
Operating temperature
∗2 +24V (Max.) when clock width < 10µs, clock duty factor < 0.1%.
–2–
∗2
ICX080AK
Bias Conditions
Item
Symbol
Min.
Typ.
Max.
Unit
11.64
12.0
∗1
12.36
V
Supply voltage
VDD
Protective transistor bias
VL
Substrate clock
φSUB
∗2
Reset gate clock
φRG
∗2
Remarks
∗1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL
power supply for the V driver should be used.
∗2 Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated
within the CCD.
DC Characteristics
Item
Symbol
Supply current
Min.
Typ.
IDD
Max.
Unit
6.0
Remarks
mA
Clock Voltage Conditions
Item
Readout clock voltage
Vertical transfer clock
voltage
Horizontal transfer
clock voltage
Reset gate clock
voltage
Min.
Typ.
Max.
Unit
Waveform
diagram
VVT
11.64
12.0
12.36
V
1
VVH1, VVH2
–0.05
0
0.05
V
2
VVH3, VVH4
–0.2
0
0.05
V
2
VVL1, VVL2,
VVL3, VVL4
–6.85
–6.5
–6.15
V
2
VVL = (VVL3 + VVL4)/2
VφV
5.95
6.5
6.9
V
2
VφV = VVHn – VVLn (n = 1 to 4)
VVH3 – VVH
–0.25
0.1
V
2
VVH4 – VVH
–0.25
0.1
V
2
VVHH
0.5
V
2
High-level coupling
VVHL
0.5
V
2
High-level coupling
VVLH
0.5
V
2
Low-level coupling
VVLL
0.5
V
2
Low-level coupling
Symbol
Remarks
VVH = (VVH1 + VVH2)/2
VφH
2.7
3.3
3.6
V
3
VHL
–0.05
0
0.05
V
3
VCR
0.5
1.65
V
3
VφRG
2.7
3.3
3.6
V
4
VRGLH – VRGLL
0.4
V
4
Low-level coupling
VRGL – VRGLm
0.5
V
4
Low-level coupling
19.3
V
5
Substrate clock voltage VφSUB
17.3
18.5
–3–
Cross-point voltage
ICX080AK
Clock Equivalent Circuit Constant
Item
Symbol
Min.
Typ.
Max. Unit Remarks
CφV1, CφV3
1000
pF
CφV2, CφV4
560
pF
CφV12, CφV34
470
pF
CφV23, CφV41
390
pF
CφV13
180
pF
CφV24
100
pF
Capacitance between horizontal transfer clock and GND
CφH1, CφH2
62
pF
Capacitance between horizontal transfer clocks
CφHH
62
pF
Capacitance between reset gate clock and GND
CφRG
12
pF
Capacitance between substrate clock and GND
CφSUB
270
pF
Vertical transfer clock series resistor
R1, R2, R3, R4
82
Ω
Vertical transfer clock ground resistor
RGND
15
Ω
Horizontal transfer clock series resistor
RφH
3
Ω
Horizontal transfer clock ground resistor
RH2
30
kΩ
Capacitance between vertical transfer clock and
GND
Capacitance between vertical transfer clocks
Vφ1
Vφ2
CφV12
R1
R2
RφH
RφH
Hφ1
CφV1
CφV41
CφV23
CφV4
Vφ4
CφH1
CφH2
RH2
CφV13
CφV24
R4
Hφ2
CφHH
CφV2
RGND CφV3
CφV34
R3
Vφ3
Vertical transfer clock equivalent circuit
Horizontal transfer clock equivalent circuit
–4–
ICX080AK
Drive Clock Waveform Conditions
(1) Readout clock waveform
100%
90%
II
II
φM
VVT
φM
2
10%
0%
tr
twh
0V
tf
(2) Vertical transfer clock waveform
Vφ1
Vφ3
VVHH
VVH1
VVHH
VVH
VVHL
VVHL
VVH3
VVHL
VVL1
VVH
VVHH
VVHH
VVHL
VVL3
VVLH
VVLH
VVLL
VVLL
VVL
VVL
Vφ2
Vφ4
VVHH
VVHH
VVH
VVH
VVHH
VVHH
VVHL
VVH2 VVHL
VVHL
VVH4
VVL2
VVHL
VVLH
VVLH
VVLL
VVLL
VVL
VVL4
VVH = (VVH1 + VVH2)/2
VVL = (VVL3 + VVL4)/2
VφV = VVHn – VVLn (n = 1 to 4)
–5–
VVL
ICX080AK
(3) Horizontal transfer clock waveform
tr
twh
tf
Hφ2
90%
VCR
VφH
twl
VφH
2
10%
VHL
Hφ1
two
Cross-point voltage for the Hφ1 rising side of the horizontal transfer clocks Hφ1 and Hφ2 waveforms is VCR.
The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two.
(4) Reset gate clock waveform
tr
twh
tf
VRGH
RG waveform
twl
VφRG
Point A
VRGLH
VRGLL
VRGLm
VRGL
VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from
Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and
VRGLL.
VRGL = (VRGLH + VRGLL) /2
Assuming VRGH is the minimum value during the interval twh, then:
VφRG = VRGH – VRGL.
Negative overshoot level during the falling edge of RG is VRGLm.
(5) Substrate clock waveform
100%
90%
φM
φM
2
VφSUB
VSUB
(A bias generated within the CCD)
10%
0%
tr
twh
–6–
tf
ICX080AK
Clock Switching Characteristics
Item
Symbol
VT
Vertical transfer
clock
Vφ1, Vφ2,
Vφ3, Vφ4
Horizontal
transfer clock
Readout clock
twh
twl
tr
tf
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
1.36 1.56
0.5
0.5
µs
During
readout
During
250 ns CXD1267AN
15
used
Hφ1
14 19.5
14 19.5
8.5 14
8.5
14
Hφ2
14 19.5
14 19.5
8.5 14
8.5
14
During
Hφ1
parallel-serial
Hφ2
conversion
5.56
0.01
0.01
5.56
0.01
0.01
37
4
5
During
imaging
Unit Remarks
Reset gate clock φRG
7
10
ns tf ≥ tr – 2ns
µs
ns
During
Substrate clock
φSUB
1.7 3.06
0.5
0.5
µs drain
charge
two
Symbol
Item
Horizontal transfer clock
Hφ1, Hφ2
Min.
Typ.
12
19.5
Max.
Unit
Remarks
ns
Spectral Sensitivity Characteristics (excludes both lens characteristics and light source characteristics)
1.0
Ye
0.8
Cy
Relative Response
G
0.6
0.4
Mg
0.2
0.0
400
450
500
550
Wave Length [nm]
–7–
600
650
700
ICX080AK
Image Sensor Characteristics
Item
(Ta = 25°C)
Symbol
Min.
Typ.
Sensitivity
S
240
300
Saturation signal
Ysat
600
Smear
Sm
Video signal shading
SHy
Unit
Measurement method
mV
1
mV
2
%
3
20
%
4
Zone 0 and I
25
%
4
Zone 0 to II'
∆Sr
10
%
5
∆Sb
10
%
5
Dark signal
Ydt
2
mV
6
Ta = 60°C
Dark signal shading
∆Ydt
1
mV
7
Ta = 60°C,∗1
Flicker Y
Fy
2
%
8
Flicker R-Y
Fcr
5
%
8
Flicker B-Y
Fcb
5
%
8
Line crawl R
Lcr
3
%
9
Line crawl G
Lcg
3
%
9
Line crawl B
Lcb
3
%
9
Line crawl W
Lcw
3
%
9
Uniformity between video
signal channels
Max.
0.009 0.015
Remarks
Ta = 60°C
Lag
Lag
0.5
%
10
∗1 Excludes vertical dark signal shading caused by vertical register high-speed transfer.
Zone Definition of Video Signal Shading
962 (H)
14
14
8
V
10
H
8
H
8
Zone 0, I
Zone II, II'
V
10
654 (V)
6
Ignored region
Effective pixel region
Measurement System
[∗Y]
[∗A]
CCD signal output
Y signal output
LPF1
(3dB down 8MHz)
CCD
C.D.S
AMP
[∗C]
SH
LPF2
S
H
Chroma signal output
(3dB down 1MHz)
Note) Adjust the amplifier gain so that the gain between [∗A] and [∗Y], and between [∗A] and [∗C]
equals 1.
–8–
ICX080AK
Image Sensor Characteristics Measurement Method
Measurement conditions
1)
In the following measurements, the device drive conditions are at the typical values of the bias and clock
voltage conditions.
2)
In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical
black level (OB) is used as the reference for the signal output, which is taken as the value of Y signal
output or chroma signal output of the measurement system.
Color coding of this image sensor & Composition of luminance (Y) and chroma (color difference) signals
Cy
Ye
Cy
Ye
G
Mg
G
Mg
Cy
Ye
Cy
Ye
G
Mg
A1
B
A2
Mg
G
As shown in the left figure, fields are read out. The charge is
mixed by pairs such as A1 and A2 in the A field. (pairs such
as B in the B field)
As a result, the sequence of charges output as signals from
the horizontal shift register (Hreg) is, for line A1, (G + Cy),
(Mg + Ye), (G + Cy), and (Mg + Ye).
Hreg
Color Coding Diagram
These signals are processed to form the Y signal and chroma (color difference) signal. The Y signal is formed
by adding adjacent signals, and the chroma signal is formed by subtracting adjacent signals. In other words,
the approximation:
Y = {(G + Cy) + (Mg + Ye)} x 1/2
= 1/2 {2B + 3G +2R}
is used for the Y signal, and the approximation:
R – Y = {(Mg + Ye) – (G + Cy)}
= {2R – G}
is used for the chroma (color difference) signal. For line A2, the signals output from Hreg in sequence are
(Mg + Cy), (G + Ye), (Mg + Cy), (G + Ye).
The Y signal is formed from these signals as follows:
Y = {(G + Ye) + (Mg + Cy)} x 1/2
= 1/2 {2B + 3G +2R}
This is balanced since it is formed in the same way as for line A1.
In a like manner, the chroma (color difference) signal is approximated as follows:
–(B – Y) = {(G + Ye) – (Mg + Cy)}
= – {2B – G}
In other words, the chroma signal can be retrieved according to the sequence of lines from R – Y and –(B – Y)
in alternation. This is also true for the B field.
–9–
ICX080AK
Definition of standard imaging conditions
1)
Standard imaging condition I:
Use a pattern box (luminance 706cd/m2, color temperature of 3200K halogen source) as a subject.
(Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR
cut filter and image at F5.6. The luminous intensity to the sensor receiving surface at this point is defined
as the standard sensitivity testing luminous intensity.
2)
Standard imaging condition II:
Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles.
Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is
adjusted to the value indicated in each testing item by the lens diaphragm.
3)
Standard imaging condition III:
Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles.
Use a testing standard lens (exit pupil distance –33mm) with CM500S (t = 1.0mm) as an IR cut filter. The
luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm.
1.
Sensitivity
Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of
1/250s, measure the Y signal (Ys) at the center of the screen and substitute the value into the following
formula.
S = Ys x
250
[mV]
60
2.
Saturation signal
Set to standard imaging condition II. After adjusting the luminous intensity to 10 times the intensity with
average value of the Y signal output, 200mV, measure the minimum value of the Y signal.
3.
Smear
Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity
to 500 times the intensity with average value of the Y signal output, 200mV. When the readout clock is
stopped and the charge drain is executed by the electronic shutter at the respective H blankings,
measure the maximum value YSm [mV] of the Y signal output and substitute the value into the following
formula.
Sm =
4.
1
YSm
1
x
x
x 100 [%] (1/10V method conversion value)
10
200
500
Video signal shading
Set to standard imaging condition III. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity
so that the average value of the Y signal output is 200mV. Then measure the maximum (Ymax [mV]) and
minimum (Ymin [mV]) values of the Y signal and substitute the values into the following formula.
SHy = (Ymax – Ymin)/200 x 100 [%]
5.
Uniformity between video signal channels
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y
signal output is 200mV, and then measure the maximum (Crmax, Cbmax [mV]) and minimum (Crmin,
Cbmin [mV]) values of the R – Y and B – Y channels of the chroma signal and substitute the values into
the following formula.
∆Sr = | (Crmax – Crmin)/200 | x 100 [%]
∆Sb = | (Cbmax – Cbmin)/200 | x 100 [%]
– 10 –
ICX080AK
6.
Dark signal
Measure the average value of the Y signal output (Ydt [mV]) with the device ambient temperature 60°C
and the device in the light-obstructed state, using the horizontal idle transfer level as a reference.
7.
Dark signal shading
After measuring 6, measure the maximum (Ydmax [mV]) and minimum (Ydmin [mV]) values of the Y
signal output and substitute the values into the following formula.
∆Ydt = Ydmax – Ydmin [mV]
8.
Flicker
1) Fy
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y
signal output is 200mV, and then measure the difference in the signal level between fields (∆Yf [mV]).
Then substitute the value into the following formula.
Fy = (∆Yf/200) x 100 [%]
2) Fcr, Fcb
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y
signal output is 200mV, insert an R and B filter, and then measure both the difference in the signal level
between fields of the chroma signal (∆Cr, ∆Cb) as well as the average value of the chroma signal output
(CAr, CAb). Substitute the values into the following formula.
Fci = (∆Ci/CAi) x 100 [%] (i = r, b)
9.
Line crawls
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y
signal output is 200mV, and then insert a white subject and R, G, and B filters and measure the difference
between Y signal lines for the same field (∆Ylw, ∆Ylr, ∆Ylg, ∆Ylb [mV]). Substitute the values into the
following formula.
Lci = (∆Yli/200) x 100 [%] (i = w, r, g, b)
10. Lag
Adjust the Y signal output value generated by strobe light to 200mV. After setting the strobe light so that it
strobes with the following timing, measure the residual signal (Ylag). Substitute the value into the
following formula.
Lag = (Ylag/200) x 100 [%]
VD
Light
Strobe light timing
Y signal output 200mV
Output
– 11 –
Ylag (lag)
7
8
9
10
XV3
XSG2
XV4
φRG
Hφ1
Hφ2
6
XV1
5
XV2
XSG1
4
CXD1267AN
11
12
13
14
15
16
17
18
1/35V
22/16V
1
2
3
4
5
6
ICX080
(BOTTOM VIEW)
8
7
9
16 15 14 13 12 11 10
Vφ4
Hφ2
3
Vφ3
Hφ1
XSUB
22/20V
100k
Vφ2
0.1 3.3/16V
φRG
19
GND
0.1 2200p
CSUB
2
Vφ1
VL
20
GND
GND
1
VOUT
12V
GND
φSUB
– 12 –
VDD
Drive Circuit
1M
0.1
3.3/20V
0.01
1.8k
47
2SK1875
CCD OUT
–6.5V
ICX080AK
– 13 –
OB
CLP
CCD
OUT
V4
V3
V2
V1
HD
BLK
VD
FLD
520
246 stages
#2m + 492
c
15
10
#2n + 5
#2n + 4
n + 6 stages (n = 0 to 192)
b
525
1
2
3
4
5
#2m + 491
a
Drive Timing Chart (Vertical Sync)
275
270
265
260
#2n + 491
#2n + 490
280
#2m + 4
#2m + 3
246 stages m + 6stages (m = 0 to 192)
d
ICX080AK
20
0
– 14 –
SUB
V4
V3
V2
V1
H1
7
7
7
7
7
#n + 5
7
Drive Timing Chart (Vertical Sync “c” Enlarged)
SUB
V4
V3
V2
V1
H1
Drive Timing Chart (Vertical Sync “a” Enlarged)
7
7
#1
7
7
7
7
7
7
#2
7
7
#n + 6
(n = 0 to 192)
Note
7
7
7
7
Note
35
Note) Shutter pulse should be synchronized with Vφ.
≥ 500ns
ICX080AK
0
– 15 –
V4
V3
V2
V1
Drive Timing Chart
(Vertical Sync “d”
Enlarged)
V4
V3
V2
V1
H1
#245
#246
7 7 7 7
≥ 5µs
Drive Timing Chart (Vertical Sync “b” Enlarged)
175
182
182
175
203
203
203
203
203
203
231
224
217
217
231
224
245
252
245
252
≥ 5µs
427
#1
7 7 7 7 7 7 7 7
420
413
406
399
392
385
378
371
364
357
350
343
#13
ICX080AK
– 16 –
OB
CLP
SUB
V4
V3
V2
V1
RG
Effective region for 5fsc
Effective region for 18MHz
H2
H1
10
11
962
1
955
Ignored region
–36
Effective OB
0
–5
49
50
0
11
22
33
44
55
66
77
5fsc = 1137.5fh : 93.5
18MHz = 1144fh : 100
Dummy bit
1
28
Ignored region
8
11
Note) 1unit : 55.87ns (5fsc = 1137.5fh)
55.56ns (18MHz = 1144fh)
1
952
Drive Timing Chart (Horizontal Sync)
ICX080AK
ICX080AK
Notes on Handling
1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non-chargeable gloves, clothes or material.
Also use conductive shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensor.
e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.
2) Soldering
a) Make sure the package temperature does not exceed 80°C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W
soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently.
c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering
tool, use a thermal controller of the zero cross On/Off type and connect it to ground.
3) Dust and dirt protection
Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and
dirt. Clean glass plates with the following operation as required, and use them.
a) Perform all assembly operations in a clean room (class 1000 or less).
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should
dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized
air is recommended.)
c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass.
d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when
moving to a room with great temperature differences.
e) When a protective tape is applied before shipping, just before use remove the tape applied for
electrostatic protection. Do not reuse the tape.
4) Installing (attaching)
a) Remain within the following limits when applying a static load to the package. Do not apply any load more
than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited
portions. (This may cause cracks in the package.)
AAAA
AAAA
AAAA AAAA
Cover glass
50N
50N
Plastic package
Compressive strength
AAAA
AAAA
1.2Nm
Torsional strength
b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the
package may fracture, etc., depending on the flatness of the bottom of the package. Therefore, for
installation, use either an elastic load, such as a spring plate, or an adhesive.
– 17 –
ICX080AK
c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated
voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area,
and indicated values should be transferred to the other locations as a precaution.
d) The notch of the package is used for directional index, and that can not be used for reference of fixing.
In addition, the cover glass and seal resin may overlap with the notch of the package.
e) If the lead bend repeatedly and the metal, etc., clash or rub against the package, the dust may be
generated by the fragments of resin.
f) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyanoacrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives. (reference)
5) Others
a) Do not expose to strong light (sun rays) for long periods, color filters will be discolored. When high
luminance objects are imaged with the exposure level control by electronic-iris, the luminance of the
image-plane may become excessive and discolor of the color filter will possibly be accelerated. In such a
case, it is advisable that taking-lens with the automatic-iris and closing of the shutter during the power-off
mode should be properly arranged. For continuous using under cruel condition exceeding the normal
using condition, consult our company.
b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or
usage in such conditions.
c) The brown stain may be seen on the bottom or side of the package. But this does not affect the CCD
characteristics.
– 18 –
– 19 –
1.2
2.5
0.69
~
~
Plastic
GOLD PLATING
42 ALLOY
0.9g
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
0.3
M
1.27
9.2
10.3
12.2 ± 0.1
H
PACKAGE MATERIAL
V
6.1
~
2.5
0.46
0.3
A
1.2
2.5
8.4
(For the first pin only)
0.5
PACKAGE STRUCTURE
B
5.7
D
B'
C
1
8
11.6
16
9
2.5
2-R0.5
9. The notches on the bottom of the package are used only for directional index, they must
not be used for reference of fixing.
8. The thickness of the cover glass is 0.75mm, and the refractive index is 1.5.
7. The tilt of the effective image area relative to the bottom “C” is less than 50µm.
The tilt of the effective image area relative to the top “D” of the cover glass is less than 50µm.
6. The height from the bottom “C” to the effective image area is 1.41 ± 0.10mm.
The height from the top of the cover glass “D” to the effective image area is 1.94 ± 0.15mm.
5. The rotation angle of the effective image area relative to H and V is ± 1°.
4. The center of the effective image area relative to “B” and “B'”
is (H, V) = (6.1, 5.7) ± 0.15mm.
3. The bottom “C” of the package, and the top of the cover glass “D”
are the height reference.
2. The two points “B” of the package are the horizontal reference.
The point “B'” of the package is the vertical reference.
1. “A” is the center of the effective image area.
16pin DIP (450mil)
9.5
11.4 ± 0.1
3.1
Unit: mm
3.35 ± 0.15
1.27
3.5 ± 0.3
0° to 9°
0.25
11.43
Package Outline
ICX080AK