ICX082AL Diagonal 11mm (Type 2/3) CCD Image Sensor for EIA Black-and-White Video Cameras Description The ICX082AL is an interline CCD solid-state image sensor suitable for EIA black-and-white video cameras with a diagonal 11mm (Type 2/3) system. High sensitivity and low dark current are achieved through the adoption of HAD (Hole-Accumulation Diode) sensors. This chip features a field period readout system and an electronic shutter with variable chargestorage time. 20 pin DIP (Ceramic) AAAAAA AAAAAA AAAAAA AAAAAA Pin 1 Features • High sensitivity (+6dB compared with the ICX022BL) • Low smear (–20dB compared with the ICX022BL) • High resolution, Low dark current • Excellent antiblooming characteristics • Continuous variable-speed shutter 2 V 12 3 Pin 11 H 40 Optical black position (Top View) Device Structure • Interline CCD image sensor • Image size: • Number of effective pixels: • Total number of pixels: • Chip size: • Unit cell size: • Optical black: • Number of dummy bits: • Substrate material: Diagonal 11mm (Type 2/3) 768 (H) × 494 (V) approx. 380K pixels 811 (H) × 508 (V) approx. 410K pixels 10.25mm (H) × 8.5mm (V) 11.6µm (H) × 13.5µm (V) Horizontal (H) direction: Front 3 pixels, rear 40 pixels Vertical (V) direction: Front 12 pixels, rear 2 pixels Horizontal 22 Vertical 1 (even fields only) Silicon Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E95935C99 ICX082AL VL 7 GND 9 Vertical Register Block Diagram and Pin Configuration (Top View) Output Unit VDD 10 VOUT 11 VGG 12 Note) 1 Vφ4 2 Vφ3 3 Vφ2 4 SUB 5 GND 6 Vφ1 VSS 13 Horizontal Register GND 14 15 16 17 18 19 20 RD RG VL Hφ1 Hφ2 HIS Note) : Photo sensor Pin Description Pin No. Symbol Description Pin No. Symbol Description 1 Vφ4 Vertical register transfer clock 11 VOUT Signal output 2 Vφ3 Vertical register transfer clock 12 VGG Output amplifier gate bias 3 Vφ2 Vertical register transfer clock 13 VSS Output amplifier source 4 SUB Substrate (overflow drain) 14 GND GND 5 GND GND 15 RD Reset drain 6 Vφ1 Vertical register transfer clock 16 RG Reset gate clock 7 VL Protective transistor bias 17 VL Protective transistor bias 8 NC 18 Hφ1 Horizontal register transfer clock 9 GND GND 19 Hφ2 Horizontal register transfer clock 10 VDD Output amplifier drain power 20 HIS Horizontal register input source bias –2– ICX082AL Absolute Maximum Ratings Item Ratings Unit –0.3 to +55 V HIS, VDD, RD, VOUT, VSS – GND –0.3 to +20 V HIS, VDD, RD, VOUT, VSS – SUB –55 to +10 V Vertical clock input pins – GND –15 to +20 V Vertical clock input pins – SUB to +10 V Voltage difference between vertical clock input pins to +15 V Voltage difference between horizontal clock input pins to +17 V Hφ1, Hφ2 – Vφ4 –17 to +17 V Hφ1, Hφ2, RG, VGG – GND –10 to +15 V Hφ1, Hφ2, RG, VGG – SUB –55 to +10 V VL – SUB –65 to +0.3 V Vφ1, Vφ3, HIS, VDD, RD, VOUT – VL –0.3 to +30 V RG – VL –0.3 to +24 V Vφ2, Vφ4, VGG, VSS, Hφ1, Hφ2 – VL –0.3 to +20 V Storage temperature –30 to +80 °C Operating temperature –10 to +60 °C Substrate voltage SUB – GND Supply voltage Vertical clock input voltage Remarks ∗1 ∗1 +27V (Max.) when clock width < 10µs, clock duty factor < 0.1%. Bias Conditions Symbol Min. Typ. Max. Unit Output amplifier drain voltage VDD 14.7 15.0 15.3 V Reset drain voltage VRD 14.7 15.0 15.3 V Output amplifier gate voltage VGG 3.8 4.2 4.6 V Output amplifier source VSS Substrate voltage adjustment range VSUB 9 19 V Substrate voltage adjustment precision ∆VSUB –3 +3 % Reset gate clock voltage adjustment range VRGL 0 3.0 V Reset gate clock voltage adjustment precision ∆VRGL –3 +3 % Protective transistor bias VL –11 –10.5 –10 V ∗3 Horizontal register input source bias VHIS 14.7 15.0 15.3 V VHIS = VDD Item –3– Grounded with 750Ω resistor Remarks VRD = VDD ±5% ∗2 ∗2 ICX082AL DC Characteristics Item Symbol Min. Typ. Max. Remarks Unit Output amplifier drain current IDD Input current IIN1 1 µA ∗4 Input current IIN2 10 µA ∗5 mA 6 ∗2 Indications of substrate voltage (VSUB) and reset gate clock voltage (VRGL) setting value The setting value of the substrate voltage and reset gate clock voltage are indicated on the back of the image sensor by a special code. Adjust the substrate voltage (VSUB) and reset gate clock voltage (VRGL) to the indicated voltage. The adjustment precision is ±3%. VSUB code — one character indication VRGL code — one character indication ↑ ↑ VRGL code VSUB code "Code" and optimal setting correspond to each other as follows. VRGL code 1 Optimal setting 0 VSUB code D 2 3 4 5 6 7 0.5 1.0 1.5 2.0 2.5 3.0 E f G h J K L m N P Q R S T U V W X Y Z Optimal setting 9.0 9.5 10.010.511.011.512.0 12.513.013.514.014.515.015.516.016.517.017.518.018.519.0 <Example> "5K" → VRGL = 2.0V VSUB = 12.0V ∗3 This must no exceed the VVL voltage of the vertical clock waveform. ∗4 1) Current to each pin when 20V is applied to VDD, RD, VOUT, VSS, HIS and SUB pins, while pins that are not tested are grounded. 2) Current to each pin when 20V is applied sequentially to Vφ1, Vφ2, Vφ3 and Vφ4 pins, while pins that are not tested are grounded. However, 20V is applied to SUB pin. 3) Current to each pin when 15V is applied sequentially to Hφ1, Hφ2, RG and VGG pins, while pins that are not tested are grounded. However, 15V is applied to SUB pin. 4) Current to VL pin when 30V is applied to Vφ1, Vφ3, HIS, VDD, RD and VOUT pins or when, 24V is applied to RG pin or when, 20V is applied to Vφ2, Vφ4, VGG, VSS, Hφ1 and Hφ2 pins, while VL pin is grounded. However, GND and SUB pins are left open. ∗5 Current to SUB pin when 55V is applied to SUB pin, while pins that are not tested are grounded. –4– ICX082AL Clock Voltage Conditions Min. Typ. Max. Unit Waveform diagram VVT 14.5 15.0 15.5 V 1 VVH1, VVH2, VVH3, VVH4 –0.6 0 V 2 VVH = (VVH1 + VVH2)/2 V 2 VVL = (VVL3 + VVL4)/2 V 2 VφV = VVHn – VVLn (n = 1 to 4) 0.2 V 2 Item Readout clock voltage Symbol VVL1, VVL2, VVL3, VVL4 VφV Vertical transfer clock voltage –9.6 8.9 | VVH1 – VVH2 | Remarks VVH3 – VVH –0.5 0 V 2 VVH4 – VVH –0.5 0 V 2 VVHH 0.8 V 2 High-level coupling VVHL 1.0 V 2 High-level coupling VVLH 0.8 V 2 Low-level coupling VVLL 0.8 V 2 Low-level coupling Horizontal transfer clock voltage VφH 6.0 8.0 V 3 VHL –3.5 –3.0 V 3 Reset gate clock voltage VφRG 6.0 13.0 V 3 VRGL 0 3.0 V 3 27.0 32.0 V 4 Substrate clock voltage VφSUB ∗1 ∗1 The reset gate clock voltage need not be adjusted when the reset gate clock is driven when the specifications are as given below. In this case, the reset gate clock voltage setting indicated on the back of the image sensor has not significance. Item Reset gate clock voltage Min. Typ. Max. Unit Waveform diagram VRGL –0.2 0 0.2 V 3 VφRG 8.5 9.0 9.5 V 3 Symbol –5– Remarks ICX082AL Clock Equivalent Circuit Constant Item Symbol Min. Typ. Max. Unit Remarks CφV1, CφV3 2700 pF CφV2, CφV4 2700 pF CφV12, CφV34 2100 pF CφV23, CφV41 900 pF CφV13 1000 pF CφV24 500 pF Capacitance between horizontal transfer clock and GND CφH1, CφH2 47 pF Capacitance between horizontal transfer clocks CφHH 58 pF Capacitance between reset gate clock and GND CφRG 7 pF Capacitance between substrate clock and GND CφSUB 800 pF Vertical transfer clock series resistor R1, R2, R3, R4 22 Ω Vertical transfer clock ground resistor RGND 3 Ω Horizontal transfer clock series resistor RφH 10 Ω Capacitance between vertical transfer clock and GND Capacitance between vertical transfer clocks Vφ2 Vφ1 CφV12 R1 R2 RφH RφH Hφ1 CφV1 CφV41 CφV24 R4 Vφ4 Hφ2 CφHH CφV2 CφV23 CφH1 CφH2 CφV13 CφV4 RGND CφV3 CφV34 R3 Vφ3 Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit –6– ICX082AL Drive Clock Waveform Conditions (1) Readout clock waveform 100% 90% II II φM VVT 10% 0% tr φM 2 twh 0V tf (2) Vertical transfer clock waveform Vφ1 Vφ3 VVHH VVH1 VVHH VVH VVHH VVHL VVHL VVHL VVHL VVL1 VVH VVHH VVH3 VVL3 VVLH VVLH VVLL VVLL VVL VVL Vφ2 Vφ4 VVHH VVHH VVH VVH VVHH VVHH VVHL VVHL VVH2 VVHL VVH4 VVL2 VVHL VVLH VVLH VVLL VVLL VVL VVL4 VVH = (VVH1 + VVH2)/2 VVL = (VVL3 + VVL4)/2 VφV = VVHn – VVLn (n = 1 to 4) –7– VVL ICX082AL (3) Horizontal transfer clock waveform · Reset gate clock waveform tr twh tf 90% twl VφH, VφRG 10% VHL, VRGL (4) Substrate clock waveform 100% 90% φM VφSUB VSUB 10% 0% tr twh φM 2 tf Clock Switching Characteristics Item Readout clock Symbol VT twh 2.3 2.5 tf 0.5 µs µs 0.74 0.1 0.1 1.3 62.1 0.1 0.1 Hφ 20 20 15 Hφ1 5.38 φRG Substrate clock φSUB 11 13 Unit 0.5 62.6 Hφ2 Reset gate clock tr Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Vertical transfer Vφ1, Vφ2 clock Vφ3, Vφ4 Horizontal transfer clock twl 19 15 Remarks During readout During µs imaging 19 ns During imaging 0.01 0.01 5.38 0.01 0.01 µs During parallel-serial µs conversion 51 2.0 2.0 ns 1.5 1.8 0.5 –8– 0.5 µs During drain charge ICX082AL Image Sensor Characteristics (Ta = 25°C) Unit Measurement method mV 1 mV 2 % 3 25 % 4 Vdt 2 mV 5 Ta = 60°C Dark signal shading ∆Vdt 1 mV 6 Ta = 60°C Flicker F 5 % 7 Lag Lag 0.5 % 8 Symbol Min. Typ. Sensitivity S 500 700 Saturation signal Vsat 800 Smear Sm Video signal shading SH Dark signal Item Max. 0.0001 0.0003 Remarks Ta = 60°C Image Sensor Characteristics Measurement Method Measurement conditions 1) In the following measurements, the substrate voltage and the reget gate clock voltage are set to the values indicated on the device, and the device drive conditions are at the typical values of the bias and clock voltage conditions. 2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical black (OB) level is used as the reference for the signal output, and the value measured at point [*A] in the drive circuit example is used. Definition of standard imaging conditions 1) Standard imaging condition I: Use a pattern box (luminance 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.00mm) as an IR cut filter and image at F8. The luminous intensity to the sensor receiving surface at this point is defined as the standard sensitivity luminous intensity. 2) Standard imaging condition II : Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles. Use a testing standard lens with CM500S (t = 1.00mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm. 1. Sensitivity Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of 1/250s, measure the signal output (Vs) at the center of the screen and substitute the value into the following formula. S = Vs × 250 [mV] 60 2. Saturation signal Set to standard imaging condition II. After adjusting the luminous intensity to 10 times the intensity with average value of signal output, 350mV, measure the minimum value of the signal output. –9– ICX082AL 3. Smear Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity to 500 times the intensity with average value of the signal output, 350mV. When the readout clock is stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum value VSm [mV] of the signal output and substitute the value into the following formula. Sm = 1 VSm 1 × × × 100 [%] (1/10V method conversion value) 10 350 500 4. Video signal shading Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so that the average value of the signal output is 350mV. Then measure the maximum (Vmax [mV]) and minimum (Vmin [mV]) values of the signal output and substitute the values into the following formula. SH = (Vmax – Vmin)/350 × 100 [%] 5. Dark signal Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature 60°C and the device in the light-obstructed state, using the horizontal idle transfer level as a reference. 6. Dark signal shading After measuring 5, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark signal output and substitute the values into the following formula. ∆Vdt = Vdmax – Vdmin [mV] 7. Flicker Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the signal output is 350mV, and then measure the difference in the signal level between fields (∆Vf [mV]). Then substitute the value into the following formula. F = (∆Vf/350) × 100 [%] 8. Lag Adjust the signal output value generated by strobe light to 350mV. After setting the strobe light so that it strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the following formula. Lag = (Vlag/350) × 100 [%] FLD V1 Light Strobe light timing Signal output 350mV Output – 10 – Vlag (lag) 6V RG H1 H2 –11V XV3 XSG2 XV4 XV2 XSG1 XV1 2.2/16V 0.1 11 10 13 8 74AC04 12 9 6 5 0.1 0.1 15 16 CXD1268M 0.1 14 7 0.1 3.3/25V 18 3 1/16V 17 4 19 2 33k 100k 91k 20 1 100k 0.01 10 10 47k 0.1 3.3/ 16V 10k 3 18 4 2200P 5 1M 6 22k 1000P 33k 0.01 10k 7 10/10V 100k 17 16 15 3.3k 100 3.3/16V 100k 750 14 9 10 39k 3.3/ 16V 11 12 8 3.3/35V 13 15 15 ICX082AL (BOTTOM VIEW) 19 2 20 1 Vφ4 HIS 22/20V Vφ3 Hφ2 5V 27k 47k 15k 39k Vφ2 Hφ1 –9V 3.3/ 35V SUB VL 15k GND RG 270k Vφ1 RD 56k VL GND XSUB NC VSS 15V GND VGG 30V VDD – 11 – VOUT Drive Circuit 0.01 CCD OUT [∗A] 3.3/16V 3.3/25V ICX082AL ICX082AL Spectral Sensitivity Characteristics (includes lens characteristics, excludes light source characteristics) 1.0 0.9 0.8 Relative Response 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 400 500 600 700 800 900 1000 Wave Length [nm] Sensor Readout Clock Timing Chart V1 2.5 V2 Odd Field V3 V4 33.5 1.6 2.5 2.5 2.5 0.2 V1 V2 Even Field V3 V4 Unit : µs – 12 – – 13 – CCD OUT V4 V3 V2 V1 HD BLK VD FLD 493 494 525 1 2 3 4 5 520 Drive Timing Chart (Vertical Sync) 10 2 4 6 1 3 5 15 2 4 6 1 3 5 265 494 493 1 3 5 2 4 6 280 1 3 5 2 4 6 ICX082AL 275 270 260 20 – 14 – SUB V4 V3 V2 V1 RG H2 H1 BLK HD 30 20 10 768 1 2 3 5 760 Drive Timing Chart (Horizontal Sync) ICX082AL 20 10 20 22 1 2 3 1 2 3 10 1 2 3 5 40 ICX082AL Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges. 2) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering tool, use a thermal controller of the zero cross On/Off type and connect it to ground. 3) Dust and dirt protection Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and dirt. Clean glass plates with the following operation as required, and use them. a) Operate in clean environments (around class 1000 is appropriate). b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. e) When a protective tape is applied before shipping, just before use remove the tape applied for electrostatic protection. Do not reuse the tape. 4) Do not expose to strong light (sun rays) for long periods. For continuous using under cruel condition exceeding the normal using condition, consult our company. 5) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to too much mechanical shocks. – 15 – + 0.25 2-φ2.50 0 V H A 11 2R3 .0 ~ 8. Planar orientation of the effective image area relative to the bottom “D” is less than 60µm. 9. The thickness of the cover glass is 0.75mm and the refractive index is 1.5. GOLD PLATING 42 ALLOY 5.9g LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT 7. The height from the bottom “D” to the effective image area is 1.46 ± 0.15mm. 6. The angle of rotation relative to the reference line “B” is less than ± 1°. 5. The center of the effective image area, specified relative to the reference hole is (H, V) = (13.15, 5.0) ± 0.15mm. 4. The bottom “D” is the height reference. (Two points are specified.) 3. A straight line “C” which passes through the center of the reference hole at right angles to vertical reference line “B” is the reference axis of horizontal direction. 2. A straight line “B” which passes through the centers of the reference hole and the elongated hole is the reference axis of vertical direction. Ceramic M ~ 1. “A” is the center of the effective image sensor area. + 0.15 2.00 0 × 2.5 (Elongated Hole) D 26.0 PACKAGE MATERIAL 0.3 0.46 1.27 1 13.15 0.5 10 26.00 ± 0.25 20 PACKAGE STRUCTURE 2.54 1Pin Index B + 0.15 φ2.00 0 (Reference Hole) 0.35 5.0 31.0 ± 0.4 27.0 ± 0.3 0.25 C 3.2 ± 0.3 0° to 9° 20pin DIP (800mil) 20.32 Unit: mm 20.2 ± 0.3 1.0 – 16 – 5.5 ± 0.2 (AT STAND OFF) Package Outline ICX082AL