SONY ICX075AL

ICX075AL
Diagonal 8mm (Type 1/2) Progressive Scan CCD Image Sensor with Square Pixel for CCIR B/W Video Cameras
Description
The ICX075AL is an interline CCD solid-state
image sensor suitable for CCIR black-and-white
video cameras. Progressive scan allows all pixels
signals to be output independently within
approximately 1/50 second. This chip features an
electronic shutter with variable charge-storage time
which makes it possible to realize full-frame still
image without mechanical shutter. Individual pixels
in a square matrix make this device suitable for
image input and processing applications.
High sensitivity and low dark current are achieved
through the adoption of HAD (Hole-Accumulation
Diode) sensors.
22 pin DIP (Cer-DIP)
Pin 1
• Number of dummy bits:
• Substrate material:
2
V
Features
• Progressive scan allows individual readout of the
image signals from all pixels.
• High vertical resolution (580TV-lines) still picture
without mechanical shutter.
• Square pixel unit cell
• High resolution, high sensitivity, low dark current
• Continuous variable-speed shutter
• Low smear
• Excellent antiblooming characteristics
• Reset gate: 5V drive (bias: no adjustment)
Device Structure
• Image size:
• Number of effective pixels:
• Total number of pixels:
• Interline CCD image sensor
• Chip size:
• Unit cell size:
• Optical black:
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
3
Pin 12
H
8
38
Optical black position
(Top View)
Diagonal 8mm (Type 1/2)
782 (H) × 582 (V)
approx. 460K pixels
823 (H) × 592 (V)
approx. 490K pixels
8.10mm (H) × 6.33mm (V)
8.3µm (H) × 8.3µm (V)
Horizontal (H) direction: Front 3 pixels, rear 38 pixels
Vertical (V) direction:
Front 8 pixels, rear 2 pixels
Horizontal 19
Vertical 5
Silicon
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E95309F99
ICX075AL
CGG2
VOUT1
CGG1
GND
VHOLDφ
Vφ1
Vφ2
Vφ3
HIS
HIGφ1
11
10
9
8
7
6
5
4
3
2
1
Vertical Register
VOUT2
Block Diagram and Pin Configuration
(Top View)
Note)
Note)
Horizontal Register 1
: Photo sensor
17
RG
VL
SUB
Hφ1
Hφ2
18
19
20
21
22
VOGφ
16
POGφ
15
HIG2
14
HHGφ2
13
HHGφ1
12
VDD
Horizontal Register 2
Pin Description
Pin No. Symbol
Description
Pin No. Symbol
Description
HIGφ1
Test pin ∗2
12
VDD
Supply voltage
2
HIS
Test pin ∗2
13
RG
Reset gate clock
3
Vφ3
Vertical register transfer clock
14
VL
Protective transistor bias
4
Vφ2
Vertical register transfer clock
15
SUB
Substrate (overflow drain)
5
Vφ1
Vertical register transfer clock
16
Hφ1
Horizontal register transfer clock
6
VHOLDφ
Vertical register final stage
accumulation clock
17
Hφ2
Horizontal register transfer clock
7
GND
GND
18
HHGφ1
Inter-horizontal register transfer clock
8
CGG1
Output amplifier 1 gate ∗1
decoupling capacitor
19
HHGφ2
Inter-horizontal register transfer clock
9
VOUT1
Signal output 1
20
HIG2
Test pin ∗2
10
CGG2
Output amplifier 2 gate ∗1
decoupling capacitor
21
POGφ
Test pin ∗2
11
VOUT2
Signal output 2
22
VOGφ
Vertical register final stage
transfer clock
1
∗1 DC bias is applied within the CCD, so that this pin should be grounded externally through a capacitance of
1µF or more.
∗2 Regarding the test pins: apply the same voltage as the supply voltage to HIS, and ground HIGφ1, HIG2, and
POGφ.
–2–
ICX075AL
Absolute Maximum Ratings
Item
Ratings
Substrate voltage SUB – GND
Unit Remarks
–0.3 to +55
V
VDD, VOUT1, VOUT2, HIS, CGG1, CGG2 – GND
–0.3 to +18
V
VDD, VOUT1, VOUT2, HIS, CGG1, CGG2 – SUB
–55 to +10
V
Vφ1, Vφ2, Vφ3, VHOLDφ, VOGφ – GND
–15 to +20
V
Vφ1, Vφ2, Vφ3, VHOLDφ, VOGφ – SUB
to +10
V
Voltage difference between vertical clock input pins
to +15
V
Voltage difference between horizontal clock input pins
to +17
V
Hφ1, Hφ2 – VOGφ
–17 to +17
V
Hφ1, Hφ2 – GND
–10 to +15
V
Hφ1, Hφ2 – SUB
–55 to +10
V
VL – SUB
–65 to +0.3
V
Vφ2, Vφ3, VDD, VOUT1, VOUT2, HIS, HIGφ1, HIG2, POGφ – VL
–0.3 to +27.5
V
RG – GND
–0.3 to +22.5
V
Vφ1, CGG1, CGG2, Hφ1, Hφ2, HHGφ1, HHGφ2, VOGφ, VHOLDφ – VL
–0.3 to +17.5
V
Storage temperature
–30 to +80
°C
Operating temperature
–10 to +60
°C
Supply voltage
Clock input voltage
∗1 +27V (Max.) when clock width < 10µs, clock duty factor < 0.1%.
–3–
∗1
ICX075AL
Bias Conditions
Item
Symbol
Min.
Typ.
Max.
15.0
15.45
V
18.5
V
Indicated
voltage + 0.1
V
Supply voltage
VDD
14.55
Substrate voltage
adjustment range
VSUB
9.0
Indicated
voltage – 0.1
Substrate voltage
adjustment precision
Protective transistor bias
Indicated
voltage
∗2
VL
Unit Remarks
∗1
DC Characteristics
Item
Symbol
Min.
Typ.
Max.
Unit
10
Remarks
Supply current
IDD
mA
Input current
IIN1
1
µA
∗3
Input current
IIN2
10
µA
∗4
∗1 Indications of substrate voltage (VSUB) setting value
The setting value of the substrate voltage is indicated on the back of image sensor by a special code.
Adjust the substrate voltage (VSUB) to the indicated voltage.
VSUB code – two characters indication
↑
Integer portion
↑
Decimal portion
The integer portion of the code and the actual value correspond to each other as follows.
Integer portion of code
9
A
Value
9
10 11 12 13 14 15 16 17 18
C
d
E
f
G
h
J
K
<Example> "A5" → VSUB = 10.5V
∗2 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL
power supply for the V driver should be used.
∗3 (1) Current to each pin when 18V is applied to VDD, VOUT1, VOUT2, HIS, RG, CGG1, CGG2, GND and SUB
pins, while pins that are not tested are grounded.
(2) Current to each pin when 20V is applied sequentially to Vφ1, Vφ2 and Vφ3 pins, while pins that are not
tested are grounded. However, 20V is applied to SUB pin.
(3) Current to each pin when 15V is applied sequentially to RG, Hφ1 and Hφ2 pins, while pins that are not
tested are grounded. However, 15V is applied to SUB pin.
(4) Current to VL pin when 25V is applied to Vφ2, Vφ3, POGφ, HIGφ1, HIG2, VDD, VOUT1 and VOUT2 pins or
when, 15V is applied to Vφ1, VHOLDφ, VOGφ, CGG1, CGG2, Hφ1, Hφ2, HHGφ1 and HHGφ2 pins, while VL
pin is grounded. However, GND and SUB pins are left open.
(5) Current to GND pin when 20V is applied to the RG pin and the GND pin is grounded.
∗4 Current to SUB pin when 55V is applied to SUB pin, while all pins that are not tested are grounded.
–4–
ICX075AL
Clock Voltage Conditions
Symbol
Item
Readout clock voltage
Vertical transfer clock
voltage
Min. Typ. Max. Unit
Waveform
diagram
Remarks
VVT
14.55 15.0 15.45
V
1
VVH02
–0.05
0
0.05
V
2
VVH1, VVH2, VVH3
–0.2
0
0.05
V
2
VVL1, VVL2, VVL3
–8.0 –7.5 –7.0
V
2
VVL = (VVL01 + VVL03)/2
VφV
6.8
8.05
V
2
VφV = VVHn – VVLn (n = 1 to 3)
| VVL1 – VVL3 |
0.1
V
2
VVHH
0.5
V
2
High-level coupling
VVHL
0.5
V
2
High-level coupling
VVLH
0.5
V
2
Low-level coupling
VVLL
0.5
V
2
Low-level coupling
7.5
VVH = VVH02
VφH
4.75
5.0
5.25
V
3
VHL
–0.05
0
0.05
V
3
4.5
5.0
5.5
V
4
Input through 0.01µF
capacitance
0.8
V
4
Low-level coupling
VDD VDD VDD
+ 0.4 + 0.6 + 0.8
V
4
Substrate clock voltage VφSUB
21.5 22.5 23.5
V
5
Vertical final stage
VVHOLDH, VVOGH
accumulation clock
voltage
VVHOLDL, VVOGL
/transfer clock voltage
–0.05
0.05
V
6
–8.0 –7.5 –7.0
V
6
VHHG1H, VHHG2H
Inter-horizontal register
VHHG1L, VHHG2L
transfer clock voltage
VHHG1M, VHHG2M
4.75
5.25
V
7
–8.0 –7.5 –7.0
V
7
–0.05
V
7
Horizontal transfer
clock voltage
VφRG
Reset gate clock
voltage
VRGLH – VRGLL
VRGH
0
5.0
0
–5–
0.05
ICX075AL
Clock Equivalent Circuit Constant
Item
Symbol
Capacitance between vertical transfer clock and GND
Capacitance between vertical transfer clocks
Min.
Typ.
Max.
Unit Remarks
CφV1
820
pF
CφV2
820
pF
CφV3
820
pF
CφV12
3300
pF
CφV23
2200
pF
CφV31
2200
pF
Capacitance between vertical final stage accumulation
clock and GND
CφVHOLD
19
pF
Capacitance between vertical final stage transfer clock
and GND
CφVOG
12
pF
Capacitance between inter-horizontal register transfer
clock and GND
CφHHG1
19
pF
CφHHG2
19
pF
Capacitance between horizontal transfer clock and
GND
CφH1
68
pF
CφH2
68
pF
Capacitance between horizontal transfer clocks
CφHH
47
pF
Capacitance between reset gate clock and GND
CφRG
10
pF
Capacitance between substrate clock and GND
CφSUB
400
pF
Vertical transfer clock series resistor
R1, R2, R3
22
Ω
Vertical transfer clock ground resistor
RGND
15
Ω
RφH1
24
Ω
RφH2
24
Ω
Horizontal transfer clock series resistor
Vφ1
R1
CφV12
CφV1
R2
Vφ2
CφV2
RφH1
Cφv31
RφH2
Hφ1
RGND
Hφ2
CφHH
CφV3
Cφv23
CφH1
CφH2
R3
Vφ3
Vertical transfer clock equivalent circuit
Horizontal transfer clock equivalent circuit
–6–
ICX075AL
Drive Clock Waveform Conditions
(1) Readout clock waveform
100%
90%
II
II
φM
VVT
φM
2
10%
0%
tr
twh
0V
tf
(2) Vertical transfer clock waveform
Vφ1
VVH1
VVH1
VVHH
VVHH
VVH
VVHL
VVHL
VVLH
VVL01
VVLH
VVL1
VVLL
Vφ2
VVH02
VVL
VVL1
VVLL
VVH2
VVHH
VVH2
VVHH
VVHL
VVH
VVHL
VVLH
VVLH
VVL2
VVL2
VVLL
Vφ3
VVL
VVLL
VVH3
VVH3
VVHH
VVHL
VVHH
VVH
VVHL
VVLH
VVL03
VVLH
VVLL
VVL3
VVL
VVLL
VφV1 = VVH1 – VVL01
VφV2 = VVH02 – VVL2
VφV3 = VVH3 – VVL03
VVH = VVH02
VVL = (VVL01 + VVL03)/2
–7–
ICX075AL
(3) Horizontal transfer clock waveform
tr
twh
tf
90%
twl
VφH
10%
VHL
(4) Reset gate clock waveform
tr
twh
tf
VRGH
twl
RG waveform
Point A
VφRG
VRGL + 0.5V
VRGLH
VRGL
VRGLL
Hφ1 waveform
2.5V
VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from
Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and
VRGLL.
VRGL = (VRGLH + VRGLL)/2
Assuming VRGH is the minimum value during the interval twh, then:
VφRG = VRGH – VRGL
(5) Substrate clock waveform
100%
90%
φM
VφSUB
VSUB
10%
0%
tr
twh
–8–
φM
2
tf
ICX075AL
(6) Vertical final stage accumulation clock waveform · Vertical final stage transfer clock waveform
VHOLDφ, VOGφ
tr
tf
VVHOLDH, VVOGH
90%
10%
VVHOLDL, VVOGL
(7) Inter-horizontal register transfer clock waveform
HHGφ1, HHGφ2
tr
tf1
VHHG1H, VHHG2H
90%
90%
tf2
10%
VHHG1M, VHHG2M
90%
10%
10%
VHHG1L, VHHG2L
–9–
ICX075AL
Clock Switching Characteristics
Item
Symbol
VT
Vertical transfer
clock
Vφ1,
Vφ2, Vφ3
Horizontal
transfer clock
Readout clock
During imaging
twh
twl
tr
tf, tf1, tf2
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
2.3 2.5
0.4
0.1
µs During readout
Hφ1
18
23
21
26
10 17.5
10 17.5
Hφ2
21
26
18
23
10
10
During parallel- Hφ1
serial conversion Hφ2
Reset gate clock
φRG
11
Substrate clock
φSUB
1.4 1.6
14
49
Remarks
400 ns ∗1
15
15
Unit
0.01
0.01
0.01
0.01
2
2
0.4
15
ns ∗2
µs
ns
0.4 µs
Vertical final stage VHOLDφ
accumulation/
VOGφ
transfer clock
20
20
ns
20
20
ns
HHGφ1
Inter-horizontal
register transfer clock HHGφ2
20
20
ns
20
20
ns
During drain
charge
∗1 When vertical transfer clock driver CXD1268M is used.
∗2 tf ≥ tr – 2ns, and the cross-point voltage (VCR) for the Hφ1 rising side of the Hφ1 and Hφ2 waveforms must be
at least 2.5V.
two
Item
Horizontal
transfer clock
Symbol
Min. Typ. Max.
Hφ1, Hφ2 20
24
Unit
ns
Remarks
∗3
∗3 The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two.
– 10 –
ICX075AL
Image Sensor Characteristics
Item
(Ta = 25°C)
Symbol
Min.
Typ.
300
Max.
Unit
Measurement method
mV
1
mV
2
0.007
%
3
Remarks
Sensitivity
S
230
Saturation signal
Vsat
375
Smear
Sm
Video signal shading
SH
25
%
4
Zone 0
Dark signal
Vdt
2
mV
5
Ta = 60°C
Dark signal shading
∆Vdt
1
mV
6
Ta = 60°C
Lag
Lag
0.5
%
7
Uniformity between output
channels
∆V
3
%
8
0.003
Ta = 60°C
Note) All the characteristic data of this image sensor was yielded when the sensor was operated in the 1/50s
interlaced mode.
Zone Definition of Video Signal Shading
782 (H)
6
6
2
582 (V)
Zone 0
2
Ignored region
Effective pixel region
Measurement System
CCD signal output 1
[∗A]
[∗C]
C.D.S
AMP
S/H
C.D.S
AMP
S/H
Signal output 1
CCD
[∗B]
Signal output 2
[∗D]
CCD signal output 2
Note) Adjust the amplifier gain so that the gain between [∗A] and [∗C], and between [∗B] and [∗D] equals 1.
– 11 –
ICX075AL
Readout modes
The output methods for the two readout modes indicated below are now described.
AAA
1/50s interlaced
Odd field
VOUT1
VOUT2
Even field
AAA
1/25s non-interlaced
AAA
VOUT1
VOUT2
VOUT1
VOUT2
1. 1/50s interlaced
In this mode, the signals are output in a 1/50s period using the two output pins (VOUT1, VOUT2).
The signals from two adjacent horizontal lines are simultaneously output from the respective output pins.
The lines output from the output pins are changed over with each field. The VOUT1 signal after it has passed
through the CDS and other external circuits or the signal produced by adding the VOUT1 and VOUT2 signals
accommodate interlaced scanning.
2. 1/25s non-interlaced
In this mode, the signals are output in a 1/25s period using only one output pin (VOUT1).
Unlike the 1/50s interlaced mode described above, the external circuit can be simplified. The imaging
characteristics also differ from those of the other modes.
– 12 –
ICX075AL
Image Sensor Characteristics Measurement Method
Measurement conditions
1) In the following measurements, the substrate voltage is set to the value indicated on the device, and the
device drive conditions are at the typical values of the bias and clock voltage conditions.
2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical
black level (OB) is used as the reference for the signal output and the value measured at point [∗A] in the
measurement system is used.
3) In the following measurements, this image sensor is operated in 1/50s interlaced mode.
Definition of standard imaging conditions
1) Standard imaging condition I:
Use a pattern box (luminance 706cd/m2, color temperature of 3200K halogen source) as a subject.
(Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.00mm) as an IR
cut filter and image at F8. The luminous intensity to the sensor receiving surface at this point is defined as
the standard sensitivity testing luminous intensity.
2) Standard imaging condition II:
Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles.
Use a testing standard lens with CM500S (t = 1.00mm) as an IR cut filter. The luminous intensity is
adjusted to the value indicated in each testing item by the lens diaphragm.
1. Sensitivity
Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of
1/250s, measure the signal output (Vs) at the center of the screen and substitute the value into the
following formula.
S = Vs ×
250
[mV]
50
2. Saturation signal
Set to standard imaging condition II. After adjusting the luminous intensity to 10 times the intensity with
average value of signal output, 120mV, measure the minimum value of the signal output.
3. Smear
Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity to
500 times the intensity with average value of signal output, 120mV. When the readout clock is stopped and
the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum
value VSm [mV] of the signal output and substitute the value into the following formula.
Sm =
1
VSm
1
×
×
× 100 [%] (1/10V method conversion value)
10
120
500
4. Video signal shading
Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity
so that the average value of the signal output is 120mV. Then measure the maximum (Vmax [mV]) and
minimum (Vmin [mV]) values of the signal output and substitute the values into the following formula.
SH = (Vmax – Vmin)/120 × 100 [%]
5. Dark signal
Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature 60°C and
the device in the light-obstructed state, using the horizontal idle transfer level as a reference.
– 13 –
ICX075AL
6. Dark signal shading
After measuring 5, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark
signal output and substitute the values into the following formula.
∆Vdt = Vdmax – Vdmin [mV]
7. Lag
Adjust the signal output value generated by strobe light to 120mV. After setting the strobe light so that it
strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the following
formula.
Lag = (Vlag/120) × 100 [%]
FLD
SG
Light
Strobe light
timing
Signal output 120mV
Vlag (lag)
Output
8. Uniformity between output channels
Set to standard imaging condition I. Measure the signals at signal output 1 (V1) and at signal output 2 (V2),
and substitute the values into the following formula.
∆V =
| V2 – V1 |
× 100 [%]
V1
– 14 –
– 15 –
RG
XHφ1
XHφ2
XSUB
XVHOLD
XHHG1-1
XHHG1-2
XHHG2-1
XHHG2-2
XVOG
XV1
XV3
XV2
XSG
5V
–7.5V
22/10V
22
/16V
22/16V
10
8
9
1
2
3
4
5
6
7
9
10
N.C. 7
8
CXD1250
CXD1268M
22/10V
14
13
12
11
18
17
16
15
20
19
15
14
13
12
11
18
17 N.C.
16
22/16V
1/35V
10/20V
22/20V
100k
3.3/16V
1/10V
1/35V
1/35V
1 2 3 4 5 6 7 8 9 10 11
HIGφ1
HIS
ICX075
(BOTTOM VIEW)
0.01
HC04
HC04
1/20V
100
22 21 20 19 18 17 16 15 14 13 12
VOGφ
POGφ
20
19
HIG2
HHGφ2
HHGφ1
Hφ2
Hφ1
1
N.C. 2
3
4
5
6
56k
Vφ3
Vφ2
Vφ1
VHOLDφ
GND
CGG1
VOUT1
CGG2
SUB
VL
RG
15V
VOUT2
VDD
Drive Circuit
3.3/20V
2SK523
1/10V
2SK523
27k
0.1
0.01
3.9k
100
3.9k
100
0.1
0.1
270k
39
2SC2785 × 3
1M
15k
47k
15k
[∗B]
CCD OUT2
[∗A]
CCD OUT1
ICX075AL
ICX075AL
Spectral Sensitivity Characteristics
(includes lens characteristics, excludes light source characteristics)
1.0
0.9
0.8
Relative Response
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
400
500
600
700
800
900
1000
Wave Length [nm]
Sensor Readout Clock Timing Chart
1/50s interlaced mode
HD
V1
Odd Field
V2
V3
43.25
2.58 2.58
3.25
V1
Even Field
V2
V3
Unit: µs
– 16 –
CCD
OUT2
SG
CCD
OUT1
V3
V2
V1
HD
BLK
VD
FLD
246 8 24 6 8
13 57 1 35 7
581
1/50s interlaced mode
625
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
582
– 17 –
581
335
1 35 7 1 3 57
2 4 6 8 2 4 6 8
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
582
Drive Timing Chart (Vertical Sync)
ICX075AL
340
– 18 –
SUB
SHD
SHP
RG
H2
H1
HHG2
HHG1
VHOLD
VOG
V3
V2
V1
CLK
BLK
HD
Drive Timing Chart (Horizontal Sync)
1/50s interlaced mode
ICX075AL
ICX075AL
Notes on Handling
1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non-chargeable gloves, clothes or material.
Also use conductive shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensor.
e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.
2) Soldering
a) Make sure the package temperature does not exceed 80°C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W
soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently.
c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering
tool, use a thermal controller of the zero cross On/Off type and connect it to ground.
3) Dust and dirt protection
Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and
dirt. Clean glass plates with the following operation as required, and use them.
a) Perform all assembly operations in a clean room (class 1000 or less).
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should
dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized
air is recommended.)
c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass.
d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when
moving to a room with great temperature differences.
e) When a protective tape is applied before shipping, just before use remove the tape applied for
electrostatic protection. Do not reuse the tape.
4) Installing (attaching)
a) Remain within the following limits when applying a static load to the package. Do not apply any load more
than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited
portions. (This may cause cracks in the package.)
AAAA AAAA AAAA AAAA
AAAA AAAA AAAA AAAA
Upper ceramic
Lower ceramic
39N
29N
29N
0.9Nm
Low melting
point glass
Compressive strength
Shearing strength
Tensile strength
Torsional strength
b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the
package may fracture, etc., depending on the flatness of the ceramic portions. Therefore, for installation,
use either an elastic load, such as a spring plate, or an adhesive.
– 19 –
ICX075AL
c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated
voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area,
and indicated values should be transferred to other locations as a precaution.
d) The upper and lower ceramic are joined by low melting point glass. Therefore, care should be taken not
to perform the following actions as this may cause cracks.
• Applying repeated bending stress to the outer leads.
• Heating the outer leads for an extended period with a soldering iron.
• Rapidly cooling or heating the package.
• Applying any load or impact to a limited portion of the low melting point glass using tweezers or other
sharp tools.
• Prying at the upper or lower ceramic using the low melting point glass as a fulcrum.
Note that the same cautions also apply when removing soldered products from boards.
e) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyanoacrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives.
(reference)
5) Others
a) Do not expose to strong light (sun rays) for long periods. For continuous using under cruel condition
exceeding the normal using condition, consult our company.
b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or
usage in such conditions.
– 20 –
– 21 –
7.55
1
V
22
Cer-DIP
TIN PLATING
42 ALLOY
2.6g
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
0.3
M
14.6
18.0 ± 0.4
H
9.0
0.69
(For the 1st. pin only) 1.27
PACKAGE STRUCTURE
B
0.7
3
0.55
3
11.55
3
11
12
A
0.46
0.3
B'
C
1
11
17.6
22
12
2-R0.7
9. The notches on the bottom must not be used for reference of fixing.
8. The thickness of the cover glass is 0.75mm, and the refractive index is 1.5.
7. The tilt of the effective image area relative to the bottom “C” is less than 60µm.
6. The height from the bottom “C” to the effective image area is 1.41 ± 0.15mm.
5. The rotation angle of the effective image area relative to H and V is ± 1°.
4. The center of the effective image area, relative to “B” and “B'” is
(H, V) = (9.0, 7.55) ± 0.15mm.
3. The bottom “C” of the package is the height reference.
2. The two points “B” of the package are the horizontal reference.
The point “B'” of the package is the vertical reference.
1. “A” is the center of the effective image area.
22pin DIP (600mil)
15.1 ± 0.3
0.7
Unit: mm
1.27
15.24
3.4 ± 0.3
4.0 ± 0.3
0° to 9°
0.25
Package Outline
ICX075AL