ICX099AL 1/2-inch Progressive Scan CCD Image Sensor with Square Pixel for B/W Cameras For the availability of this product, please contact the sales office. Description The ICX099AL is a 1/2-inch optical interline CCD solid-state image sensor with a square pixel array and 800K effective pixels. Progressive scan allows all pixels' signals to be output independently within approximately 1/15 second. Also, the adoption of high-speed mode supports 30 frames per second. This chip features an electronic shutter with variable charge-storage time which makes it possible to realize high resolution, full-frame still image without a mechanical shutter. Further, high sensitivity and low dark current are achieved through the adoption of HAD (Hole-Accumulation Diode) sensors. This chip is suitable for applications such as high resolution cameras for FA, etc. Features • Progressive scan allows individual readout of the image signals from all pixels. • High horizontal and vertical resolution still image without a mechanical shutter. • Supports 30 frames per second mode • Square pixel • Horizontal drive frequency: 14.31818MHz • No voltage adjustments (reset gate and substrate bias are not adjusted.) • High resolution, high sensitivity, low dark current • Continuous variable-speed shutter • Low smear • Excellent antiblooming characteristics Device Structure • Interline CCD image sensor • Optical size: • Number of effective pixels: • Total number of pixels: • Chip size: • Unit cell size: • Optical black: • Number of dummy bits: • Substrate material: 20 pin DIP (Cer-DIP) AAAAA AAAAA AAAAA AAAAA AAAAA Pin 1 2 V 3 Pin 11 H 7 40 Optical black position (Top View) 1/2-inch format 1034 (H) × 779 (V) approx. 800K pixels 1077 (H) × 788 (V) approx. 850K pixels 7.60mm (H) × 6.20mm (V) 6.25µm (H) × 6.25µm (V) Horizontal (H) direction: Front 3 pixels, rear 40 pixels Vertical (V) direction: Front 7 pixels, rear 2 pixels Horizontal 29 Vertical 1 Silicon Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E97747-PS 4 Vφ1 5 NC 6 Vφ2A 7 NC Vφ3 8 Vφ2B GND 9 GND 10 3 2 1 Vertical register NC Block Diagram and Pin Configuration (Top View) VOUT ICX099AL Note) Note) Pin No. Symbol 12 13 14 15 16 17 18 19 20 VDD φSUB CSUB NC NC VL φRG Hφ1 Hφ2 Pin Description 11 GND Horizontal register Description Pin No. Symbol : Photo sensor Description 1 Vφ1 Vertical register transfer clock 11 VDD Supply voltage 2 Vφ2A Vertical register transfer clock 12 GND GND 3 NC 13 φSUB 4 Vφ2B 14 CSUB Substrate clock Substrate bias∗1 5 NC 15 NC 6 Vφ3 Vertical register transfer clock 16 NC 7 GND GND 17 VL Protective transistor bias 8 GND GND 18 φRG Reset gate clock 9 NC 19 Hφ1 Horizontal register transfer clock 10 VOUT 20 Hφ2 Horizontal register transfer clock Vertical register transfer clock Signal output ∗1 DC bias is generated within the CCD, so that this pin should be grounded externally through a capacitance of 0.1µF. Absolute Maximum Ratings Item Against φSUB Ratings Unit VDD, VOUT, φRG – φSUB –40 to +10 V Vφ2A, Vφ2B – φSUB –50 to +15 V Vφ1, Vφ3, VL – φSUB –50 to +0.3 V Hφ1, Hφ2, GND – φSUB –40 to +0.3 V –25 to V VDD, VOUT, φRG, CSUB – GND –0.3 to +18 V Vφ1, Vφ2A, Vφ2B, Vφ3 – GND –10 to +18 V Hφ1, Hφ2 – GND –10 to +5 V Vφ2A, Vφ2B – VL –0.3 to +28 V Vφ1, Vφ3, Hφ1, Hφ2, GND – VL –0.3 to +15 V to +15 V CSUB – φSUB Against GND Against VL Voltage difference between vertical clock input pins Between input Hφ1 – Hφ2 clock pins Hφ1, Hφ2 – Vφ3 –5 to +5 V –13 to +13 V Storage temperature –30 to +80 °C –10 to +60 °C Operating temperature ∗2 +24V (Max.) when clock width < 10µs, clock duty factor < 0.1%. –2– Remarks ∗2 ICX099AL Bias Conditions Item Symbol Min. Typ. Max. Unit 14.55 15.0 ∗1 15.45 V Supply voltage VDD Protective transistor bias VL Substrate clock φSUB ∗2 Reset gate clock φRG ∗2 Remarks ∗1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL power supply for the V driver should be used. ∗2 Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated within the CCD. DC Characteristics Item Symbol Min. Typ. IDD Supply current Max. 6.0 Remarks Unit mA Clock Voltage Conditions Min. Typ. Max. Unit Waveform diagram VVT 14.55 15.0 15.45 V 1 VVH02A –0.05 0 0.05 V 2 VVH1, VVH2A, VVH2B, VVH3 –0.2 0 0.05 V 2 VVL1, VVL2A, VVL2B, VVL3 –5.8 –5.5 –5.2 V 2 Vφ1, Vφ2A, Vφ2B, Vφ3 5.2 5.5 5.8 V 2 | VVL1 – VVL3 | 0.1 V 2 VVHH 0.3 V 2 High-level coupling VVHL 1.0 V 2 High-level coupling VVLH 0.5 V 2 Low-level coupling VVLL 0.5 V 2 Low-level coupling Item Readout clock voltage Vertical transfer clock voltage Horizontal transfer clock voltage Symbol Substrate clock voltage VVH = VVH02A VVL = (VVL1+VVL3)/2 VφH 4.75 5.0 5.25 V 3 VHL –0.05 0 0.05 V 3 3.0 3.3 5.5 V 4 VRGLH – VRGLL 0.4 V 4 Low-level coupling VRGL – VRGLm 0.5 V 4 Low-level coupling 21.25 V 5 VφRG Reset gate clock voltage Remarks VφSUB 19.75 20.5 –3– ICX099AL Clock Equivalent Circuit Constant Symbol Item Capacitance between vertical transfer clock and GND Capacitance between vertical transfer clocks Min. Typ. Max. Unit CφV1 2200 pF CφV2A, CφV2B 1800 pF CφV3 6800 pF CφV12A, CφV2B1 1200 pF CφV2A3, CφV32B 1000 pF CφV13 1500 pF Capacitance between horizontal transfer clock and GND CφH1, CφH2 56 pF Capacitance between horizontal transfer clocks CφHH 120 pF Capacitance between reset gate clock and GND CφRG 10 pF Capacitance between substrate clock and GND CφSUB 400 pF Vertical transfer clock series resistor R1, R2A, R2B, R3 30 Ω Vertical transfer clock ground resistor RGND 30 Ω Horizontal transfer clock series resistor RφH 20 Ω Horizontal transfer clock ground resistor RH2 20 kΩ Vφ1 Remarks Vφ2A CφV12A R1 R2A RφH RφH Hφ1 CφV1 Hφ2 CφHH CφV2A CφV2B1 CφV2A3 CφH1 CφH2 RH2 CφV13 CφV2B R2B Vφ2B RGND CφV3 CφV32B R3 Vφ3 Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit –4– ICX099AL Drive Clock Waveform Conditions (1) Readout clock waveform VT 100% 90% II II φM VVT φM 2 10% 0% tr twh 0V tf Note) Readout clock is used by composing vertical transfer clocks Vφ2A and Vφ2B. (2) Vertical transfer clock waveform Vφ1 VVH1 VVHH VVH VVHL VVLH VVL01 VVL1 VVL VVLL Vφ2A, Vφ2B VVH02A, VVH02B VVH2A, VVH2B VVHH VVH VVHL VVLH VVL2A, VVL2B VVL VVLL Vφ3 VVH3 VVHH VVH VVHL VVLH VVL03 VVL VVLL VVH = VVH02A VVL = (VVL01 + VVL03) /2 VVL3 = VVL03 VφV1 = VVH1 – VVL01 VφV2A = VVH02A – VVL2A VφV2B = VVH02B – VVL2B VφV3 = VVH3 – VVL03 –5– ICX099AL (3) Horizontal transfer clock waveform tr twh tf Hφ2 90% VCR VφH twl VφH 2 10% VHL Hφ1 two Cross-point voltage for the Hφ1 rising side of the horizontal transfer clocks Hφ1 and Hφ2 waveforms is VCR. The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two. (4) Reset gate clock waveform tr twh tf VRGH RG waveform twl VφRG Point A VRGLH VRGLL VRGLm VRGL VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL. VRGL = (VRGLH + VRGLL)/2 Assuming VRGH is the minimum value during the interval twh, then: VφRG = VRGH – VRGL Negative overshoot level during the falling edge of RG is VRGLm. (5) Substrate clock waveform 100% 90% φM φM 2 VφSUB 10% 0% VSUB (A bias generated within the CCD) tr twh –6– tf ICX099AL Clock Switching Characteristics Item Symbol VT Vertical transfer clock Vφ1, Vφ2A, Vφ2B, Vφ3 Horizontal transfer clock Readout clock During imaging twh twl tr tf Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. 2.3 2.5 0.5 0.5 15 350 Hφ1 19 24 21 26 10 15 10 15 Hφ2 21 26 19 24 10 15 10 15 During Hφ1 parallel-serial Hφ2 conversion Reset gate clock φRG 11 Substrate clock φSUB 1.5 1.8 13 51 0.01 0.01 0.01 0.01 3 3 0.5 Unit Remarks µs During readout ns ∗1 ns ∗2 µs ns 0.5 µs During drain charge ∗1 When vertical transfer clock driver CXD1267AN × 2 are used. ∗2 tf ≥ tr – 2ns, and the cross-point voltage (VCR) for the Hφ1 rising side of the Hφ1 and Hφ2 waveforms must be at least VφH/2 [V]. two Item Symbol Horizontal transfer clock Hφ1, Hφ2 Min. Typ. Max. 16 20 Unit Remarks ns Spectral Sensitivity Characteristics (excludes lens characteristics and light source characteristics) 1 0.9 0.8 Relative Response 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 400 500 600 700 Wave Length [nm] –7– 800 900 1000 ICX099AL Image Sensor Characteristics (Ta = 25°C) Symbol Min. Typ. Sensitivity S 480 600 Saturation signal Vsat 500 Smear Sm Video signal shading SH Dark signal Item Max. Unit Measurement method Remarks mV 1 1/30s accumulation mode mV 2 Ta = 60°C 0.0025 % 3 1/15s accumulation mode 20 % 4 Zone 0 and I 25 % 4 Zone 0 to II' Vdt 8 mV 5 Ta = 60°C Dark signal shading ∆Vdt 2 mV 6 Ta = 60°C Lag Lag 0.5 % 7 0.001 Zone Definition of Video Signal shading 1034 (H) 12 H 8 12 12 V 10 H 8 Zone 0, I Zone II, II' V 10 779 (V) 10 Ignored region Effective pixel region Measurement System CCD signal output [∗A] CCD C.D.S AMP Signal output [∗B] S/H Note) Adjust the amplifier gain so that the gain between [∗A] and [∗B] equals 1. –8– ICX099AL Image Sensor Characteristics Measurement Method Readout modes The diagram below shows the output methods for the following two readout modes. High-speed mode Progressive scan mode VOUT 7 7 6 6 5 5 4 4 3 3 2 2 1 1 VOUT Note) Blacked out portions in the diagram indicate pixels which are not read out. 1. Progressive scan mode In this mode, all pixel signals are output in non-interlace format in 1/15s. The vertical resolution is approximately 760TV-lines and all pixel signals within the same exposure period are read out simultaneously, making this mode suitable for high resolution image capturing. 2. High-speed mode The signals for all effective areas are output in approximately 1/30s by repeating readout pixels and nonreadout pixels every two lines. The vertical resolution is approximately 380TV-lines. This readout mode emphasizes processing speed over vertical resolution. –9– ICX099AL Measurement conditions 1) In the following measurements, the device drive conditions are at the typical values of the bias and clock voltage conditions. 2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical black level (OB) is used as the reference for the signal output, which is taken as the value measured at point [∗B] of the measurement system. Definition of standard imaging conditions 1) Standard imaging condition I: Use a pattern box (luminance : 706cd/m2, color temperature of 3200K halogen source) as a subject. (pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter and image at F8. The luminous intensity to the sensor receiving surface at this point is defined as the standard sensitivity testing luminous intensity. 2) Standard imaging condition II: Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles. Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm. 1. Sensitivity Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of 1/250s, measure the signal output (VS) at the center of the screen, and substitute the value into the following formula. S = VS × 250 [mV] 30 2. Saturation signal Set to standard imaging condition II. After adjusting the luminous intensity to 10 times the intensity with the average value of the signal output, 150mV, measure the minimum value of the signal output. 3. Smear Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, first adjust the luminous intensity to 500 times the intensity with the average value of the signal output, 150mV. Then after the readout clock is stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum value (Vsm [mV]) of the signal output and substitute the value into the following formula. Sm = Vsm 1 1 × × 150 500 10 × 100 [%] (1/10V method conversion value) 4. Video signal shading Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so that the average value of the signal output is 150mV. Then measure the maximum (Vmax [mV]) and minimum (Vmin [mV]) values of the signal output and substitute the values into the following formula. SH = (Vmax – Vmin)/150 × 100 [%] 5. Dark signal Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature 60°C and the device in the light-obstructed state, using the horizontal idle transfer level as a reference. – 10 – ICX099AL 6. Dark signal shading After measuring 5, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark signal output and substitute the values into the following formula. ∆Vdt = Vdmax – Vdmin [mV] 7. Lag Adjust the signal output value generated by strobe light to 150mV. After setting the strobe light so that it strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the following formula. Lag = (Vlag/150) × 100 [%] VD V2A Light Strobe light timing Signal output 150mV Output – 11 – Vlag (Lag) H2 H1 RG XSUB XV3 XV2B XSG2 XV1 XV2A XSG1 –5.5V 15V 22/20V 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 CXD1267AN CXD1267AN 20 19 18 17 16 15 14 13 12 11 20 19 18 17 16 15 14 13 12 11 1/35V 100k 1/20V 0.1 22/16V 1 2 3 4 5 6 7 8 9 10 (Bottom View) ICX099 Vφ1 Vφ2A NC Vφ2B NC Vφ3 GND GND NC VOUT 1M 0.1 2200p 22/20V Hφ2 Hφ1 φRG VL NC NC CSUB φSUB GND VDD – 12 – 20 19 18 17 16 15 14 13 12 11 Drive Circuit 3.9k 0.01 CCD OUT 2SK523 100 ICX099AL ICX099AL Sensor Readout Clock Timing Chart Progressive Scan Mode XV1 XV2A XV2B XV3 XSG1 XSG2 Sensor readout clocks XSG1 and XSG2 are used by composing XV2A and XV2B. 69.8ns (1 bit) HD 2.51µs (36 bits) 42.2µs (604 bits) V1 V2A V2B V3 – 13 – ICX099AL Sensor Readout Clock Timing Chart High-speed Mode XV1 XV2A XV2B XV3 XSG1 XSG2 Sensor readout clock XSG1 is used by composing XV2A. 69.8ns (1 bit) HD 2.51µs (36 bits) 42.2µs (604 bits) V1 V2A V2B V3 – 14 – – 15 – CCD OUT V3 V2B V2A V1 HD VD Drive Timing Chart (Vertical Sync) 778 779 794 Progressive Scan Mode 800 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 1 2 3 4 5 6 7 401 785 778 779 787 790 795 800 1 2 3 1 2 3 4 5 6 7 1 2 3 ICX099AL – 16 – CCD OUT V3 V2B V2A V1 HD VD Drive Timing Chart (Vertical Sync) 765 766 769 770 773 774 777 778 High-speed Mode 389 390 391 392 393 394 395 396 397 398 399 400 1 2 3 4 5 6 7 8 9 10 11 12 1 4 5 1 2 5 6 9 10 13 765 766 769 770 773 774 777 778 388 389 390 391 392 393 394 395 396 397 398 399 400 1 2 3 4 5 6 7 8 9 10 11 12 1 4 5 1 2 5 6 9 10 13 765 766 769 770 773 774 777 778 388 389 390 391 392 393 394 395 396 397 398 399 400 1 2 3 4 5 6 7 8 9 10 11 12 1 4 5 1 2 5 6 9 10 13 ICX099AL – 17 – SHD SHP RG SUB V3 V2B V2A V1 H2 H1 CLK HD 5 bits rear OPB 40 bits 1 2 3 4 Progressive Scan Mode 5 6 7 8 9 10 11 12 dummy 29 bits front OPB 3 bits 165 1197 Drive Timing Chart (Horizontal Sync) 5 bits ICX099AL – 18 – SHD SHP RG SUB V3 V2B V2A V1 H2 H1 CLK HD 5 bits rear OPB 40 bits 1 2 3 High-speed Mode 4 5 6 7 8 9 10 11 12 dummy 29 bits front OPB 3 bits 165 1197 Drive Timing Chart (Horizontal Sync) 5 bits ICX099AL ICX099AL Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges. 2) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering tool, use a thermal controller of the zero cross On/Off type and connect it to ground. 3) Dust and dirt protection Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and dirt. Clean glass plates with the following operation as required, and use them. a) Perform all assembly operations in a clean room (class 1000 or less). b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. e) When a protective tape is applied before shipping, just before use remove the tape applied for electrostatic protection. Do not reuse the tape. 4) Installing (attaching) a) Remain within the following limits when applying a static load to the package. Do not apply any load more than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited portions. (This may cause cracks in the package.) AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA Upper ceramic Lower ceramic 39N 29N 29N 0.9Nm Low melting point glass Compressive strength Shearing strength Tensile strength Torsional strength b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portions. Therefore, for installation, use either an elastic load, such as a spring plate, or an adhesive. – 19 – ICX099AL c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area, and indicated values should be transferred to other locations as a precaution. d) The upper and lower ceramic are joined by low melting point glass. Therefore, care should be taken not to perform the following actions as this may cause cracks. • Applying repeated bending stress to the outer leads. • Heating the outer leads for an extended period with a soldering iron. • Rapidly cooling or heating the package. • Applying any load or impact to a limited portion of the low melting point glass using tweezers or other sharp tools. • Prying at the upper or lower ceramic using the low melting point glass as a fulcrum. Note that the same cautions also apply when removing soldered products from boards. e) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyanoacrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives. (reference) 5) Others a) Do not expose to strong light (sun rays) for long periods. For continuous using under cruel condition exceeding the normal using condition, consult our company. b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. – 20 – – 21 – 3 0.55 ~ ~ 3 11.55 TIN PLATING 42 ALLOY 2.6g LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT 0.3 M 1.778 3 14.6 11 10 A 18.0 ± 0.4 H 0.4 V Cer-DIP 1 20 9.0 PACKAGE MATERIAL PACKAGE STRUCTURE B 0.7 7.55 0.4 0.83 15.1 ± 0.3 B' 0.8 0.46 0.7 C 0° to 9° 1.4 10 11 (R0.7) (1.0) 17.6 φ1.4 1 20 (1.7) 9. The notch and the hole on the bottom must not be used for reference of fixing. 8. The thickness of the cover glass is 0.75mm, and the refractive index is 1.5. 7. The tilt of the effective image area relative to the bottom “C” is less than 60µm. 6. The height from the bottom “C” to the effective image area is 1.41 ± 0.15mm. 5. The rotation angle of the effective image area relative to H and V is ± 1°. 4. The center of the effective image area, relative to “B” and “B'” is (H, V) = (9.0, 7.55) ± 0.15mm. 3. The bottom “C” of the package is the height reference. 2. The two points “B” of the package are the horizontal reference. The point “B'” of the package is the vertical reference. 1. “A” is the center of the effective image area. 0.25 20pin DIP (600mil) 1.27 15.24 3.4 ± 0.3 4.0 ± 0.3 (4.0) Unit: mm ~ Package Outline ICX099AL